JPS6364330A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6364330A JPS6364330A JP61210317A JP21031786A JPS6364330A JP S6364330 A JPS6364330 A JP S6364330A JP 61210317 A JP61210317 A JP 61210317A JP 21031786 A JP21031786 A JP 21031786A JP S6364330 A JPS6364330 A JP S6364330A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- recess
- semiconductor
- area
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 239000000463 material Substances 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、半導体素子と半導体
素子載置部との接合構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a bonding structure between a semiconductor element and a semiconductor element mounting portion.
〔従来の技４＋ｊ ）
第３図、第５図は従来の半導体装置の半導体素子載置部
付近を示す平面図であり、第４図は第３図のＴＶ −Ｉ
Ｖ線断面であり、第６図は第５図の■−■線断面図であ
る。第３図〜第６図において、１は半導体素子、２は半
導体素子載置部、３は半導体素子１と半導体素子載置部
２とを接合する接合材、４は配線材、５は外部端子であ
る。[Conventional Technique 4+j] FIGS. 3 and 5 are plan views showing the vicinity of the semiconductor element mounting portion of a conventional semiconductor device, and FIG.
This is a cross-sectional view taken along the line V, and FIG. 6 is a cross-sectional view taken along the line ■--■ in FIG. 3 to 6, 1 is a semiconductor element, 2 is a semiconductor element mounting part, 3 is a bonding material for joining the semiconductor element 1 and the semiconductor element mounting part 2, 4 is a wiring material, and 5 is an external terminal. It is.
従来の半導体装置は以上のように構成されているので、
半導体素子１が大型化して熱放散性改善のために銅系の
半導体素子載置部を用いた場合、半導体素子と熱膨張係
数が大きく異なるため、第４図に示すように半導体素子
１の全面を接合材３で接合すると、接合後、温度変化に
伴い熱応力が発生し、半導体素子１に割れが生じるとい
う問題があった。Conventional semiconductor devices are configured as described above, so
When the semiconductor element 1 becomes larger and a copper-based semiconductor element mounting part is used to improve heat dissipation, the entire surface of the semiconductor element 1 as shown in FIG. When these are bonded using the bonding material 3, there is a problem in that thermal stress is generated due to temperature changes after bonding, and the semiconductor element 1 is cracked.
この割れを防止するため、第５図および第６図に示すよ
うに半導体素子１を部分的に接合すると、半導体素子１
が傾いたり、半導体素子１が半導体素子載置部２から浮
いている部分があるため配線材４０半専体素子１への接
合が安定してできないというような問題があった。In order to prevent this cracking, if the semiconductor element 1 is partially bonded as shown in FIGS. 5 and 6, the semiconductor element 1
There have been problems in that the wiring material 40 cannot be stably bonded to the semi-dedicated element 1 because the semiconductor element 1 is tilted and there is a part where the semiconductor element 1 is floating from the semiconductor element mounting part 2.
本発明はこのような点に濫みてなされたものであり、そ
の目的とするところは、半導体素子にかかる応力を緩和
し、半導体素子が半導体素子載置部に対して傾いたり浮
いたりしない半導体装置を得ることにある。The present invention has been made in view of these points, and its purpose is to provide a semiconductor device in which the stress applied to the semiconductor element is alleviated, and the semiconductor element does not tilt or float with respect to the semiconductor element mounting part. It's about getting.
このような目的を達成するために本発明は、半導体素子
と半導体素子載置部とを有する半導体装置において、半
導体素子載置部の半導体素子を載置する面に半導体素子
より小さい面積の凹部を設け、半導体素子と半導体素子
載置部とを凹部に入れた接合材で接合するようにしたも
のである。In order to achieve such an object, the present invention provides a semiconductor device having a semiconductor element and a semiconductor element mounting part, in which a recess having an area smaller than the semiconductor element is formed on the surface of the semiconductor element mounting part on which the semiconductor element is placed. The semiconductor element and the semiconductor element mounting part are bonded together using a bonding material placed in the recess.
本発明においては、半導体素子が半導体素子載置部に対
して傾いたり浮いたりすることはない。In the present invention, the semiconductor element does not tilt or float with respect to the semiconductor element mounting portion.
〔実施例〕 本発明に係わる半導体装置の一実施例を第１図に示す。〔Example〕 An embodiment of a semiconductor device according to the present invention is shown in FIG.
第２図は第１図の■−■線断面図である。FIG. 2 is a sectional view taken along the line ■--■ in FIG.
第１図および第２図において、６は四部であり、第３図
および第４図と同一部分又はｔｌｌ当部分（こ１ま同一
符号が付しである。第１図および第２図に示す半導体素
子載置部２コこは、半導体素子１より小さな面積の四部
が１つ設けられており、半導体素子１と半導体素子裁置
部２との接合面積は４×４ｍｍ２以下で半導体素子１０
表面積より小さい面積である。In Figs. 1 and 2, 6 indicates four parts, which are the same parts as in Figs. The semiconductor element mounting part 2 is provided with one four parts each having a smaller area than the semiconductor element 1, and the bonding area between the semiconductor element 1 and the semiconductor element mounting part 2 is 4 x 4 mm2 or less, and the semiconductor element 10 is
The area is smaller than the surface area.
本実施例においては、半導体素子１と凹部６との接合面
積が４．Ｘ４ｍｍ２以下で半導体素子１の表面積より小
さい面積であるため、熱膨張係数の違いにより生しる応
力を緩和できる。In this embodiment, the bonding area between the semiconductor element 1 and the recess 6 is 4. Since the area is smaller than the surface area of the semiconductor element 1, which is less than X4 mm2, stress caused by the difference in coefficient of thermal expansion can be alleviated.
また、半導体素子載置部２の凹部６に入れた接合材３で
半４体素子１を接合しているため、半導体素子１が半導
体素子裁置部２に対して傾いたりン♀いたりすることが
ない。Furthermore, since the half-quad elements 1 are bonded with the bonding material 3 placed in the recess 6 of the semiconductor element mounting section 2, the semiconductor element 1 may be tilted or turned against the semiconductor element mounting section 2. There is no.
以上説明したように本発明は、半導体素子載置部に半導
体素子より小さい面積の凹部を設け、この凹部に入れた
接合材で半導体素子を接合したことにより、半導体素子
と凹部との接合面積を半導体素子より小さい面積とする
ことができたので、熱膨張係数の違いにより半導体素子
にかかる応力を凄和でき、半導体素子が半導体素子裁置
部に対して傾いたり浮いたりしない効果がある。As explained above, the present invention provides a recess with a smaller area than the semiconductor element in the semiconductor element mounting part and joins the semiconductor element with the bonding material placed in the recess, thereby reducing the bonding area between the semiconductor element and the recess. Since the area can be made smaller than that of the semiconductor element, the stress applied to the semiconductor element due to the difference in coefficient of thermal expansion can be reduced, and there is an effect that the semiconductor element does not tilt or float with respect to the semiconductor element placement section.
第１図および第２図は本発明に係わる半導体装置の一実
施例を示す平面図および断面図、第３図および第４図は
従来の半導体装置を示す平面図および断面図、第５図お
よび第６図はさらに別の従来の半導体装置を示す平面図
および断面図である。
１・・・半導体素子、２・・・半導体素子裁置部、３・
・・接合材、４・・・配線材、５・・・外部端子、６・
・・凹部。1 and 2 are a plan view and a sectional view showing an embodiment of a semiconductor device according to the present invention, FIGS. 3 and 4 are a plan view and a sectional view showing a conventional semiconductor device, and FIGS. FIG. 6 is a plan view and a sectional view showing still another conventional semiconductor device. 1... Semiconductor element, 2... Semiconductor element placement section, 3.
・・Joining material, 4・Wiring material, 5・External terminal, 6・
・Concavity.
Claims (2)
装置において、前記半導体素子載置部の前記半導体素子
を載置する面に前記半導体素子より小さい面積の凹部を
備え、前記半導体素子と前記半導体素子載置部とを前記
凹部に入れた接合材で接合したことを特徴とする半導体
装置。(1) In a semiconductor device having a semiconductor element and a semiconductor element mounting part, a recessed part having an area smaller than the semiconductor element is provided on a surface of the semiconductor element mounting part on which the semiconductor element is placed, and the semiconductor element and the A semiconductor device, characterized in that the semiconductor element mounting portion is bonded to the semiconductor device mounting portion using a bonding material placed in the recess.
が４×４ｍｍ＾２以下であることを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein there is only one recessed portion, and the area in contact with the semiconductor element is 4×4 mm^2 or less.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210317A JPS6364330A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
| US07/093,524 US4857989A (en) | 1986-09-04 | 1987-09-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210317A JPS6364330A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6364330A true JPS6364330A (en) | 1988-03-22 |
Family
ID=16587419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61210317A Pending JPS6364330A (en) | 1986-09-04 | 1986-09-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6364330A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02213945A (en) * | 1988-12-29 | 1990-08-27 | Internatl Business Mach Corp <Ibm> | Computer system performing expert consulation |
| US6265770B1 (en) * | 1998-03-24 | 2001-07-24 | Seiko Epson Corporation | Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment |
-
1986
- 1986-09-04 JP JP61210317A patent/JPS6364330A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02213945A (en) * | 1988-12-29 | 1990-08-27 | Internatl Business Mach Corp <Ibm> | Computer system performing expert consulation |
| US6265770B1 (en) * | 1998-03-24 | 2001-07-24 | Seiko Epson Corporation | Mounting structure of semiconductor chip, liquid crystal device, and electronic equipment |
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