JP2000049271A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000049271A JP2000049271A JP10217041A JP21704198A JP2000049271A JP 2000049271 A JP2000049271 A JP 2000049271A JP 10217041 A JP10217041 A JP 10217041A JP 21704198 A JP21704198 A JP 21704198A JP 2000049271 A JP2000049271 A JP 2000049271A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- heat sink
- power device
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はパワーデバイスを有
する半導体装置、詳細にはパワーデバイスを実装してい
るリードフレームが外部放熱板に接触固定されている半
導体装置に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a power device, and more particularly, to a semiconductor device in which a lead frame mounting a power device is fixedly connected to an external heat sink.
【０００２】[0002]
【従来の技術】最初に、従来のパワーデバイスを備えた
半導体装置について説明する。従来例にかかる半導体装
置３０は、図６（Ａ）、（Ｂ）で示すように、平板構造
のリードフレーム３１のチップ実装面にパワーデバイス
チップ２、制御用モノリシックＩＣチップ３及び抵抗用
チップ４を配置し、リードフレーム３１のチップ実装面
の背面８（以下ヒートシンク面とする）を露出するよう
にモールド樹脂３２で一体封止したものである。さら
に、半導体装置３０は、ヒートシンク面８を外部放熱板
（図示せず）に接触固定される。即ち、外部放熱板は、
ヒートシンク面８を介して半導体装置３０で発生した熱
を放熱する役割を果たす。尚、制御用ＩＣチップ４がパ
ワーデバイスチップ２を制御する回路を形成するよう
に、上記３つのチップ２、３、４はボンデングワイヤ５
で接続されている。2. Description of the Related Art First, a semiconductor device having a conventional power device will be described. As shown in FIGS. 6A and 6B, a semiconductor device 30 according to a conventional example has a power device chip 2, a control monolithic IC chip 3, and a resistor chip 4 on a chip mounting surface of a lead frame 31 having a flat structure. Are arranged, and are integrally sealed with a mold resin 32 so as to expose a back surface 8 (hereinafter, referred to as a heat sink surface) of a chip mounting surface of the lead frame 31. Further, the heat sink surface 8 of the semiconductor device 30 is contact-fixed to an external heat sink (not shown). That is, the external heat sink is
It serves to radiate heat generated in the semiconductor device 30 via the heat sink surface 8. The three chips 2, 3, and 4 are bonded to each other so that the control IC chip 4 forms a circuit that controls the power device chip 2.
Connected by
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、リード
フレーム３１は平板構造であるので剛性に乏しく、パワ
ーデバイス２を封止する際に発生するモールド樹脂３２
の応力の影響を受けて、リードフレーム３１が変形しヒ
ートシンク面８が反り返る。このことによって、外部放
熱板とヒートシンク面８との間に隙間ができるので、半
導体装置３０で発生する熱を十分に放熱できないという
課題があった。However, since the lead frame 31 has a flat plate structure, it has poor rigidity, and the molding resin 32 generated when the power device 2 is sealed.
, The lead frame 31 is deformed and the heat sink surface 8 warps. As a result, a gap is formed between the external heat sink and the heat sink surface 8, so that the heat generated in the semiconductor device 30 cannot be sufficiently dissipated.
【０００４】さらに、上記半導体装置３０は、リードフ
レームが平板構造である為に、モールド樹脂３２のリー
ドフレーム３１に対する密着性が悪く、半導体装置の信
頼度の低下を招いていた。Further, in the semiconductor device 30, since the lead frame has a flat plate structure, the adhesion of the molding resin 32 to the lead frame 31 is poor, and the reliability of the semiconductor device is reduced.
【０００５】本発明は、従来技術の有するこのような問
題点に鑑みてなされたものであり、リードフレームを介
して外部放熱板に効率良く熱を放熱させることができる
半導体装置、及びリードフレームにモールド樹脂が十分
に密着している信頼性の高い半導体装置を提供すること
を目的とする。The present invention has been made in view of the above-mentioned problems of the prior art, and is directed to a semiconductor device and a lead frame capable of efficiently dissipating heat to an external heat sink through a lead frame. It is an object of the present invention to provide a highly reliable semiconductor device in which a mold resin is sufficiently adhered.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明にかかる第１の半導体装置は、リードフレーム
の剛性を強化して、ヒートシンク面の反りを防止する。
具体的には、本発明にかかる第１の半導体装置は、パワ
ーデバイスと該パワーデバイスを制御する制御デバイス
とを、リードフレームのデバイス実装面に配置しその背
面であるヒートシンク面を露出させてモールド樹脂で封
止し、上記ヒートシンク面を外部放熱板上に接触固定し
てなる半導体装置であって、上記リードフレームの上記
実装面は、上記パワーデバイスが実装される平坦なリー
ドフレーム平坦部及び該リードフレーム平坦部に連続し
て延びる上記制御用デバイスが実装される制御用デバイ
ス領域を有し、上記リードフレーム平坦部の対向する縁
辺部を上記リードフレームの上方に向かって立ち上げ補
強部を形成することで、ヒートシンク面の剛性を強化し
たことを特徴とする。In order to solve the above-mentioned problems, a first semiconductor device according to the present invention enhances the rigidity of a lead frame to prevent warpage of a heat sink surface.
Specifically, in the first semiconductor device according to the present invention, a power device and a control device for controlling the power device are arranged on a device mounting surface of a lead frame, and a heat sink surface as a back surface thereof is exposed to mold. A semiconductor device which is sealed with resin and fixedly contacts the heat sink surface on an external heat sink, wherein the mounting surface of the lead frame has a flat lead frame flat portion on which the power device is mounted, and A control device region in which the control device extending continuously to the lead frame flat portion is mounted, and an opposing edge portion of the lead frame flat portion is raised toward the upper side of the lead frame to form a reinforcing portion. By doing so, the rigidity of the heat sink surface is enhanced.
【０００７】さらに、本発明にかかる第１の半導体装置
は、上記補強部に上記モールド樹脂が食い込む貫通孔又
は切欠部を設け、リードフレームとモールド樹脂との密
着性を向上させるのが好ましい。Further, in the first semiconductor device according to the present invention, it is preferable that a through-hole or a cutout into which the molding resin bites is provided in the reinforcing portion to improve the adhesion between the lead frame and the molding resin.
【０００８】上記課題を解決するために本発明にかかる
第２の半導体装置は、モールド樹脂部を分割し各モール
ド樹脂部の寸法を小さくして、モールド樹脂が引き起こ
す応力を低減させてヒートシンク面の変形を防止する。
具体的には、本発明にかかる第２の半導体装置は、パワ
ーデバイスと該パワーデバイスを制御する制御デバイス
とを、リードフレームのデバイス実装面に配置しその背
面であるヒートシンク面を露出させてモールド樹脂で封
止し、上記ヒートシンク面を外部放熱板上に接触固定し
てなる半導体装置であって、上記リードフレームの上記
実装面は、上記パワーデバイスが実装される平坦なリー
ドフレーム平坦部及び該リードフレーム平坦部に連続し
て延びる上記制御用デバイスが実装される制御用デバイ
ス領域を有し、上記パワーデバイスを上記リードフレー
ム平坦部に封止するパワーデバイスモールド部と、上記
制御用デバイスを封止する制御用デバイスモールド部と
が分離されていることを特徴とする。In order to solve the above-mentioned problems, a second semiconductor device according to the present invention divides a mold resin portion, reduces the size of each mold resin portion, reduces stress caused by the mold resin, and reduces the stress caused by the mold resin. Prevent deformation.
Specifically, in the second semiconductor device according to the present invention, a power device and a control device for controlling the power device are arranged on a device mounting surface of a lead frame, and a heat sink surface as a back surface thereof is exposed to mold. A semiconductor device which is sealed with a resin and fixedly contacts the heat sink surface on an external heat sink, wherein the mounting surface of the lead frame has a flat lead frame flat portion on which the power device is mounted, and A power device molding portion for sealing the power device to the lead frame flat portion, the power device molding portion including a control device region in which the control device extending continuously to the lead frame flat portion is mounted, and sealing the control device; The control device mold section to be stopped is separated from the control device mold section.
【０００９】さらに、本発明にかかる第２の半導体装置
は、上記リードフレーム平坦部の対向する縁辺部を上記
リードフレームの上方に向かって立ち上げ補強部を形成
し、ヒートシンク面の剛性を強化して、より確実にヒー
トシンク面の変形を防止するのが好ましい。Further, in the second semiconductor device according to the present invention, the opposing edges of the flat portion of the lead frame are raised toward the upper part of the lead frame to form a reinforcing portion, thereby enhancing the rigidity of the heat sink surface. Therefore, it is preferable to more reliably prevent the deformation of the heat sink surface.
【００１０】さらに、本発明にかかる第２の半導体装置
は、上記補強部に上記モールド樹脂が食い込む貫通孔又
は切欠部を設け、リードフレームとモールド樹脂との密
着性を向上させるのが好ましい。Further, in the second semiconductor device according to the present invention, it is preferable that a through hole or a notch portion into which the molding resin bites is provided in the reinforcing portion to improve the adhesion between the lead frame and the molding resin.
【００１１】また、さらに、本発明にかかる第２の半導
体装置は、上記制御用デバイス領域及び上記リードフレ
ーム平坦部に連続し、上記制御用デバイスモールド部と
上記パワーデバイスモールド部との間で露出されている
湾曲リード部を備えていること、外力を上記湾曲リード
部に吸収させることで該リード部の破損を防止し、上記
半導体装置の信頼性を向上させることができる。Further, the second semiconductor device according to the present invention is continuous with the control device region and the lead frame flat portion, and is exposed between the control device mold portion and the power device mold portion. By providing the curved lead portion, and by absorbing the external force to the curved lead portion, breakage of the lead portion can be prevented, and the reliability of the semiconductor device can be improved.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態にかか
る半導体装置に関して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.
【００１３】実施の形態１．図１（Ａ）に示すように、
本発明の実施１にかかる半導体装置２０は、モールド部
６を外部放熱板２２に固定したものである。モールド部
６はパワーデバイスチップ２、制御用デバイスチップ３
及び抵抗チップ４をリードフレーム１５に封止したもの
であり、リードフレーム１５は、デバイス実装面にパワ
ーデバイスチップ２を実装する部分、制御用デバイスチ
ップ３及び抵抗チップ４を実装する部分を備えている。
また、リードフレーム１５はモールド部６の外部まで延
び、その端部は外部端子２３をなす。図１（Ｂ）で示す
ように、上記モールド部６は、デバイス実装面のパワー
デバイスチップ２が実装されている部分の背面８（以下
ヒートシンク面とする）を露出させるように、モールド
樹脂で上記３つのチップ２，３，４を一体封止したもの
であり、リードフレーム１２の制御用デバイスチップ３
及び抵抗チップ４を実装する部分は完全にモールド樹脂
で覆われている。さらに、モールド部６は、ヒートシン
ク面８を外部放熱板２２に接触させて、外部放熱板２２
に固定されている。尚、制御用デバイスチップ４がパワ
ーデバイスチップ２を制御する回路を形成するように、
上記３つのチップ２、３、４はボンデングワイヤ５で接
続されている。Embodiment 1 FIG. As shown in FIG.
In the semiconductor device 20 according to the first embodiment of the present invention, the mold part 6 is fixed to the external heat sink 22. The mold part 6 includes the power device chip 2 and the control device chip 3
And the resistance chip 4 is sealed in a lead frame 15, and the lead frame 15 includes a part for mounting the power device chip 2 on the device mounting surface, and a part for mounting the control device chip 3 and the resistance chip 4. I have.
Further, the lead frame 15 extends to the outside of the mold section 6, and its end forms an external terminal 23. As shown in FIG. 1 (B), the molding part 6 is formed of a molding resin so as to expose a back surface 8 (hereinafter referred to as a heat sink surface) of a part of the device mounting surface on which the power device chip 2 is mounted. A device chip 3 for controlling the lead frame 12 in which three chips 2, 3 and 4 are integrally sealed.
The portion where the resistor chip 4 is mounted is completely covered with the mold resin. Further, the mold portion 6 contacts the heat sink surface 8 with the external heat radiating plate 22 and
It is fixed to. Note that the control device chip 4 forms a circuit for controlling the power device chip 2,
The above three chips 2, 3, 4 are connected by a bonding wire 5.
【００１４】他方、図１（Ａ）に示すように、パワーデ
バイスチップ２は、リードフレーム１２のデバイス実装
面の平坦な部分であるパワーデバイス領域１６ａに実装
されていて、さらに、パワーデバイス領域１６ａの両側
にリードフレーム１２の縁辺部に沿って延びるリードフ
レーム壁１６ｂを設けることで、パワーデバイス領域１
６ａを補強している。On the other hand, as shown in FIG. 1A, the power device chip 2 is mounted on a power device region 16a which is a flat portion of a device mounting surface of the lead frame 12, and furthermore, the power device region 16a By providing lead frame walls 16b extending along the edges of the lead frame 12 on both sides of the power device region 1,
6a is reinforced.
【００１５】詳細には、図１（Ｃ）に示すように、リー
ドフレーム壁１６ｂは、パワーデバイス領域１６ａに対
して外側上方に向かって延びていて、リードフレーム壁
１６ｂの側面には図１（Ａ）、（Ｂ）で示すように複数
の貫通孔９が設けられている。本実施の形態では、上記
貫通孔９の直径を０.６ｍｍ、貫通孔９の間隔を２ｍｍ
とする。More specifically, as shown in FIG. 1C, the lead frame wall 16b extends outward and upward with respect to the power device region 16a, and the side of the lead frame wall 16b is formed as shown in FIG. A plurality of through holes 9 are provided as shown in FIGS. In the present embodiment, the diameter of the through hole 9 is 0.6 mm, and the distance between the through holes 9 is 2 mm.
And
【００１６】上記のように、リードフレーム１５にリー
ドフレーム壁１６ｂを設けることによって、リードフレ
ーム１５のヒートシンク面８の剛性が強化されるので、
チップ２、３、４を封止する際に発生する応力によるリ
ードフレーム１５の変形を防止し、ヒートシンク面８の
反りを防ぐ。従って、ヒートシンク面８を平面に保持さ
れ、図１（Ｂ）、（Ｃ）で示すように、ヒートシンク面
８は、外部放熱板２２に隙間なく接触し、パワーデバイ
ス２で発生する熱を効率良く放熱させることができる。As described above, by providing the lead frame wall 16b on the lead frame 15, the rigidity of the heat sink surface 8 of the lead frame 15 is enhanced.
The deformation of the lead frame 15 due to the stress generated when the chips 2, 3, and 4 are sealed is prevented, and the heat sink surface 8 is prevented from warping. Therefore, the heat sink surface 8 is held flat, and as shown in FIGS. 1B and 1C, the heat sink surface 8 contacts the external heat sink 22 without any gap, and efficiently removes the heat generated by the power device 2. Heat can be dissipated.
【００１７】また、リードフレーム壁１６ｂに形成され
た貫通孔９にモールド樹脂が食い込むので、モールド樹
脂とリードフレーム１５との密着性が高まり、半導体装
置２０ａの信頼性が向上される。Further, since the molding resin penetrates into the through holes 9 formed in the lead frame wall 16b, the adhesion between the molding resin and the lead frame 15 is enhanced, and the reliability of the semiconductor device 20a is improved.
【００１８】次に、上記半導体装置２０の第１の変形例
にかかる半導体装置２０ａについて説明する。図３で示
すように、半導体装置２０ａは、リードフレーム壁１６
ｂにリードフレーム壁１５の底面側に向かって開口する
切欠け１０ａを形成したこと特徴とする。本実施の形態
においては、上記切欠け１０ａの寸法は、一辺を１ｍ
ｍ、切欠け間の間隔を３ｍｍとする。切欠け１０ａを設
けたことを除いて、上記半導体装置２０ａは、上記実施
の形態１にかかる半導体装置２０と同様である。Next, a semiconductor device 20a according to a first modification of the semiconductor device 20 will be described. As shown in FIG. 3, the semiconductor device 20a is
b, a notch 10a opening toward the bottom side of the lead frame wall 15 is formed. In the present embodiment, the size of the notch 10a is 1 m on one side.
m, and the interval between the notches is 3 mm. The semiconductor device 20a is the same as the semiconductor device 20 according to the first embodiment except that the notch 10a is provided.
【００１９】リードフレーム壁１６ｂに形成された切欠
け１０ａにモールド樹脂が食い込むので、モールド樹脂
とリードフレーム１５との密着性が高まり、半導体装置
２０ａの信頼性が向上される。Since the mold resin bites into the notch 10a formed in the lead frame wall 16b, the adhesion between the mold resin and the lead frame 15 is enhanced, and the reliability of the semiconductor device 20a is improved.
【００２０】次に、上記半導体装置２０の第１の変形例
にかかる半導体装置２０ｂについて説明する。図３で示
すように、半導体装置２０ｂは、リードフレーム壁１６
ｂに該リードフレーム壁１６ｂの上端辺に向かって開口
する切欠け１０ｂを形成したものである。本実施の形態
においては、上記切欠け１０ｂの寸法は、一辺を１ｍ
ｍ、切欠け間の間隔を３ｍｍとする。切欠け１０を設け
たことを除いて、上記半導体装置２０ｂは上記実施の形
態１にかかる半導体装置２０と同様である。Next, a semiconductor device 20b according to a first modification of the semiconductor device 20 will be described. As shown in FIG. 3, the semiconductor device 20b is
b is formed with a notch 10b opening toward the upper end side of the lead frame wall 16b. In the present embodiment, the size of the notch 10b is 1 m on one side.
m, and the interval between the notches is 3 mm. Except that the notch 10 is provided, the semiconductor device 20b is the same as the semiconductor device 20 according to the first embodiment.
【００２１】上記の構造においては、リードフレーム壁
１６ｂに形成された切欠け１０ｂにモールド樹脂が食い
込むので、モールド樹脂とリードフレーム１５との密着
性が高まり、半導体装置２０ｂの信頼性を向上させるこ
とができる。In the above structure, since the molding resin penetrates into the notch 10b formed in the lead frame wall 16b, the adhesion between the molding resin and the lead frame 15 is increased, and the reliability of the semiconductor device 20b is improved. Can be.
【００２２】尚、前述した実施の形態１においては、リ
ードフレーム壁１６ｂは、リードフレーム平面部に対し
て斜め上方に延びているが、本願発明は、リードフレー
ム壁をリードフレーム平面部に対して斜め上方に延びる
ものに限定するものではなく、リードフレーム壁は平面
部に対して鉛直上方に延びるものであってもよい。In the above-described first embodiment, the lead frame wall 16b extends obliquely upward with respect to the lead frame plane portion. The lead frame wall is not limited to the one extending obliquely upward, and the lead frame wall may extend vertically upward relative to the plane portion.
【００２３】実施の形態２．次に、本発明の実施の形態
２にかかる半導体装置２１について説明する。図４
（Ａ）で示すように、半導体装置２１は、パワーデバイ
ス用モールド部６ａ及び制御用デバイス用モールド部６
ｂを備えていて、パワーデバイス用モールド部６ａが外
部放熱板２２に固定されたものである。パワーデバイス
用モールド部６ａはパワーデバイスチップ２を、制御用
デバイス用モールド部６ｂは抵抗チップ４と制御用チッ
プ３を、各々別々にリードフレーム１５ａに封止するも
のである。上記実施の形態１と同様に、リードフレーム
１５ａは、デバイス実装面にパワーデバイスチップ２を
実装する部分、制御用デバイスチップ３及び抵抗チップ
４を実装する部分を備えている。また、リードフレーム
１５の端部は外部用端子２３の役割を果たす。Embodiment 2 FIG. Next, a semiconductor device 21 according to a second embodiment of the present invention will be described. FIG.
As shown in (A), the semiconductor device 21 includes a power device mold portion 6a and a control device mold portion 6a.
b, and the power device mold portion 6 a is fixed to the external heat sink 22. The power device mold portion 6a seals the power device chip 2 and the control device mold portion 6b seals the resistor chip 4 and the control chip 3 separately in the lead frame 15a. As in the first embodiment, the lead frame 15a includes a portion for mounting the power device chip 2 on the device mounting surface, and a portion for mounting the control device chip 3 and the resistor chip 4 on the device mounting surface. The end of the lead frame 15 plays the role of an external terminal 23.
【００２４】詳細には、図４（Ｂ）で示すように、パワ
ーデバイス用モールド部６ａは、デバイス実装面のパワ
ーデバイスチップ２が実装されている部分の背面８（以
下ヒートシンク面とする）を露出させるようにモールド
樹脂でパワーデバイスチップ２を封止する。一方、制御
デバイス用モールド部６ｂは、制御用デバイスチップ３
及び抵抗チップ４が実装されている部分をモールド樹脂
で完全に覆うように両チップ３、４を封止する。More specifically, as shown in FIG. 4B, the power device mold portion 6a has a back surface 8 (hereinafter referred to as a heat sink surface) of a portion of the device mounting surface on which the power device chip 2 is mounted. The power device chip 2 is sealed with a mold resin so as to be exposed. On the other hand, the control device mold part 6b is
Then, both chips 3 and 4 are sealed so as to completely cover the portion where the resistor chip 4 is mounted with the mold resin.
【００２５】他方、パワーデバイス用モールド部６ａと
制御用デバイスモールド部６ｂとの間にリードフレーム
１５ａの一部分１７（以下露出リード部とする）が露出
されている。尚、制御用ＩＣチップ４がパワーデバイス
チップ２を制御する回路を形成するように、上記３つの
チップ２、３、４はボンデングワイヤ５で接続されてい
る。On the other hand, a portion 17 of the lead frame 15a (hereinafter referred to as an exposed lead portion) is exposed between the power device mold portion 6a and the control device mold portion 6b. The three chips 2, 3, 4 are connected by bonding wires 5 so that the control IC chip 4 forms a circuit for controlling the power device chip 2.
【００２６】モールド部を二分割することで、パワーデ
バイス用モールド部６ａと制御用デバイスモールド部６
ｂの寸法が小型になる。こうすると、リードフレーム１
５ｄにパワーデバイスチップ２を封止する際に発生する
応力が減少するので、ヒートシンク面８が変形すること
を防止し、ヒートシンク面の平面度を確保することがで
きる。By dividing the mold part into two parts, a power device mold part 6a and a control device mold part 6a are formed.
The size of b becomes smaller. Then, lead frame 1
Since the stress generated when sealing the power device chip 2 at 5d is reduced, the heat sink surface 8 is prevented from being deformed, and the flatness of the heat sink surface can be ensured.
【００２７】尚、リードフレーム１２のデバイス実装面
のパワーデバイスチップが実装されるパワーデバイス領
域両側に、実施の形態１と同様のリードフレーム壁を設
けてもよい。こうすることで、ヒートシンク面の剛性が
強化され、ヒートシンク面の平面度をより確実に確保す
ることができる。Note that lead frame walls similar to those of the first embodiment may be provided on both sides of the power device area on the device mounting surface of the lead frame 12 where the power device chip is mounted. By doing so, the rigidity of the heat sink surface is enhanced, and the flatness of the heat sink surface can be more reliably ensured.
【００２８】さらに、上記リードフレーム壁に実施の形
態１と同様の貫通孔又は切欠部を設けて、モールド樹脂
をリードフレームと密着性を向上させてもよい。Further, a through hole or a notch similar to that of the first embodiment may be provided in the lead frame wall to improve the adhesion of the mold resin to the lead frame.
【００２９】次に、図５を参照して、上記実施の形態２
にかかる半導体装置の変形例２１ａに関して説明する。
変形例にかかる半導体装置２１ａは、上述した半導体装
置２１の露出リード部１７にＵ字状屈曲形状部１７ａを
設けたものである。Next, referring to FIG. 5, the second embodiment will be described.
A modification 21a of the semiconductor device according to the first embodiment will be described.
The semiconductor device 21a according to the modified example is such that the exposed lead portion 17 of the semiconductor device 21 described above is provided with a U-shaped bent portion 17a.
【００３０】露出リード部１７にＵ字状屈曲形状部１７
ａを設けることによって、半導体装置２１ａの外部端子
２３に別の部品等を接続した場合に外部端子２３に伝わ
る外力を、Ｕ字状屈曲形状部１７ａで吸収することで、
露出リード部１７の破損を防止する。The exposed lead portion 17 has a U-shaped bent portion 17.
By providing a, external force transmitted to the external terminal 23 when another component or the like is connected to the external terminal 23 of the semiconductor device 21a is absorbed by the U-shaped bent portion 17a.
The exposed lead portion 17 is prevented from being damaged.
【００３１】[0031]
【発明の効果】本発明の第１の半導体装置によると、リ
ードフレームのパワーデバイスチップが実装される平坦
部の両側にリードフレーム壁を設けることによって、リ
ードフレームのヒートシンク面の剛性を強化し、モール
ド樹脂の応力によってリードフレームのヒートシンク面
が変形することを防止する。According to the first semiconductor device of the present invention, the rigidity of the heat sink surface of the lead frame is enhanced by providing the lead frame walls on both sides of the flat portion of the lead frame on which the power device chip is mounted, The deformation of the heat sink surface of the lead frame due to the stress of the mold resin is prevented.
【００３２】本発明の第１の半導体装置によると、上記
リードフレーム壁に貫通孔又は切欠部を設けることのよ
って、モールド樹脂が上記貫通孔又は切欠部に食い込み
半導体装置の信頼性を向上させることができる。According to the first semiconductor device of the present invention, by providing a through hole or a notch in the lead frame wall, the mold resin bites into the through hole or the notch to improve the reliability of the semiconductor device. Can be.
【００３３】本発明の第２の半導体装置によると、パワ
ーデバイスチップを封止するパワーデバイスモールド部
と制御用デバイスチップを封止する制御用デバイスモー
ルド部とを分離して設けることで、各モールド部の寸法
を小型し、モールド樹脂が発生する応力を低減させ、リ
ードフレームの変形を防止する。According to the second semiconductor device of the present invention, the power device mold section for sealing the power device chip and the control device mold section for sealing the control device chip are separately provided, so that each mold is provided. The size of the portion is reduced, the stress generated by the molding resin is reduced, and the deformation of the lead frame is prevented.
【００３４】本発明の第２の半導体装置によると、リー
ドフレームのパワーデバイスチップが実装される平坦部
の両側にリードフレーム壁を設けることによって、リー
ドフレームのヒートシンク面の剛性を強化し、モールド
樹脂の応力によってリードフレームのヒートシンク面が
変形することをより確実に防止する。According to the second semiconductor device of the present invention, the rigidity of the heat sink surface of the lead frame is enhanced by providing the lead frame walls on both sides of the flat portion of the lead frame on which the power device chip is mounted, and the molding resin is provided. This prevents the heat sink surface of the lead frame from being deformed by the stress.
【００３５】本発明の第２の半導体装置によると、上記
リードフレーム壁に貫通孔又は切欠部を設けることによ
って、モールド樹脂が上記貫通孔又は切欠部に食い込み
半導体装置の信頼性を向上させることができる。According to the second semiconductor device of the present invention, by providing a through hole or a notch in the lead frame wall, the mold resin can cut into the through hole or the notch to improve the reliability of the semiconductor device. it can.
【００３６】本発明の第２の半導体装置によると、パワ
ーデバイスモールド部と制御用デバイスモールド部との
間に形成されている露出リード部に湾曲部を設けること
で、外力による露出リード部の破損を防止する。According to the second semiconductor device of the present invention, the exposed lead portion formed between the power device mold portion and the control device mold portion is provided with a curved portion, so that the exposed lead portion is damaged by an external force. To prevent
【図１】 本発明の実施の形態１にかかる半導体装置を
示すもので、（Ａ）は上面図を、（Ｂ）は側面図を、
（Ｃ）は（Ａ）の線ＩＣ−ＩＣに沿った断面図を示す。1A and 1B show a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a top view, FIG.
(C) shows a cross-sectional view along the line IC-IC of (A).
【図２】 本発明の実施の形態１にかかる半導体装置の
第１の変形例を示すもので、（Ａ）は上面図を、（Ｂ）
は側面図を示す。FIGS. 2A and 2B show a first modification of the semiconductor device according to the first embodiment of the present invention, in which FIG.
Shows a side view.
【図３】 本発明の実施の形態１にかかる半導体装置の
第２の変形例を示すもので、（Ａ）は上面図を、（Ｂ）
は側面図を示す。FIGS. 3A and 3B show a second modification of the semiconductor device according to the first embodiment of the present invention, wherein FIG. 3A is a top view and FIG.
Shows a side view.
【図４】 本発明の実施の形態２にかかる半導体装置を
示すもので、（Ａ）は上面図を、（Ｂ）は側面図をを示
す。4A and 4B show a semiconductor device according to a second embodiment of the present invention, wherein FIG. 4A is a top view and FIG. 4B is a side view.
【図５】 本発明の実施の形態２にかかる半導体装置の
変形例を示すもので、（Ａ）は上面図を、（Ｂ）は側面
図を示す。FIGS. 5A and 5B show a modification of the semiconductor device according to the second embodiment of the present invention, wherein FIG. 5A is a top view and FIG. 5B is a side view.
【図６】 従来例にかかる半導体装置を示すもので、
（Ａ）は上面図を、（Ｂ）は側面図を示す。FIG. 6 illustrates a semiconductor device according to a conventional example.
(A) shows a top view and (B) shows a side view.
２ パワーデバイスチップ、 ３ 制御用デバイスチッ
プ、 ６ モールド部、 ６ａ パワーデバイス用モー
ルド部、 ６ｂ 制御用デバイス用モールド部、 ８
ヒートシンク面、 ９ 貫通孔、 １０ａ 切欠部、
１０ｂ 切欠部、 １５ リードフレーム、 １５ａ
リードフレーム、 １６ａ パワーデバイス領域、 １
６ｂ リードフレーム壁、 ２０ 半導体装置、 ２０
ａ 半導体装置、 ２０ｂ 半導体装置、 ２１ 半導
体装置、 ２１ａ 半導体装置、２２ 外部放熱板。2 Power device chip, 3 Control device chip, 6 Mold part, 6a Power device mold part, 6b Control device mold part, 8
Heat sink surface, 9 through hole, 10a notch,
10b notch, 15 lead frame, 15a
Lead frame, 16a power device area, 1
6b Lead frame wall, 20 semiconductor device, 20
a semiconductor device, 20b semiconductor device, 21 semiconductor device, 21a semiconductor device, 22 external heat sink.
Claims (6)
御する制御デバイスとを、リードフレームのデバイス実
装面に配置しその背面であるヒートシンク面を露出させ
てモールド樹脂で封止し、上記ヒートシンク面を外部放
熱板上に接触固定してなる半導体装置であって、 上記リードフレームの上記実装面は、上記パワーデバイ
スが実装される平坦なリードフレーム平坦部及び該リー
ドフレーム平坦部に連続して延びる上記制御用デバイス
が実装される制御用デバイス領域を有し、 上記リードフレーム平坦部の対向する縁辺部を上記リー
ドフレームの上方に向かって立ち上げ補強部を形成した
ことを特徴とする半導体装置。1. A power device and a control device for controlling the power device are arranged on a device mounting surface of a lead frame, a heat sink surface as a back surface thereof is exposed, and sealed with a mold resin. A semiconductor device fixedly contacted on a heat sink, wherein the mounting surface of the lead frame is a flat lead frame flat portion on which the power device is mounted and the control device extending continuously to the lead frame flat portion. A semiconductor device having a control device region on which a device for mounting is mounted, wherein a reinforcement portion is formed by raising an opposing edge of the flat portion of the lead frame toward above the lead frame.
む貫通孔又は切欠部を備えていることを特徴とする請求
項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the reinforcing portion includes a through hole or a cutout into which the mold resin bites.
御する制御デバイスとを、リードフレームのデバイス実
装面に配置しその背面であるヒートシンク面を露出させ
てモールド樹脂で封止し、上記ヒートシンク面を外部放
熱板上に接触固定してなる半導体装置であって、 上記リードフレームの上記実装面は、上記パワーデバイ
スが実装される平坦なリードフレーム平坦部及び該リー
ドフレーム平坦部に連続して延びる上記制御用デバイス
が実装される制御用デバイス領域を有し、 上記パワーデバイスを上記リードフレーム平坦部に封止
するパワーデバイスモールド部と、上記制御用デバイス
を封止する制御用デバイスモールド部とが分離されてい
ることを特徴とする半導体装置。3. A power device and a control device for controlling the power device are arranged on a device mounting surface of a lead frame, and a heat sink surface as a back surface thereof is exposed and sealed with a mold resin. A semiconductor device fixedly contacted on a heat sink, wherein the mounting surface of the lead frame is a flat lead frame flat portion on which the power device is mounted and the control device extending continuously to the lead frame flat portion. A power device mold section for sealing the power device in the flat portion of the lead frame and a control device mold section for sealing the control device. A semiconductor device characterized in that:
辺部を上記リードフレームの上方に向かって立ち上げ補
強部を形成したことを特徴とする請求項３記載の半導体
装置。4. The semiconductor device according to claim 3, wherein a reinforcement portion is formed by raising an opposite edge of the flat portion of the lead frame toward an upper side of the lead frame.
む貫通孔又は切欠部を備えていることを特徴とする請求
項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the reinforcing portion has a through hole or a cutout into which the mold resin bites.
フレーム平坦部に連続し上記制御用デバイスモールド部
と上記パワーデバイスモールド部との間で露出されてい
る湾曲リード部を備えていることを特徴とする請求項３
〜５のいずれか一つに記載の半導体装置。6. A curved lead portion which is continuous with the control device region and the lead frame flat portion and is exposed between the control device mold portion and the power device mold portion. Claim 3
6. The semiconductor device according to any one of items 5 to 5.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10217041A JP2000049271A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device |
| KR1019990011174A KR20000011229A (en) | 1998-07-31 | 1999-03-31 | Semiconductor device |
| DE19915065A DE19915065A1 (en) | 1998-07-31 | 1999-04-01 | Semiconductor module with improved heat dissipation; has power component and control component chip on fastening face of carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10217041A JP2000049271A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000049271A true JP2000049271A (en) | 2000-02-18 |
Family
ID=16697921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10217041A Pending JP2000049271A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2000049271A (en) |
| KR (1) | KR20000011229A (en) |
| DE (1) | DE19915065A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009070934A (en) * | 2007-09-12 | 2009-04-02 | Hitachi Ltd | Power semiconductor module, and manufacturing method thereof |
| JP2011029588A (en) * | 2009-06-24 | 2011-02-10 | Denso Corp | Linked semiconductor module and motor with built-in electronic circuit using the same |
| JPWO2015104834A1 (en) * | 2014-01-10 | 2017-03-23 | 三菱電機株式会社 | Power semiconductor device |
| WO2023203754A1 (en) * | 2022-04-22 | 2023-10-26 | 三菱電機株式会社 | Capacitor unit and electronic device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005059995A2 (en) * | 2003-12-18 | 2005-06-30 | Rf Module And Optical Design Limited | Semiconductor package with integrated heatsink and electromagnetic shield |
-
1998
- 1998-07-31 JP JP10217041A patent/JP2000049271A/en active Pending
-
1999
- 1999-03-31 KR KR1019990011174A patent/KR20000011229A/en not_active Application Discontinuation
- 1999-04-01 DE DE19915065A patent/DE19915065A1/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009070934A (en) * | 2007-09-12 | 2009-04-02 | Hitachi Ltd | Power semiconductor module, and manufacturing method thereof |
| JP2011029588A (en) * | 2009-06-24 | 2011-02-10 | Denso Corp | Linked semiconductor module and motor with built-in electronic circuit using the same |
| US8630095B2 (en) | 2009-06-24 | 2014-01-14 | Denso Corporation | Linked semiconductor module unit and electronic circuit-integrated motor vehicle device using same |
| US9025336B2 (en) | 2009-06-24 | 2015-05-05 | Denso Corporation | Linked semiconductor module unit and electronic circuit-integrated motor device using same |
| JPWO2015104834A1 (en) * | 2014-01-10 | 2017-03-23 | 三菱電機株式会社 | Power semiconductor device |
| US9627302B2 (en) | 2014-01-10 | 2017-04-18 | Mitsubishi Electric Corporation | Power semiconductor device |
| WO2023203754A1 (en) * | 2022-04-22 | 2023-10-26 | 三菱電機株式会社 | Capacitor unit and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000011229A (en) | 2000-02-25 |
| DE19915065A1 (en) | 2000-02-10 |
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