JP2001358259A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JP2001358259A
JP2001358259A JP2000179897A JP2000179897A JP2001358259A JP 2001358259 A JP2001358259 A JP 2001358259A JP 2000179897 A JP2000179897 A JP 2000179897A JP 2000179897 A JP2000179897 A JP 2000179897A JP 2001358259 A JP2001358259 A JP 2001358259A
Authority
JP
Japan
Prior art keywords
heat sink
chip
heat
sealing member
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000179897A
Other languages
Japanese (ja)
Inventor
Manabu Kondo
学 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000179897A priority Critical patent/JP2001358259A/en
Publication of JP2001358259A publication Critical patent/JP2001358259A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which radiates heat efficiently and is equipped with a heat sink as a measure to prevent the increase in soldering temperature when the package is mounted on a main substrate. SOLUTION: An IC chip 11 whose backside is fixed on a die 10 is formed with a plurality of electrodes 12 on a main surface, and is protected by a sealing member 13 formed of, for example, molding resin. External terminals 14 have their one end extended outside from the sealing member 13 and the other end electrically connected to the IC chip 11 by a bonding wire 15 or the like. The heat sink 16 has the larger area side exposed outside the sealing member 13 and the opposite side fixed on the main surface of the IC chip 11. The heat sink 16 can be installed after being mounted on the main substrate by means of the external terminals 14, that is, after-installation is allowed for the heat sink 16.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、特にヒートシンクを必要とする半導体パッケージに
関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor package requiring a heat sink.

【０００２】[0002]

【従来の技術】半導体パッケージにおいて、高速動作の
ＩＣチップ、消費電力の大きなＩＣチップを搭載する場
合、自己の発熱によって誤動作してしまう恐れがある。
このようなＩＣチップには放熱対策が必要であり、ヒー
トシンクを伴うパッケージを構成することが一般的であ
る。2. Description of the Related Art In a semiconductor package, when an IC chip operating at a high speed or an IC chip having a large power consumption is mounted, a malfunction may occur due to its own heat generation.
Such an IC chip requires heat radiation measures, and it is common to configure a package with a heat sink.

【０００３】図５（ａ），（ｂ）は、それぞれ従来にお
けるヒートシンク付きの半導体パッケージの構成を示す
断面図である。各図とも、封止部材５３は、外部端子５
４の一端を含み、ＩＣチップ５１及び外部端子５４との
電気的接続部分を保護している。同図（ａ），（ｂ）に
おいて、外部端子５４が互いに逆曲げ構成となっている
点のみが異なっている。FIGS. 5A and 5B are cross-sectional views showing the structure of a conventional semiconductor package with a heat sink. In each of the drawings, the sealing member 53 is connected to the external terminal 5.
4 to protect the electrical connection between the IC chip 51 and the external terminals 54. 11A and 11B, the only difference is that the external terminals 54 are reversely bent.

【０００４】各図において、ＩＣチップ５１は、その裏
面がヒートシンク５６の一方側に密着されている。ヒー
トシンク５６の他方側は封止部材５３から露出してい
る。これにより、ＩＣチップ５１動作時の発熱は、チッ
プ裏面からヒートシンク５６を介して放熱する。In each figure, the back surface of the IC chip 51 is in close contact with one side of a heat sink 56. The other side of the heat sink 56 is exposed from the sealing member 53. Thus, heat generated during the operation of the IC chip 51 is radiated from the back surface of the chip via the heat sink 56.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、上記構
成の半導体パッケージでは、ＩＣチップ５１表面の発熱
をチップ裏面から吸収することになる。このため、放熱
性について若干のロスが生じる。However, in the semiconductor package having the above configuration, heat generated on the surface of the IC chip 51 is absorbed from the back surface of the chip. For this reason, a slight loss occurs in heat dissipation.

【０００６】また、上記構成の半導体パッケージでは、
ヒートシンク５６は、予め半導体パッケージになった時
にパッケージと一体化している。このため、パッケージ
自体の熱容量が増大する。Further, in the semiconductor package having the above configuration,
The heat sink 56 is integrated with the package when it is made into a semiconductor package in advance. Therefore, the heat capacity of the package itself increases.

【０００７】つまり、この半導体パッケージがメイン基
板（図示せず）に実装される際、メイン基板全体のハン
ダ付け温度設定を上昇させることになる。メイン基板に
は、ハンダ付け温度設定を高くすると、より影響が深刻
になる他の部品も含まれていることが少なくない。That is, when this semiconductor package is mounted on a main board (not shown), the soldering temperature setting of the entire main board is increased. In many cases, the main board also contains other components that become more serious when the soldering temperature setting is increased.

【０００８】本発明は上記のような事情を考慮してなさ
れたもので、より効率良く放熱し、メイン基板への実装
時にはハンダ付け温度設定を上昇させないように対策可
能なヒートシンクを備えた半導体パッケージを提供しよ
うとするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a heat sink capable of dissipating heat more efficiently and taking measures to prevent the soldering temperature setting from increasing when mounted on a main board. It is intended to provide.

【０００９】[0009]

【課題を解決するための手段】本発明に係る半導体パッ
ケージにおいては、主表面に複数の電極が形成された半
導体チップと、前記半導体チップを保護する封止部材
と、一端側が前記封止部材から外部へ伸び、他端側が前
記半導体チップの電極に電気的に接続される外部端子
と、より大きな表面積を有する側が前記封止部材から露
出しその反対側が前記半導体チップの主表面に固着され
る放熱用部材とを具備したことを特徴とする。In a semiconductor package according to the present invention, a semiconductor chip having a plurality of electrodes formed on a main surface; a sealing member for protecting the semiconductor chip; An external terminal that extends to the outside and has the other end electrically connected to the electrode of the semiconductor chip, and a heat radiator that has a larger surface area exposed from the sealing member and the opposite side fixed to the main surface of the semiconductor chip. And a member for use.

【００１０】上記本発明に係る半導体パッケージによれ
ば、放熱用部材は半導体チップの主表面側から発熱を吸
収する。放熱部材はより大きな表面積を有する側が封止
部材から露出しているので、外部雰囲気へ広がる放熱路
がより多く確保される。According to the semiconductor package of the present invention, the heat radiating member absorbs heat from the main surface side of the semiconductor chip. Since the side of the heat dissipating member having the larger surface area is exposed from the sealing member, more heat dissipating paths extending to the outside atmosphere are secured.

【００１１】また、本発明に係る半導体パッケージにお
いては、前記放熱用部材は、前記外部端子によるメイン
基板への実装後に装着される後付け構成であることを特
徴とする。Further, in the semiconductor package according to the present invention, the heat dissipating member has a retrofit structure that is mounted after the external terminal is mounted on the main board.

【００１２】上記本発明に係る半導体パッケージによれ
ば、メイン基板全体のハンダ付け温度設定を上昇させる
要因となる放熱用部材を外してメイン基板に実装できる
ことになる。According to the semiconductor package of the present invention, it is possible to remove the heat dissipating member, which is a factor for increasing the soldering temperature setting of the entire main board, and mount it on the main board.

【００１３】[0013]

【発明の実施の形態】図１は、本発明の第１実施形態に
係る半導体パッケージの構成を示す断面図である。半導
体チップ１１は、高速動作あるいは消費電力の大きい、
放熱を要するＩＣチップ（１１）である。ダイ１０に裏
面が固着されたＩＣチップ１１は、主表面に複数の電極
１２が形成され、例えばモールド樹脂による封止部材１
３により保護されている。外部端子１４は、その一端側
が上記封止部材１３から外部へ伸び、他端側がＩＣチッ
プ１１にボンディングワイヤ１５等を介して電気的に接
続されている。FIG. 1 is a sectional view showing the structure of a semiconductor package according to a first embodiment of the present invention. The semiconductor chip 11 operates at high speed or consumes large power.
This is an IC chip (11) requiring heat radiation. An IC chip 11 having a back surface fixed to a die 10 has a plurality of electrodes 12 formed on a main surface thereof.
3 protected. One end of the external terminal 14 extends from the sealing member 13 to the outside, and the other end is electrically connected to the IC chip 11 via a bonding wire 15 or the like.

【００１４】ヒートシンク１６は、より大きな表面積を
有する側が上記封止部材１３から露出し、その反対側が
ＩＣチップ１１の主表面に固着されている。すなわち、
ヒートシンク１６は、ＩＣチップ１１の電極１２が形成
されている周辺部以外の部分と熱伝導率の高い樹脂系の
接着剤（図示せず）を介して密着されている。The side of the heat sink 16 having a larger surface area is exposed from the sealing member 13, and the opposite side is fixed to the main surface of the IC chip 11. That is,
The heat sink 16 is in close contact with a portion other than the peripheral portion of the IC chip 11 where the electrodes 12 are formed, via a resin-based adhesive (not shown) having a high thermal conductivity.

【００１５】上記第１実施形態に係る半導体パッケージ
の構成によれば、ヒートシンク１６は、ＩＣチップ１１
の主表面側から発熱を吸収するようになっている。ヒー
トシンク１６は、より大きな表面積を有する側が封止部
材１３から露出しているので、外部雰囲気へ広がる放熱
路がより多く確保される。これにより、従来に比べて放
熱性の優れた半導体パッケージが実現できる。According to the configuration of the semiconductor package according to the first embodiment, the heat sink 16
Heat is absorbed from the main surface side of the. Since the side of the heat sink 16 having the larger surface area is exposed from the sealing member 13, more heat radiation paths extending to the outside atmosphere are secured. As a result, a semiconductor package having excellent heat dissipation as compared with the related art can be realized.

【００１６】図２は、図１の構成の半導体パッケージを
適用した、メイン基板への実装手法を示す断面図であ
る。上記ヒートシンク１６は、外部端子１４によるメイ
ン基板２１への実装後に装着される後付け構成であるこ
とを表している。FIG. 2 is a cross-sectional view showing a method for mounting the semiconductor package having the configuration shown in FIG. 1 on a main board. This shows that the heat sink 16 is a retrofit configuration that is mounted after the external terminals 14 are mounted on the main board 21.

【００１７】この図２のような実装手法を実現できる構
成であれば、ヒートシンク付きの半導体パッケージが、
実装時にメイン基板全体のハンダ付け温度設定を上昇さ
せることはない。すなわち、メイン基板全体のハンダ付
け温度設定を上昇させる要因となるヒートシンク１６を
外してメイン基板２１へ実装できるからである。If the mounting method as shown in FIG. 2 can be realized, the semiconductor package with a heat sink is
The soldering temperature setting of the entire main board is not increased during mounting. That is, the heat sink 16 which causes an increase in the soldering temperature setting of the entire main board can be removed and mounted on the main board 21.

【００１８】なお、ヒートシンク１６は、より大きな表
面積を有する側が封止部材１３から露出しその反対側が
ＩＣチップ１１の主表面に固着される形態であれば、上
記形状に限定されることはない。The shape of the heat sink 16 is not limited to the above shape as long as the side having the larger surface area is exposed from the sealing member 13 and the opposite side is fixed to the main surface of the IC chip 11.

【００１９】図３、図４は、それぞれ本発明に係るヒー
トシンクの変形例を示す断面図である。ヒートシンクが
装着される半導体パッケージは破線で示した。ヒートシ
ンク３６，４６のように、凹凸による表面積の拡大を図
る形態は容易に考えられる。また、図４のヒートシンク
４６ように、封止部材１３側面にまで延在させるような
形態をとってもよい。このような構成によって、より効
率的な放熱対策が実現される。FIGS. 3 and 4 are sectional views showing modified examples of the heat sink according to the present invention. The semiconductor package to which the heat sink is mounted is indicated by a broken line. As in the case of the heat sinks 36 and 46, a mode for increasing the surface area by the unevenness can be easily considered. Further, as in the heat sink 46 shown in FIG. 4, a form in which the heat sink 46 extends to the side surface of the sealing member 13 may be adopted. With such a configuration, more efficient heat dissipation measures are realized.

【００２０】もちろん、このような半導体パッケージの
メイン基板への実装の際、ヒートシンク３６または４６
は装着せず、メイン基板実装後に装着するといった、ハ
ンダ付け温度設定を上昇させないような対策も可能であ
る。Of course, when such a semiconductor package is mounted on the main substrate, the heat sink 36 or 46
It is also possible to take measures not to raise the soldering temperature setting, such as mounting after mounting the main board without mounting.

【００２１】さらに、上記各実施形態における、外部端
子のタイプ、外部端子とＩＣチップとの接続手段（ここ
ではボンディングワイヤ）は、限定されることはなく、
ＴＡＢ（Tape Automated Bonding）など他のタイプの外
部端子や接続手段が様々考えられる。Furthermore, in each of the above embodiments, the type of the external terminal and the means for connecting the external terminal to the IC chip (here, the bonding wire) are not limited.
There are various other types of external terminals and connection means such as TAB (Tape Automated Bonding).

【００２２】[0022]

【発明の効果】以上説明したように本発明の半導体パッ
ケージによれば、放熱部材（ヒートシンク）は、より大
きな表面積を有する側が封止部材から露出し、反対側は
半導体チップの主表面側から発熱を吸収するように装着
される。すなわち、半導体チップ主表面から外部雰囲気
へ広がる放熱路がより多く確保される。これにより、高
速動作、大きな消費電力を有する発熱量の大きいＩＣが
放熱性能を懸念することなく封止できる。さらに、この
放熱部材（ヒートシンク）は、メイン基板実装後の後付
けでも対応可能である。この結果、より効率良く放熱
し、メイン基板への実装時にはハンダ付け温度設定を上
昇させないように対策可能なヒートシンクを備えた半導
体パッケージを提供することができる。As described above, according to the semiconductor package of the present invention, the side of the heat radiating member (heat sink) having a larger surface area is exposed from the sealing member, and the opposite side generates heat from the main surface side of the semiconductor chip. Is installed to absorb the That is, more heat radiation paths extending from the main surface of the semiconductor chip to the outside atmosphere are secured. As a result, an IC that operates at high speed and consumes a large amount of heat and that has a large amount of heat can be sealed without concern about heat radiation performance. Further, this heat radiating member (heat sink) can be applied even after the main board is mounted. As a result, it is possible to provide a semiconductor package having a heat sink that can dissipate heat more efficiently and can take measures to prevent the setting of the soldering temperature from increasing when mounted on the main board.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態に係る半導体パッケージ
の構成を示す断面図である。FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor package according to a first embodiment of the present invention.

【図２】図１の構成の半導体パッケージを適用した、メ
イン基板への実装手法を示す断面図である。FIG. 2 is a cross-sectional view showing a method of mounting the semiconductor package having the configuration of FIG. 1 on a main board.

【図３】本発明に係るヒートシンクの変形例を示す第１
の断面図である。FIG. 3 is a first view showing a modification of the heat sink according to the present invention.
FIG.

【図４】本発明に係るヒートシンクの変形例を示す第２
の断面図である。FIG. 4 is a second view showing a modification of the heat sink according to the present invention.
FIG.

【図５】（ａ），（ｂ）は、それぞれ従来におけるヒー
トシンク付きの半導体パッケージの構成を示す断面図で
ある。FIGS. 5A and 5B are cross-sectional views each showing a configuration of a conventional semiconductor package with a heat sink.

【符号の説明】[Explanation of symbols]

１０…ダイ １１，５１…半導体チップ（ＩＣチップ） １２…電極 １３，５３…封止部材 １４，５４…外部端子 １５…ボンディングワイヤ １６，３６，４６，５６…ヒートシンク ２１…メイン基板 DESCRIPTION OF SYMBOLS 10 ... Die 11, 51 ... Semiconductor chip (IC chip) 12 ... Electrode 13, 53 ... Sealing member 14, 54 ... External terminal 15 ... Bonding wire 16, 36, 46, 56 ... Heat sink 21 ... Main board

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 主表面に複数の電極が形成された半導体
チップと、 前記半導体チップを保護する封止部材と、 一端側が前記封止部材から外部へ伸び、他端側が前記半
導体チップの電極に電気的に接続される外部端子と、 より大きな表面積を有する側が前記封止部材から露出し
その反対側が前記半導体チップの主表面に固着される放
熱用部材と、を具備したことを特徴とする半導体パッケ
ージ。A semiconductor chip having a plurality of electrodes formed on a main surface thereof; a sealing member for protecting the semiconductor chip; one end extending to the outside from the sealing member, and the other end forming an electrode of the semiconductor chip. A semiconductor, comprising: an external terminal to be electrically connected; and a heat-dissipating member having a side having a larger surface area exposed from the sealing member and the opposite side fixed to a main surface of the semiconductor chip. package. 【請求項２】 前記放熱用部材は、前記外部端子による
メイン基板への実装後に装着される後付け構成であるこ
とを特徴とする請求項１記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein said heat radiating member has a retrofit configuration mounted after said external terminal is mounted on a main board.
JP2000179897A 2000-06-15 2000-06-15 Semiconductor package Withdrawn JP2001358259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000179897A JP2001358259A (en) 2000-06-15 2000-06-15 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000179897A JP2001358259A (en) 2000-06-15 2000-06-15 Semiconductor package

Publications (1)

Publication Number Publication Date
JP2001358259A true JP2001358259A (en) 2001-12-26

Family

ID=18681084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000179897A Withdrawn JP2001358259A (en) 2000-06-15 2000-06-15 Semiconductor package

Country Status (1)

Country Link
JP (1) JP2001358259A (en)

Cited By (8)

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JP2004064093A (en) * 2002-07-26 2004-02-26 Stmicroelectronics Inc Method and system for removing heat from active area of integrated circuit device
US6946729B2 (en) * 2002-04-19 2005-09-20 Advanced Semiconductor Engineering, Inc. Wafer level package structure with a heat slug
US7071550B2 (en) 2004-02-03 2006-07-04 Kabushiki Kaisha Toshiba Semiconductor module having heat sink serving as wiring line
JP2006253168A (en) * 2005-03-08 2006-09-21 Tdk Corp Substrate having built-in semiconductor ic
US7554210B2 (en) 2002-09-05 2009-06-30 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
JP2014179602A (en) * 2013-03-13 2014-09-25 Freescale Semiconductor Inc Semiconductor device assembly having heat spreader
JP2018056538A (en) * 2016-09-26 2018-04-05 株式会社パウデック Semiconductor package, module, and electric device
CN111725160A (en) * 2020-06-16 2020-09-29 杰群电子科技（东莞）有限公司 High-power semiconductor module, packaging method and electronic product

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946729B2 (en) * 2002-04-19 2005-09-20 Advanced Semiconductor Engineering, Inc. Wafer level package structure with a heat slug
JP2004064093A (en) * 2002-07-26 2004-02-26 Stmicroelectronics Inc Method and system for removing heat from active area of integrated circuit device
US7554210B2 (en) 2002-09-05 2009-06-30 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
US7071550B2 (en) 2004-02-03 2006-07-04 Kabushiki Kaisha Toshiba Semiconductor module having heat sink serving as wiring line
JP2006253168A (en) * 2005-03-08 2006-09-21 Tdk Corp Substrate having built-in semiconductor ic
JP4595593B2 (en) * 2005-03-08 2010-12-08 Ｔｄｋ株式会社 Semiconductor IC built-in substrate
JP2014179602A (en) * 2013-03-13 2014-09-25 Freescale Semiconductor Inc Semiconductor device assembly having heat spreader
JP2018056538A (en) * 2016-09-26 2018-04-05 株式会社パウデック Semiconductor package, module, and electric device
JP2018093221A (en) * 2016-09-26 2018-06-14 株式会社パウデック Semiconductor package, module, and electric device
CN111725160A (en) * 2020-06-16 2020-09-29 杰群电子科技（东莞）有限公司 High-power semiconductor module, packaging method and electronic product

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