CN111725160A - High-power semiconductor module, packaging method and electronic product - Google Patents

High-power semiconductor module, packaging method and electronic product Download PDF

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Publication number
CN111725160A
CN111725160A CN202010549571.6A CN202010549571A CN111725160A CN 111725160 A CN111725160 A CN 111725160A CN 202010549571 A CN202010549571 A CN 202010549571A CN 111725160 A CN111725160 A CN 111725160A
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heat dissipation
epoxy resin
packaging material
packaging
layer
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CN202010549571.6A
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Chinese (zh)
Inventor
王琇如
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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Priority to CN202010549571.6A priority Critical patent/CN111725160A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737Organic materials with or without a thermoconductive filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The embodiment of the application discloses a high-power semiconductor module, a packaging method and an electronic product. According to the technical scheme, the chip arranged on the chip carrier is sealed and fixed through the insulating heat dissipation glue, the packaging material is used for packaging, and the sealing cover is carried out through the heat dissipation sealing cover layer. By adopting the technical means, the insulating heat dissipation glue can ensure the insulativity of the semiconductor element while providing a good heat dissipation effect of the semiconductor element, and the short circuit of a product caused by the conduction of a packaging material is avoided. And the element is covered by the heat dissipation covering layer, so that the heat dissipation effect of the element is optimized while the protection and fixation are provided. In addition, the packaging material of the embodiment of the application is formed by mixing epoxy resin and a radiator, the internal structure of the element can be protected by the epoxy resin, corrosion gas corrosion is avoided, and a good radiating effect is further provided by the radiator which is discretely arranged.

Description

High-power semiconductor module, packaging method and electronic product
Technical Field
The embodiment of the application relates to the technical field of semiconductor packaging, in particular to a high-power semiconductor module, a packaging method and an electronic product.
Background
The semiconductor is a material with a conductive capability between a conductor and a non-conductor, and the semiconductor element belongs to a solid element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely introduced in the technical field of electronics. In the case of a high power semiconductor device, the heat dissipation performance is an important index for evaluating the operational reliability and stability of the high power semiconductor device. Particularly in a high-heat working environment, it is a very important issue to maintain good heat dissipation performance of the semiconductor element.
Disclosure of Invention
The embodiment of the application provides a high-power semiconductor module, which can provide good heat dissipation performance of elements.
In a first aspect, the embodiment of the application provides a high power semiconductor module, be in including chip carrier, setting chip, the cover at chip carrier top are in the insulating heat dissipation of chip top is glued and is covered the insulating heat dissipation that glues the top and be used for carrying out the packaging material of plastic envelope, the chip carrier include the base plate and paste cover in the copper foil of base plate top and bottom, packaging material's top cover one deck heat dissipation capping layer, insulating heat dissipation glue packaging material and the week portion of heat dissipation capping layer is provided with and is used for connecting insulating heat dissipation glue packaging material and the annular connecting portion of heat dissipation capping layer.
Preferably, a groove is formed in the edge of the top of the substrate, a protrusion is arranged at one end, close to the substrate, of the annular connecting part, and the protrusion is clamped in the groove to enable the bottom of the annular connecting part to be connected with the substrate; the inner side of one end, far away from the groove, of the annular connecting portion is provided with a buckle, and the edge of the heat dissipation sealing layer is clamped and fixed with the buckle.
Preferably, the heat dissipation capping layer is a copper foil.
Preferably, the packaging material comprises epoxy resin and a radiator, the radiator is in a discrete state and is mixed with the epoxy resin, and the radiator is an insulating radiator and comprises a radiating inner core and an insulating layer completely coated outside the radiating inner core.
Preferably, the heat dissipation inner core is graphene or carbide.
In a second aspect, embodiments of the present application provide a semiconductor packaging method, including:
s1, providing a chip carrier;
s2, bonding a chip to the surface of the chip carrier by using a bonding material, wherein the bonding material is a welding material or epoxy resin;
s3, baking and curing the bonding material;
s4, covering the chip with insulating heat dissipation glue;
s5, baking and curing the insulating heat dissipation adhesive;
s6, covering the top of the insulating heat dissipation adhesive with a packaging material for plastic package, wherein the packaging material comprises epoxy resin and a heat dissipation body, and the heat dissipation body is mixed with the epoxy resin in a discrete state;
s7, baking and curing the packaging material;
and S8, covering a heat dissipation sealing layer on the top of the packaging material.
Further, use packaging material to cover carry out the plastic envelope at insulating heat dissipation glue top, include:
s61, preparing the packaging material;
and S62, performing injection molding packaging by using the packaging material.
Further, preparing the packaging material comprises:
preparing and mixing a radiator according to the mass fraction of 40-60 and epoxy resin according to the mass fraction of 60-40 to prepare the packaging material; alternatively, the first and second electrodes may be,
providing a first epoxy resin layer, arranging a radiator on the surface of the first epoxy resin layer, providing a second epoxy resin layer, covering the second epoxy resin layer on the surface of the first epoxy resin layer provided with the radiator, enabling the radiator to be located between the first epoxy resin layer and the second epoxy resin layer to form a laminated structure, and thermally pressing the laminated first epoxy resin layer and the second epoxy resin layer to enable the first epoxy resin layer and the second epoxy resin layer to be fused.
In a third aspect, an embodiment of the present application provides an electronic product, which includes the high power semiconductor module according to the first aspect of the present application.
In a fourth aspect, the present application provides an electronic product, including a semiconductor device, which is formed by packaging using the semiconductor packaging method according to the second aspect of the present application.
The high power semiconductor module that this application embodiment provided seals fixedly through using insulating heat dissipation to set up the chip on the chip carrier, uses packaging material to encapsulate and carry out the closing cap through heat dissipation capping layer. By adopting the technical means, the insulating heat dissipation glue can ensure the insulativity of the semiconductor element while providing a good heat dissipation effect of the semiconductor element, and the short circuit of a product caused by the conduction of a packaging material is avoided. And the element is covered by the heat dissipation covering layer, so that the heat dissipation effect of the element is optimized while the protection and fixation are provided.
In addition, the packaging material of the embodiment of the application is formed by mixing epoxy resin and a radiator, the internal structure of the element can be protected by the epoxy resin, corrosion gas corrosion is avoided, and a good radiating effect is further provided by the radiator which is discretely arranged.
Drawings
Fig. 1 is a schematic structural diagram of a high power semiconductor module according to an embodiment of the present disclosure;
FIG. 2 is a schematic view of the connection of the plastic housing with the substrate and the heat dissipation package layer in the embodiment of the present application;
fig. 3 is a schematic structural diagram of a heat sink according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of another heat sink provided in an embodiment of the present application;
fig. 5 is a flowchart of a semiconductor packaging method according to an embodiment of the present application;
FIG. 6 is a flow chart of a process for preparing a packaging material according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of an encapsulation material provided in an embodiment of the present application.
In the figure, 11, a substrate; 12. copper foil; 13. a chip; 14. an epoxy resin; 15. a heat sink; 151. an insulating layer; 152. a heat dissipation inner core; 153. silver particles; 16. a plastic housing; 161. a protrusion; 162. buckling; 17. insulating heat dissipation glue; 18. and a heat dissipation capping layer.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The application provides a high power semiconductor module, when aiming at carrying out the semiconductor component encapsulation, use insulating heat dissipation to glue and cover the chip, further use epoxy to mix the radiator and carry out the encapsulation as packaging material to the chip of moulding plastics, the rethread heat dissipation capping layer replaces traditional plastic housing closing cap packaging material. The heat dissipation capping layer can provide element structure protection and good heat dissipation performance, the insulating heat dissipation glue can provide good insulating heat dissipation performance, the epoxy resin of the packaging material can protect the internal structure of the element and avoid corrosion gas erosion, and the heat dissipation body in discrete arrangement can also provide good heat dissipation effect. Therefore, the internal structure of the element can be protected, and meanwhile, good heat dissipation performance is provided, and the working reliability and stability of the semiconductor element are guaranteed. Compared with the traditional high-power semiconductor element, when a chip is packaged, the chip is generally packaged in a mode of sequentially filling silicone gel and silicone rubber, and the effects of protecting the internal structure of the element and preventing corrosive gas corrosion are realized through two polymers. However, the package using the above-mentioned packaging material cannot provide a good heat dissipation effect, and the packaging process is relatively complicated. For high power semiconductor components, their operational reliability and stability are susceptible. Therefore, the high-power semiconductor module provided by the embodiment of the application is provided to solve the technical problem that the existing high-power semiconductor element is poor in heat dissipation performance.
Example (b):
fig. 1 shows a schematic structural diagram of a high power semiconductor module according to an embodiment of the present disclosure, and referring to fig. 1, the high power semiconductor module specifically includes: the chip carrier comprises a chip carrier, a chip 13 arranged at the top of the chip carrier, an insulating heat dissipation adhesive 17 covering the top of the chip 13 and a packaging material covering the top of the insulating heat dissipation adhesive 17 and used for plastic packaging, the chip carrier comprises a substrate 11 and copper foils 12 attached to the top and the bottom of the substrate 11, a heat dissipation cover layer 18 covers the top of the packaging material, the periphery of the insulating heat dissipation adhesive 17, the packaging material and the heat dissipation cover layer 18 is provided with an annular connecting part used for connecting the insulating heat dissipation adhesive 17, the packaging material and the heat dissipation cover layer 18, and the annular connecting part is a plastic shell 16. The packaging material comprises epoxy resin 14 and a radiator 15, wherein the radiator 15 is mixed with the epoxy resin 14 in a discrete state.
In the embodiment of the application, a layer of heat dissipation capping layer 18 is arranged on the top of the packaging material, the heat dissipation capping layer 18 is made of copper foil or copper sheet, and the heat dissipation capping layer 18 replaces the traditional plastic shell mode for final capping of the semiconductor element, so that good heat dissipation performance is provided, and the heat dissipation effect of the semiconductor element is further optimized. Moreover, it should be noted that, in the embodiment of the present application, the heat dissipation capping layer 18 is directly used to replace the plastic housing to cap the top of the semiconductor device, so as to achieve the effect of capping the protection device and providing good heat dissipation. In addition, the plastic shell 16 is arranged on the periphery of the insulating heat dissipation glue 17, the packaging material and the heat dissipation cover layer 18, and the plastic shell 16 can provide a structural protection function outside the whole element. Moreover, because the top of the semiconductor is provided with three layers of heat dissipation packaging materials, namely the insulating heat dissipation glue 17, the packaging material and the heat dissipation packaging cover layer 18, the three layers of heat dissipation packaging materials can be connected and fixed through the plastic shell 16, so that the situation of cracking among all layers is avoided, and a better protection effect of the semiconductor module is provided.
Specifically, in an embodiment, as shown in fig. 2, a groove is disposed at a top edge of the substrate 11, a protrusion 161 is disposed at one end of the plastic casing 16 close to the substrate 11, and the protrusion 161 is engaged with the groove to connect a bottom of the plastic casing 16 to the substrate 11; a buckle 162 is arranged on the inner side of one end of the plastic shell 16 far away from the groove, and the edge of the heat dissipation cover layer 18 is fixed with the buckle 162 in a clamping manner. By the two clamping structures, the annular connecting part and the heat dissipation sealing cover layer 18 can be conveniently used for carrying out the final sealing process of the semiconductor module, so that the sealing process is simple and convenient to operate.
The packaging material used in the embodiment of the application has good heat dissipation performance and sealing protection performance, and can obtain a better heat dissipation effect compared with the traditional mode of packaging by using silica gel and silicone rubber or directly packaging by using epoxy resin 14. The semiconductor packaged by the packaging method can be applied to products with more high power, such as 2.5IC products, 3DIC products, SIP modules or power modules and other products with large heat generation quantity.
Further, referring to fig. 1, in the embodiment of the present application, a layer of insulating heat dissipation adhesive 17 is further disposed between the packaging material and the chip 13, and the insulating heat dissipation adhesive 17 covers the chip 13, so as to further provide a good heat dissipation effect. And because of the insulating characteristic of insulating heat dissipation 17, can guarantee the insulating properties of chip 13 while providing the good radiating effect of chip 13, avoid the condition that chip 13 electric leakage causes the short circuit. The insulating and heat dissipating adhesive 17 may cover only the corresponding range of the chip 13, or may cover the corresponding range of the entire substrate. The insulating heat-dissipating adhesive 17 can be a single-component room-temperature-vulcanized silicone adhesive, has the characteristics of convenience in use, high bonding strength, elasticity after curing, impact resistance, vibration resistance and the like, and simultaneously, a cured product also has good heat conduction and heat dissipation functions and excellent high-low temperature resistance and electrical performance.
Furthermore, in the embodiment of the present application, a heat dissipation layer (not shown) is further covered on the top of the package material, and then the top of the heat dissipation layer is covered, and the heat dissipation layer adopts graphene or high heat dissipation carbide to provide good heat dissipation performance, so as to further optimize the heat dissipation effect of the semiconductor element. In addition, when the heat dissipation capping layer 18 is capped, the capping layer may be directly capped on the sealing material, or may be capped on the heat dissipation layer.
Preferably, referring to fig. 3, the heat sink 15 is an insulating heat sink, and includes a heat dissipation core 152 and an insulating layer 151 completely covering the heat dissipation core 152. According to the embodiment of the application, the insulating heat radiator 15 is discretely arranged in the packaging material, the specific heat capacity of the heat radiator 15 absorbs part of heat, and on the other hand, the heat transfer in the packaging material can be accelerated, so that the heat dissipation effect of a semiconductor product is improved. The insulated heat sink 15 has good heat conduction performance and insulation performance, and can ensure the insulation performance of the product through the insulating layer 151 while improving the heat dissipation effect of the semiconductor product through the heat dissipation inner core 152, thereby avoiding the short circuit of the product caused by the conduction of the packaging material.
Specifically, the heat dissipation core 152 has a spherical structure, a columnar structure, or a cubic structure. As shown in fig. 3, the heat dissipation core 152 of the heat dissipation body 15 has a spherical structure, and the spherical heat dissipation body 15 is covered by the insulating layer 151. It should be noted that the structure of the heat radiator 15 of the present application is not limited to the spherical structure described above, and a columnar structure, a cubic structure, a bar structure, or an elliptical structure may also be adopted in some embodiments. The insulator is mainly required to have an insulating layer 151 wrapped outside and a heat dissipation core 152 having good heat dissipation performance disposed inside, and its shape is not limited.
In one embodiment, referring to fig. 4, a schematic structural diagram of another heat sink 15 is provided. In addition to the spherical heat sink 15, the heat sink 15 further includes silver particles 153 discretely arranged in the heat sink core 152. The silver particles 153 are metal having excellent thermal conductivity, and have a thermal conductivity of 400W/m · K, which further optimizes the heat dissipation effect of the heat sink 15.
In one embodiment, the heat spreader 15 is completely encapsulated by the epoxy 14 in an encapsulation material in which the heat spreader 15 is mixed with the epoxy 14. The heat radiator 15 needs to keep a certain distance from the edge position of the epoxy resin 14, so that the insulating layer 151 outside the heat radiator 15 forms primary insulating seal, the epoxy resin 14 simultaneously realizes secondary insulating seal, and the insulating property of the product is ensured. Further, the distance from the heat sink 15 to the edge of the sealing material may be set within a fixed distance range according to actual needs. In one embodiment, the distance of the heat sink 15 from the edge position of the encapsulation material may be set equal to the diameter of the heat sink 15. In other embodiments, the distance between the heat sink 15 closest to the edge of the encapsulation material and the edge of the encapsulation material may also be larger than the diameter of the heat sink 15, or smaller than the diameter of the heat sink 15. The difference between the above schemes lies in the difference between the heat dissipation effect and the insulation effect, and it can be understood that when a better heat dissipation effect is required, the minimum distance between the heat sink 15 and the edge of the packaging material can be selected to be reduced, and the distance between the adjacent heat sinks 15 is reduced at the same time; when a better insulation effect is required, the minimum distance between the heat radiator 15 and the edge of the packaging material can be selected to be increased, and the distance between adjacent heat radiators 15 can be increased.
In the actual working process of the semiconductor element, heat is diffused from the chip 13 to the packaging material, and is firstly diffused from the epoxy resin 14 of the packaging material, when the heat is expanded to the heat radiator 15, the heat is transferred to the heat radiating inner core 152 through the insulating layer 151, and because the heat radiating inner core 152 has good heat radiation performance, the heat is rapidly diffused at the moment and is transferred to all directions through the heat radiator 15, so that the transfer speed of the heat in the packaging material can be accelerated, and the heat radiation effect is improved.
Specifically, the dimensional relationship between the heat dissipation core 152 and the insulating layer 151 in this embodiment also affects the insulation and heat dissipation performance of the packaging material. The ratio of the diameter of the heat dissipation core 152 to the thickness of the insulating layer 151 is 5: 1. In another embodiment, the ratio of the diameter of the heat dissipation core 152 to the thickness dimension of the insulating layer 151 is 4: 1. In yet another preferred embodiment, the ratio of the diameter of the heat dissipation core 152 to the thickness dimension of the insulating layer 151 is 3: 1. It can be understood that the larger the ratio of the diameter of the heat dissipation core 152 to the thickness of the insulating layer 151 is, the better the heat dissipation effect of the product is, and on the contrary, the relatively thinner the insulating layer 151 is, the lower the insulation effect is compared with the small ratio.
In the embodiment of the present application, the insulators may be randomly arranged in the epoxy resin 14 in a manner that the distance between adjacent insulators is different, only the distance between the insulator closest to the edge position of the encapsulating material and the edge position of the encapsulating material is defined, and the reliability of the insulating effect is ensured by the distance. It should be noted that the arrangement of the insulators is not limited to the same distance, and in some embodiments, the same distance may be used between adjacent insulators.
More specifically, the heat dissipation core 152 of the heat dissipation body 15 is graphene or carbide. Graphene has very good thermal conductivity. The pure defect-free single-layer graphene has the thermal conductivity coefficient as high as 5300W/mK, is the carbon material with the highest thermal conductivity coefficient so far, and is higher than that of a single-wall carbon nanotube (3500W/mK) and a multi-wall carbon nanotube (3000W/mK). When it is used as the carrier 100, the thermal conductivity can also reach 600W/mK. Therefore, the heat radiator 15 with graphene is arranged in the packaging material, so that a plurality of heat radiating islands with good heat radiating effect are formed in the packaging material, and the heat at the chip 13 is quickly diffused to the outside of the packaging material by utilizing the heat absorption and heat conduction effects of the heat radiating islands. And the carbide adopts high heat dissipation carbide, and the high heat dissipation carbide also has good heat dissipation performance. It should be noted that, in some embodiments, the heat dissipation core 152 may be replaced by another heat conductive material with good heat dissipation performance. According to the actual heat dissipation performance requirement, a corresponding material can be adaptively selected as the heat dissipation core 152. In the embodiment of the present invention, the insulating layer 151 covering the heat dissipation core 152 may be made of an insulating material having good insulating properties, such as rubber or resin.
In a second aspect, referring to fig. 5, an embodiment of the present application further provides a semiconductor packaging method, including:
s1, providing a chip carrier;
s2, bonding a chip to the surface of the chip carrier by using a bonding material, wherein the bonding material is a welding material or epoxy resin;
s3, baking and curing the bonding material;
s4, covering the chip with insulating heat dissipation glue;
s5, baking and curing the insulating heat dissipation adhesive;
s6, covering the top of the insulating heat dissipation adhesive with a packaging material for plastic package, wherein the packaging material comprises epoxy resin and a heat dissipation body, and the heat dissipation body is mixed with the epoxy resin in a discrete state;
s7, baking and curing the packaging material;
and S8, covering a heat dissipation sealing layer on the top of the packaging material.
Specifically, in semiconductor packaging, a chip carrier is provided to house the chip 13. The chip carrier includes a substrate 11 and copper foils 12 covering both upper and lower surfaces of the substrate 11. The substrate 11 is made of a ceramic material, which facilitates heat dissipation of the semiconductor device. The chip 13 is further bonded to the chip carrier. The bonding of the chip 13 may be performed by soldering or bonding. Correspondingly, when the chip 13 is jointed, a welding object is provided for welding the chip 13 or epoxy resin 14 is provided for bonding the chip 13. After the bonding of the chip 13 is completed, the bonding material is cured by baking to fix the chip 13 to the chip carrier. If a wire is required between the chips, the chips 13 are connected by bonding wires. After the bonding of the chip 13 is completed, the chip 13 is covered with the insulating and heat-dissipating adhesive 17.
After the insulating and heat dissipating adhesive 17 is covered, the chip 13 can be plastically packaged by using a packaging material. The chip 13 is injection molded using the epoxy resin 14 hybrid heat spreader 15 as an encapsulating material, and the top of the encapsulating material is further capped using a copper foil. Thereby providing a good heat dissipation effect for the semiconductor device. Referring to fig. 6, the plastic packaging of the chip 13 with a packaging material includes:
s61, preparing the packaging material;
and S62, performing injection molding packaging by using the packaging material.
It can be understood that, in the embodiment of the present application, the chip 13 is encapsulated by injection molding, and before this, the encapsulating material needs to be prepared in advance, so as to complete the injection molding encapsulation process at a time later. Compared with the traditional mode of sequentially filling and packaging silicon gel and silicon rubber, the heat dissipation and sealing protection device has the advantages that the heat dissipation and sealing protection effect is provided, and meanwhile, the packaging process is simplified. Further, when the packaging material is prepared, preparing and mixing the heat radiator 15 according to the mass fraction of 40-60 and the epoxy resin 14 according to the mass fraction of 60-40 to prepare the packaging material; alternatively, as shown in fig. 7, a first epoxy resin 14 layer is provided, a layer of a radiator 15 is arranged on the surface of the first epoxy resin 14 layer, a second epoxy resin 14 layer is provided, the second epoxy resin 14 layer is covered on the surface of the first epoxy resin 14 layer provided with the radiator 15, the radiator 15 is positioned between the first epoxy resin 14 layer and the second epoxy resin 14 layer to form a laminated structure, and the laminated first epoxy resin 14 layer and the second epoxy resin 14 layer are hot-pressed, so that the first epoxy resin 14 layer and the second epoxy resin 14 layer are fused. There are many ways to prepare the encapsulation material by mixing the epoxy resin 14 and the heat sink 15, and the embodiment of the present application is not limited thereto.
Specifically, the preparation process of the encapsulating material is not limited to the above technical scheme of having two epoxy resin layers and disposing the heat sink 15 between the two epoxy resin layers, the number of the epoxy resin layers in the specific implementation process may be set to be multiple layers according to actual needs, and the thickness of each layer may be selected differently according to different heat dissipation and insulation requirements. The preparation process of the packaging material is not limited to the above-mentioned structure of laminating multiple epoxy resin layers, and the heat sink 15 and the epoxy resin 14 can be mixed and molded, and the epoxy resin layer is arranged on the surface of the molded material for insulation, so as to prevent the heat sink 15 from being located at the edge position in the mixing and molding process and affecting the insulation effect. In addition, when the heat radiators 15 are disposed on the epoxy resin layer, they may be disposed at regular intervals or may be disposed at random intervals on the epoxy resin layer. In some embodiments, the number of the heat sinks 15 disposed on each epoxy layer is fixed, so that the heat dissipation effect of each epoxy layer is uniform.
In one embodiment, a hybrid manufacturing process for the above-described encapsulant is provided. The preparation process comprises the following steps:
(1) placing graphite and NaNO3 into a flask, adding sulfuric acid, adding KMnO4 into the flask, keeping the temperature at 35-55 ℃, fully stirring for 5-9 hours, after the reaction is finished, adding deionized water into the flask to raise the temperature to 80-95 ℃, keeping the temperature for 15-20 minutes, cooling the solution to room temperature, injecting hydrogen peroxide and deionized water, washing with water and acid, taking out the product, and placing the product into a vacuum drying oven for drying to obtain graphene;
(2) dissolving the graphene obtained in the step (1) in an insulating material, and fully and uniformly stirring to obtain a heat radiator 15 coated with an insulating layer 151;
(3) configuring a radiator 15 according to the mass fraction of 40-60, configuring an epoxy resin 14 according to the mass fraction of 60-40, and stirring for 5-10 min at the revolution speed of 1500-2000 rpm and the rotation speed of 800-1000 rpm by using a planetary vacuum stirring defoaming machine to fully mix the radiator 15 and the epoxy resin 14;
(4) and (4) coating a layer of epoxy resin 14 on the periphery of the mixture of the epoxy resin 14 and the radiator 15 obtained in the step (3), and finally obtaining the packaging material.
The chip arranged on the chip carrier is sealed and fixed by the insulating heat dissipation glue, packaged by the packaging material and capped by the heat dissipation capping layer. By adopting the technical means, the insulating heat dissipation glue can ensure the insulativity of the semiconductor element while providing a good heat dissipation effect of the semiconductor element, and the short circuit of a product caused by the conduction of a packaging material is avoided. And the element is covered by the heat dissipation covering layer, so that the heat dissipation effect of the element is optimized while the protection and fixation are provided. In addition, the packaging material of the embodiment of the application is formed by mixing epoxy resin and a radiator, the internal structure of the element can be protected by the epoxy resin, corrosion gas corrosion is avoided, and a good radiating effect is further provided by the radiator which is discretely arranged.
Meanwhile, the embodiment of the invention also provides an electronic product which is provided with the high-power semiconductor module.
The embodiment of the invention also provides an electronic product which comprises the semiconductor device, wherein the semiconductor device is formed by packaging by adopting the semiconductor packaging method.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.

Claims (10)

1. A high power semiconductor module, comprising: the chip carrier comprises a substrate and copper foils attached to the top and the bottom of the substrate, the top of the packaging material is covered with a heat dissipation sealing layer, and the peripheral parts of the insulating heat dissipation adhesive, the packaging material and the heat dissipation sealing layer are provided with annular connecting parts for connecting the insulating heat dissipation adhesive, the packaging material and the heat dissipation sealing layer.
2. The high power semiconductor module as claimed in claim 1, wherein a groove is formed at a top edge of the substrate, a protrusion is formed at an end of the annular connecting portion close to the substrate, and the protrusion engages with the groove to connect a bottom of the annular connecting portion to the substrate; the inner side of one end, far away from the groove, of the annular connecting portion is provided with a buckle, and the edge of the heat dissipation sealing layer is clamped and fixed with the buckle.
3. The high power semiconductor module of claim 1, wherein the heat dissipation capping layer is a copper foil.
4. The high power semiconductor module of claim 1, wherein the encapsulation material comprises epoxy and a heat sink, the heat sink being mixed with the epoxy in a discrete state.
5. The high power semiconductor module of claim 3, wherein the heat sink is an insulating heat sink, and comprises a heat dissipation core and an insulating layer completely covering the heat dissipation core, and the heat dissipation core is made of graphene or carbide.
6. A semiconductor packaging method, comprising:
s1, providing a chip carrier;
s2, bonding a chip to the surface of the chip carrier by using a bonding material, wherein the bonding material is a welding material or epoxy resin;
s3, baking and curing the bonding material;
s4, covering the chip with insulating heat dissipation glue;
s5, baking and curing the insulating heat dissipation adhesive;
s6, covering the top of the insulating heat dissipation adhesive with a packaging material for plastic package, wherein the packaging material comprises epoxy resin and a heat dissipation body, and the heat dissipation body is mixed with the epoxy resin in a discrete state;
s7, baking and curing the packaging material;
and S8, covering a heat dissipation sealing layer on the top of the packaging material.
7. The semiconductor packaging method according to claim 6, wherein the plastic packaging is performed by covering the top of the insulating heat dissipation adhesive with a packaging material, and comprises the following steps:
s61, preparing the packaging material;
and S62, performing injection molding packaging by using the packaging material.
8. The semiconductor packaging method according to claim 7, wherein preparing the packaging material comprises:
preparing and mixing a radiator according to the mass fraction of 40-60 and epoxy resin according to the mass fraction of 60-40 to prepare the packaging material; alternatively, the first and second electrodes may be,
providing a first epoxy resin layer, arranging a radiator on the surface of the first epoxy resin layer, providing a second epoxy resin layer, covering the second epoxy resin layer on the surface of the first epoxy resin layer provided with the radiator, enabling the radiator to be located between the first epoxy resin layer and the second epoxy resin layer to form a laminated structure, and thermally pressing the laminated first epoxy resin layer and the second epoxy resin layer to enable the first epoxy resin layer and the second epoxy resin layer to be fused.
9. An electronic product, characterized in that, has the high power semiconductor module of any one of claims 1-5.
10. An electronic product comprising a semiconductor device, wherein the semiconductor device is formed by packaging according to the semiconductor packaging method of any one of claims 6 to 8.
CN202010549571.6A 2020-06-16 2020-06-16 High-power semiconductor module, packaging method and electronic product Pending CN111725160A (en)

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Application publication date: 20200929