JP6124810B2 - Power module - Google Patents

Power module Download PDF

Info

Publication number
JP6124810B2
JP6124810B2 JP2014005583A JP2014005583A JP6124810B2 JP 6124810 B2 JP6124810 B2 JP 6124810B2 JP 2014005583 A JP2014005583 A JP 2014005583A JP 2014005583 A JP2014005583 A JP 2014005583A JP 6124810 B2 JP6124810 B2 JP 6124810B2
Authority
JP
Japan
Prior art keywords
terminal
ceramic substrate
conductor layer
case
bridging member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014005583A
Other languages
Japanese (ja)
Other versions
JP2015133462A (en
Inventor
藤野 純司
純司 藤野
三紀夫 石原
三紀夫 石原
山田 浩司
浩司 山田
正行 眞舩
正行 眞舩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2014005583A priority Critical patent/JP6124810B2/en
Publication of JP2015133462A publication Critical patent/JP2015133462A/en
Application granted granted Critical
Publication of JP6124810B2 publication Critical patent/JP6124810B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45624Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Inverter Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

この発明は、パワーモジュールに関し、特に、端子が樹脂で封止されているパワーモジュールに関する。   The present invention relates to a power module, and particularly to a power module in which terminals are sealed with resin.

パワーモジュールは、発電と送電の分野だけではなく、効率的なエネルギーの利用と再生を目指すあらゆる場面で利用されている。家電に搭載されるモジュールについては、小型軽量であるとともに多品種に対応できる高い生産性と高い信頼性が求められる。一方、SiC半導体は動作温度が高く、効率に優れている点で、今後のパワーモジュールの主流半導体素子となることが期待されている。このためパワーモジュールはSiC半導体に適用できるパッケージ形態であることも求められている。   Power modules are used not only in the fields of power generation and transmission, but also in all situations where efficient energy use and regeneration are aimed. Modules mounted on home appliances are required to have high productivity and high reliability that are small and light and can be used in a wide variety of products. On the other hand, SiC semiconductors are expected to become mainstream semiconductor elements for future power modules because of their high operating temperature and excellent efficiency. For this reason, the power module is also required to have a package form applicable to a SiC semiconductor.

パワーモジュールの普及は、産業機器から家電情報端末まであらゆる製品に進展している。電力半導体素子の信号端子は、放熱の必要がないので、通常、ケースの外周部に配置される。信号端子はインダクタンスの低減を目的に中央部に配置されている(例えば特許文献1)。   The spread of power modules has progressed to every product from industrial equipment to home appliance information terminals. Since the signal terminals of the power semiconductor elements do not need to be radiated, they are usually arranged on the outer periphery of the case. The signal terminal is arranged at the center for the purpose of reducing inductance (for example, Patent Document 1).

特許第4829690号公報Japanese Patent No. 4829690

パワーモジュールは、高電圧と大電流を扱う半導体の特徴を備えている。回路を絶縁封止するため、パワーモジュールのケースはシリコーンゲルなどで充填される。多くの場合、リードフレームは金型を用いてトランスファモールド封止されている。シリコーンゲル自体は柔軟なため、ゲルの上面はエポキシ樹脂などで覆い固められる。トランスファモールドを行うには工期が長く高額な金型が必要になる。そこで、ケース内に樹脂を流し込んだ後に加熱硬化させることで絶縁封止を実現するダイレクトポッティング封止が検討され始めている。   The power module has the characteristics of a semiconductor that handles high voltage and large current. In order to insulate and seal the circuit, the case of the power module is filled with silicone gel or the like. In many cases, the lead frame is transfer-molded using a mold. Since the silicone gel itself is flexible, the upper surface of the gel is covered with an epoxy resin or the like. To perform transfer molding, a long construction period and an expensive mold are required. Therefore, direct potting sealing that realizes insulating sealing by pouring resin into the case and then heat-curing has begun to be studied.

ダイレクトポッティング封止は、金型が不要で、ゲル封止に比較すると信頼性に優れているが、封止樹脂のケースに対する密着力は低い。樹脂の硬化収縮や基材との膨張係数ミスマッチが存在すると封止樹脂とケースとの界面で樹脂の剥離が生じる。封止樹脂の剥離はケースの外周部に発生しやすく、信号端子に接続するワイヤボンドには破断が引き起こされる。   Direct potting sealing does not require a mold and is more reliable than gel sealing, but the adhesion of the sealing resin to the case is low. If there is a cure shrinkage of the resin or an expansion coefficient mismatch with the substrate, the resin peels off at the interface between the sealing resin and the case. The peeling of the sealing resin is likely to occur on the outer periphery of the case, and the wire bond connected to the signal terminal is broken.

信号端子は放熱が不要にも関わらずセラミック基板や金属基板を占有することとなり、大型化や重量増大の要因となっている。また、信号端子はワイヤボンドツールとの干渉を防ぐためにある程度の大きさが必要であり、パワーモジュールを小型化する際の障壁となっている。ワイヤボンドを、信号端子から電力半導体素子の順に打つことで、ケースの信号端子を小さくすることはできるが、電力半導体素子の上でワイヤを切断することによるカッターの衝撃で電力半導体素子が破壊することが懸念されている。   The signal terminal occupies a ceramic substrate or a metal substrate even though it does not need to dissipate heat, which is a factor in increasing the size and weight. Further, the signal terminal needs to have a certain size in order to prevent interference with the wire bond tool, which is a barrier when the power module is downsized. The signal terminal of the case can be made smaller by hitting wire bonds in order from the signal terminal to the power semiconductor element, but the power semiconductor element is destroyed by the impact of the cutter by cutting the wire on the power semiconductor element. There are concerns.

この発明は、以上のような課題を鑑みて成されたもので、パワーモジュールにおける出力端子の信頼性を向上することを目指している。   The present invention has been made in view of the above-described problems, and aims to improve the reliability of output terminals in a power module.

本発明に係るパワーモジュールは、第1主面には外周に第1余白部を残して第1導体層が形成されており、第2主面には外周に第2余白部を残して第2導体層が形成されているセラミック基板と、セラミック基板の第2導体層に固定されているダイオードと、制御電
極を有しセラミック基板の第2導体層に固定されているトランジスタと、セラミック基板の第2導体層に接続されている第1端子と、ダイオードおよびトランジスタを接続する第2端子と、トランジスタの制御電極とワイヤで接続されている第3端子と、第2端子に固定され第3端子を保持する絶縁性の第1橋渡し部材と、セラミック基板に固定され第1端子と第2端子を保持する絶縁性の第2橋渡し部材と、セラミック基板に接着され、ダイオードとトランジスタと第1端子と第2端子と第3端子と第1橋渡し部材と第2橋渡し部材を収容するケースと、ケースの内側に充填された封止樹脂部材と、を備え、第1端子および第2端子は一部が第2橋渡し部材に固定され、第3端子は先端が封止樹脂部材から突出していることを特徴とする。
In the power module according to the present invention, the first main surface has the first conductor layer formed on the outer periphery leaving the first margin, and the second main surface has the second margin on the outer periphery. A ceramic substrate on which a conductor layer is formed; a diode fixed to the second conductor layer of the ceramic substrate; a transistor having a control electrode and fixed to the second conductor layer of the ceramic substrate; A first terminal connected to the two conductor layers, a second terminal connecting the diode and the transistor, a third terminal connected to the control electrode of the transistor by a wire, and a third terminal fixed to the second terminal An insulating first bridging member to be held, an insulating second bridging member fixed to the ceramic substrate and holding the first terminal and the second terminal, and bonded to the ceramic substrate, the diode, the transistor, and the first terminal A case containing the second terminal, the third terminal, the first bridging member and the second bridging member, and a sealing resin member filled inside the case, wherein the first terminal and the second terminal are partially The third terminal is fixed to the second bridging member, and the tip of the third terminal protrudes from the sealing resin member .

ケースの周辺部から封止樹脂部材が硬化収縮や熱膨張係数差により剥離したとしても、橋渡し部材は第3端子(信号端子)を破断から保護することができる。   Even if the sealing resin member is peeled off from the periphery of the case due to curing shrinkage or a difference in thermal expansion coefficient, the bridging member can protect the third terminal (signal terminal) from breaking.

実施の形態1によるパワーモジュールの概念断面図である。1 is a conceptual cross-sectional view of a power module according to Embodiment 1. FIG. 実施の形態1によるパワーモジュールの概念上面図である。1 is a conceptual top view of a power module according to Embodiment 1. FIG. セラミック基板に電力半導体素子が接合された状態を表す平面図である。It is a top view showing the state by which the power semiconductor element was joined to the ceramic substrate. セラミック基板に電力半導体素子が接合された状態を表す断面図である。It is sectional drawing showing the state by which the power semiconductor element was joined to the ceramic substrate. セラミック基板に主端子が接合された状態を表している平面図である。It is a top view showing the state where the main terminal was joined to the ceramic substrate. セラミック基板がケースと固定されている状態を表す断面図である。It is sectional drawing showing the state by which the ceramic substrate is being fixed with the case. 実施の形態2によるパワーモジュールの概念断面図である。4 is a conceptual cross-sectional view of a power module according to Embodiment 2. FIG. 実施の形態2によるパワーモジュールの概念上面図である。6 is a conceptual top view of a power module according to Embodiment 2. FIG. 電力半導体素子に主端子が接合された状態を表す平面図である。It is a top view showing the state by which the main terminal was joined to the power semiconductor element. 実施の形態2によるパワーモジュールの別形態を示す概念上面図である。It is a conceptual top view which shows another form of the power module by Embodiment 2.

以下に本発明にかかるパワーモジュールの実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の既述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。図において、同一符号が付与されている構成要素は、同一の、または、相当する構成要素を表している。   Embodiments of a power module according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. In the figure, the components given the same reference numerals represent the same or corresponding components.

実施の形態1.
図1は実施の形態1によるパワーモジュール100を表す概念断面図である。IGBT(Insulated Gate Bipolar Transistor)1とダイオード2はAlN製のセラミック基板11の上に搭載されている。IGBT1はトランジスタの一種である。セラミック基板11の上面には銅製の回路導体層12aおよび回路導体層12bが形成されている。IGBT1は回路導体層12aにはんだダイボンドによって接合されている。ダイオード2は回路導体層12bにはんだダイボンドによって接合されている。パワーモジュール100は、通常、セラミック基板11の下面に形成されている回路導体層13を使って冷却器にはんだ付けされるが、熱伝導性の良いグリスを用いて冷却器に装着することもできる。
Embodiment 1 FIG.
FIG. 1 is a conceptual sectional view showing a power module 100 according to the first embodiment. An IGBT (Insulated Gate Bipolar Transistor) 1 and a diode 2 are mounted on a ceramic substrate 11 made of AlN. The IGBT 1 is a kind of transistor. A copper circuit conductor layer 12 a and a circuit conductor layer 12 b are formed on the upper surface of the ceramic substrate 11. The IGBT 1 is joined to the circuit conductor layer 12a by solder die bonding. The diode 2 is joined to the circuit conductor layer 12b by solder die bonding. The power module 100 is usually soldered to the cooler using the circuit conductor layer 13 formed on the lower surface of the ceramic substrate 11, but can also be attached to the cooler using grease with good thermal conductivity. .

セラミック基板11はPPS(Poly Phenylene Sulfide)樹脂製のケース5にシリコーン製の接着剤10を用いて固定されている。ケース5の内側にはダイレクトポッティング封止樹脂部材15が充填されている。ケース5とセラミック基板11との隙間を接着剤10で埋めることでダイレクトポッティング封止樹脂部材15がケース5から漏れることを防止している。ケース5の内部にはPPS樹脂製またはPS(Poly Styrene)樹脂製の橋渡し部材3が形成されている。PPS樹脂およびPS樹脂はともに絶縁物である。橋渡し部材3は大電流が流れる主端子6の上に固定されている。主端子6はIGBT1とダイオード2を接続している。主端子6は片方の端部がケース5にインサートモールドされている。信号端子7は、先端がダイレクトポッティング封止樹脂部材15から突出し、橋渡し部材3に固定されている。ワイヤ4は信号端子7とIGBT1を接続している。ネジ止め端子6aは主端子6の先端に形成されている。   The ceramic substrate 11 is fixed to a case 5 made of PPS (Poly Phenylene Sulfide) resin by using an adhesive 10 made of silicone. The inside of the case 5 is filled with a direct potting sealing resin member 15. The gap between the case 5 and the ceramic substrate 11 is filled with the adhesive 10 to prevent the direct potting sealing resin member 15 from leaking from the case 5. A bridging member 3 made of PPS resin or PS (Poly Styrene) resin is formed inside the case 5. Both the PPS resin and the PS resin are insulators. The bridging member 3 is fixed on the main terminal 6 through which a large current flows. The main terminal 6 connects the IGBT 1 and the diode 2. One end of the main terminal 6 is insert-molded in the case 5. The signal terminal 7 protrudes from the direct potting sealing resin member 15 and is fixed to the bridging member 3. The wire 4 connects the signal terminal 7 and the IGBT 1. The screw terminal 6 a is formed at the tip of the main terminal 6.

IGBT1とダイオード2を含む電力半導体素子は、珪素(Si)によって形成したものの他、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成したものも好適に使用することができる。ワイドバンドギャップ半導体としては、炭化珪素(SiC)、窒化ガリウム系材料またはダイヤモンドなどがある。ワイドバンドギャップ半導体を用いた場合、許容電流密度が高く、電力損失も低いため、電力半導体素子を用いた装置の小型化が可能となる。   As the power semiconductor element including the IGBT 1 and the diode 2, a power semiconductor element formed of a wide band gap semiconductor having a band gap larger than that of silicon can be suitably used in addition to that formed of silicon (Si). Examples of the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride material, and diamond. When a wide bandgap semiconductor is used, the allowable current density is high and the power loss is low, so that a device using a power semiconductor element can be downsized.

図2は実施の形態1によるパワーモジュール100を表す概念上面図である。主端子8(第1端子)はセラミック基板11の回路導体層12bに直接はんだ付けされている。主端子(第2端子)6はIGBT1のソース電極1aおよびダイオード2のアノード電極2aに直接はんだ付けされている。回路導体層12aはIGBT1のドレイン電極と接続されている。回路導体層12bはダイオード2のカソード電極と接続されている。ここでは、IGBT1は4個の制御電極1bを有している。IGBT1の制御電極1bは4個の信号端子(第3端子)7とアルミ製のワイヤ4で個々に接続されている。ネジ止め端子8aは主端子8の先端に形成されている。主端子8は、主端子6よりも長さが短く、幅が狭い。   FIG. 2 is a conceptual top view showing the power module 100 according to the first embodiment. The main terminal 8 (first terminal) is directly soldered to the circuit conductor layer 12 b of the ceramic substrate 11. The main terminal (second terminal) 6 is directly soldered to the source electrode 1 a of the IGBT 1 and the anode electrode 2 a of the diode 2. The circuit conductor layer 12a is connected to the drain electrode of the IGBT1. The circuit conductor layer 12 b is connected to the cathode electrode of the diode 2. Here, the IGBT 1 has four control electrodes 1b. The control electrode 1 b of the IGBT 1 is individually connected to four signal terminals (third terminals) 7 by aluminum wires 4. The screw terminal 8 a is formed at the tip of the main terminal 8. The main terminal 8 is shorter and narrower than the main terminal 6.

ダイレクトポッティング封止樹脂部材15はケース5の内側に注入されていて、内部の部品を封止している。ケース5の内部には橋渡し部材3が形成されている。信号端子7は、個々に橋渡し部材3に、インサートモールドなどの方法で、固定されている。ネジ止め端子6aおよびネジ止め端子8aはケース5の外周部に形成されている。ネジ止め端子6aは主端子6と一体化している。ネジ止め端子8aは主端子8と一体化している。ネジ止め端子6aとネジ止め端子8aを使って、パワーモジュール100を外部機器に接続する。信号端子7の幅は1.5mmとした。ネジ止め端子6aおよびネジ止め端子8aの幅は10mmとした。ケース5は、ダイオード2とIGBT1と主端子6と主端子8と信号端子7と橋渡し部材3を収容している。   The direct potting sealing resin member 15 is injected inside the case 5 and seals internal components. A bridging member 3 is formed inside the case 5. The signal terminals 7 are individually fixed to the bridging member 3 by a method such as insert molding. The screw terminal 6 a and the screw terminal 8 a are formed on the outer periphery of the case 5. The screw terminal 6 a is integrated with the main terminal 6. The screw terminal 8 a is integrated with the main terminal 8. The power module 100 is connected to an external device using the screw terminal 6a and the screw terminal 8a. The width of the signal terminal 7 was 1.5 mm. The width of the screw terminal 6a and the screw terminal 8a was 10 mm. The case 5 houses the diode 2, the IGBT 1, the main terminal 6, the main terminal 8, the signal terminal 7, and the bridging member 3.

次に、パワーモジュール100の製造方法を説明する。図3はセラミック基板11に電力半導体素子(IGBT1およびダイオード2)が接合された状態を表す平面図である。セラミック基板11の上側の第2主面には外周に余白部(第2余白部)11aを残して回路導体層12aおよび回路導体層12bが形成されている。IGBT1は上面にソース電極1a(またはドレイン電極)と制御電極1bが形成されている。ダイオード2は上面にアノード電極2a(またはカソード電極)が形成されている。セラミック基板11の上面に形成されている回路導体層12aおよび回路導体層12bは、連通しており、そのパターン厚さを0.4mmとした。セラミック基板11の大きさは40mm×25mmとし、厚さ0.635mmのものを用いた。IGBT1に形成されている4個の制御電極1bはゲート電極、温度センサー電極などを含む。ダイオード2の大きさは15mm×15mmとし、厚さ0.3mmのものを用いた。   Next, a method for manufacturing the power module 100 will be described. FIG. 3 is a plan view showing a state where power semiconductor elements (IGBT 1 and diode 2) are joined to the ceramic substrate 11. On the second main surface on the upper side of the ceramic substrate 11, a circuit conductor layer 12a and a circuit conductor layer 12b are formed leaving a blank portion (second blank portion) 11a on the outer periphery. The IGBT 1 has a source electrode 1a (or drain electrode) and a control electrode 1b formed on the upper surface. The diode 2 has an anode electrode 2a (or cathode electrode) formed on the upper surface. The circuit conductor layer 12a and the circuit conductor layer 12b formed on the upper surface of the ceramic substrate 11 communicate with each other, and the pattern thickness is set to 0.4 mm. The ceramic substrate 11 had a size of 40 mm × 25 mm and a thickness of 0.635 mm. The four control electrodes 1b formed on the IGBT 1 include a gate electrode, a temperature sensor electrode, and the like. The size of the diode 2 was 15 mm × 15 mm and the thickness was 0.3 mm.

図4はセラミック基板11に電力半導体素子(IGBT1およびダイオード2)が接合された状態を表す側面図である。セラミック基板11は片面にしか導体層が形成されていないとそりが大きくなるので、両面に導体層が形成されている。セラミック基板11の下側の第1主面には外周に余白部(第1余白部)11bを残して回路導体層13が形成されている。IGBT1は回路導体層12aにはんだダイボンドによって接合されている。ダイオード2は回路導体層12bにはんだダイボンドによって接合されている。   FIG. 4 is a side view showing a state in which power semiconductor elements (IGBT 1 and diode 2) are joined to the ceramic substrate 11. The ceramic substrate 11 has a large warp when a conductor layer is formed only on one side, and therefore a conductor layer is formed on both sides. A circuit conductor layer 13 is formed on the first main surface on the lower side of the ceramic substrate 11 leaving a blank portion (first blank portion) 11b on the outer periphery. The IGBT 1 is joined to the circuit conductor layer 12a by solder die bonding. The diode 2 is joined to the circuit conductor layer 12b by solder die bonding.

図5はセラミック基板11に主端子6と主端子8と接合した状態を表している。主端子6はIGBT1の主電極(ソース電極またはドレイン電極)およびダイオード2の主電極(アノード電極またはカソード電極)に直接はんだ付けする。主端子8はセラミック基板11の回路導体層12bに直接はんだ付けする。主端子6の先端にはネジ止め端子6aが形成されている。主端子8の先端にはネジ止め端子8aが形成されている。   FIG. 5 shows a state in which the main terminal 6 and the main terminal 8 are joined to the ceramic substrate 11. The main terminal 6 is directly soldered to the main electrode (source electrode or drain electrode) of the IGBT 1 and the main electrode (anode electrode or cathode electrode) of the diode 2. The main terminal 8 is directly soldered to the circuit conductor layer 12b of the ceramic substrate 11. A screw terminal 6 a is formed at the tip of the main terminal 6. A screw terminal 8 a is formed at the tip of the main terminal 8.

図6はセラミック基板11をケース5で囲んだ状態を表している。ケース5の幅と奥行きは48mm×28mmとし、高さは12mmとした。ケース5とセラミック基板11との隙間はシリコーン製の接着剤10で埋める。ケース5にはネジ止め端子6aおよびネジ止め端子8aを含む部分をインサートモールドする。主端子6の上には信号端子7がインサートモールドされている橋渡し部材3を溶着する。主端子6はケース5の中でセラミック基板11から2mm程度浮いている。主端子6はIGBT1とダイオード2にはんだ14で接合した。アルミ製のワイヤ4は直径0.15mmのものを使用した。ワイヤ4は信号端子7の上に配置されているため、ワイヤボンド時に超音波を容易に印加できる。   FIG. 6 shows a state in which the ceramic substrate 11 is surrounded by the case 5. Case 5 had a width and depth of 48 mm x 28 mm and a height of 12 mm. A gap between the case 5 and the ceramic substrate 11 is filled with an adhesive 10 made of silicone. The part including the screw terminal 6a and the screw terminal 8a is insert-molded in the case 5. The bridging member 3 in which the signal terminal 7 is insert-molded is welded onto the main terminal 6. The main terminal 6 floats about 2 mm from the ceramic substrate 11 in the case 5. The main terminal 6 was joined to the IGBT 1 and the diode 2 with solder 14. The aluminum wire 4 having a diameter of 0.15 mm was used. Since the wire 4 is disposed on the signal terminal 7, an ultrasonic wave can be easily applied at the time of wire bonding.

最後に、ケース5にダイレクトポッティング封止樹脂部材15を60℃に加熱した状態で流し込む。ダイレクトポッティング封止樹脂部材15には例えば菱電化成製のR-416を使用する。その後、加熱した状態で真空脱泡する(100℃,1.5時間)。さらに、昇温(140℃,1.5時間)して封止樹脂を硬化させると、ダイレクトポッティングが完了し、パワーモジュールが完成する。ケースの中央部には信号端子7が配置されている。信号端子7は、ダイレクトポッティング封止樹脂部材15の硬化収縮や温度サイクルによる剥離の影響を受けにくいので、断線にいたる寿命を長くすることが出来る。   Finally, the direct potting sealing resin member 15 is poured into the case 5 while being heated to 60 ° C. For the direct potting sealing resin member 15, for example, R-416 made by Ryoden Kasei is used. Thereafter, vacuum degassing is performed in a heated state (100 ° C., 1.5 hours). Furthermore, when the sealing resin is cured by raising the temperature (140 ° C., 1.5 hours), the direct potting is completed and the power module is completed. A signal terminal 7 is disposed at the center of the case. Since the signal terminal 7 is not easily affected by curing shrinkage of the direct potting sealing resin member 15 or peeling due to a temperature cycle, it is possible to prolong the life leading to disconnection.

ここではセラミック基板11の材料としてAlNを用いたが、アルミナやSiNなどのセラミック材料でも同様の効果が得られる。放熱性の必要性があまり高くない場合であれば、基板にガラスエポキシ基板などを用いることも可能である。ケース5の材料としてPPS樹脂を用いているが、LCP(液晶ポリマー)を用いても同様の効果が得られる。ここでは1対のダイオード2とIGBT1を内蔵している(1 in 1)でのモジュール構成を示しているが、ダイオードとIGBTを2対内蔵している(2 in 1)、6対内蔵している(6 in 1)であっても、主端子となる金属板上に信号端子を配置することで同様の効果が得られる。   Here, AlN is used as the material of the ceramic substrate 11, but the same effect can be obtained with a ceramic material such as alumina or SiN. If the necessity for heat dissipation is not so high, a glass epoxy substrate or the like can be used as the substrate. Although a PPS resin is used as the material of the case 5, the same effect can be obtained by using LCP (liquid crystal polymer). Here, the module configuration is shown in which one pair of diodes 2 and IGBTs 1 are built in (1 in 1), but two pairs of diodes and IGBTs are built in (2 in 1), and six pairs are built in. (6 in 1), the same effect can be obtained by arranging the signal terminal on the metal plate serving as the main terminal.

セラミック基板の代わりに、ベース板とセラミック基板の機能を併せ持つ金属基板を用いれば部品点数の削減が可能となり、軽量化や小型化が可能となる。ここでいう金属基板はアルミ板上に有機絶縁層と銅箔導体層を積層した物である。ここではアルミ製のワイヤボンドを用いているが、銅製ワイヤ、アルミ被覆銅ワイヤ、または金ワイヤを用いても同様の効果が得られる。また、主端子6にリボンボンドを用いたり、バスバーなどを用いても同様の効果が得られる。バスバーは金属板(IGBT1のソース電極およびダイオード2のアノード電極)に超音波接合する。バスバーの断面は細長い長方形をしているので放熱効果を持つ他、表面積がより大きいので表面電流が大きい高速システムでより有利となる。   If a metal substrate having both the functions of a base plate and a ceramic substrate is used instead of the ceramic substrate, the number of components can be reduced, and the weight and size can be reduced. Here, the metal substrate is a laminate in which an organic insulating layer and a copper foil conductor layer are laminated on an aluminum plate. Although aluminum wire bonds are used here, the same effect can be obtained by using copper wires, aluminum-coated copper wires, or gold wires. The same effect can be obtained by using a ribbon bond or a bus bar for the main terminal 6. The bus bar is ultrasonically bonded to a metal plate (the source electrode of the IGBT 1 and the anode electrode of the diode 2). Since the cross section of the bus bar is a long and narrow rectangle, it has a heat dissipation effect, and since the surface area is larger, it is more advantageous in a high speed system with a large surface current.

ダイレクトポッティング封止樹脂部材については、流し込んで常温硬化させる種類のものでも同様の効果が得られる。さらにゲル封止を行っても同様のパワーモジュールの形成が可能となる。また、電力半導体素子とセラミック基板の接続や、主端子と電力半導体素子の接続にはんだを用いたが、Agフィラーをエポキシ樹脂に分散させた導電性接着剤や、ナノ粒子を低温焼成させるAgナノパウダやCuナノパウダなどを用いても同様の効果が得られる。   About the direct potting sealing resin member, the same effect can be obtained even if it is of a type that is poured and cured at room temperature. Further, even if gel sealing is performed, the same power module can be formed. In addition, a solder is used to connect the power semiconductor element and the ceramic substrate, or between the main terminal and the power semiconductor element, but a conductive adhesive in which an Ag filler is dispersed in an epoxy resin, or an Ag nanopowder for firing nanoparticles at a low temperature. Similar effects can be obtained by using Cu nano powder or the like.

実施の形態2.
図7は実施の形態2によるパワーモジュール100の概念断面図である。IGBT1とダイオード2はAlN製のセラミック基板11の上に搭載されている。セラミック基板11の上面には銅製の回路導体層12aおよび回路導体層12bが形成されている。IGBT1は回路導体層12aにはんだダイボンドによって固定されている。ダイオード2は回路導体層12bにはんだダイボンドによって固定されている。セラミック基板11は片面にしか導体層が形成されていないとそりが大きいので、両面に導体層が形成されている。パワーモジュール100は、通常、セラミック基板11の下面に形成されている回路導体層13を使って冷却器にはんだ付けされるが、熱伝導性の良いグリスを用いて冷却器に装着することもできる。
Embodiment 2. FIG.
FIG. 7 is a conceptual cross-sectional view of the power module 100 according to the second embodiment. The IGBT 1 and the diode 2 are mounted on an AlN ceramic substrate 11. A copper circuit conductor layer 12 a and a circuit conductor layer 12 b are formed on the upper surface of the ceramic substrate 11. The IGBT 1 is fixed to the circuit conductor layer 12a by solder die bonding. The diode 2 is fixed to the circuit conductor layer 12b by solder die bonding. The ceramic substrate 11 has a large warp when the conductor layer is formed only on one side, and therefore the conductor layer is formed on both sides. The power module 100 is usually soldered to the cooler using the circuit conductor layer 13 formed on the lower surface of the ceramic substrate 11, but can also be attached to the cooler using grease with good thermal conductivity. .

PPS樹脂製のケース5の上部外周には厚さ0.2mmの薄肉部5aが形成されている。ケース5の内部には橋渡し部材(第1橋渡し部材)3と橋渡し部材(第2橋渡し部材)9が固定されている。橋渡し部材3はIGBT1とダイオード2との間の空間上部に配置されている。橋渡し部材9はセラミック基板11の上面に配置されている。主端子6は橋渡し部材9に、インサートモールドなどの方法で、固定されている。橋渡し部材3は主端子6よりも下側まで回り込んでいる。橋渡し部材3の樹脂が主端子6の下側まで回りこんでいるほうが信号端子7を固定しやすく強度が確保できる。溶接端子6bは主端子6の先端に形成されていて、ダイレクトポッティング封止樹脂部材15から突出している。ケース5は、ダイオード2とIGBT1と主端子6と主端子8と信号端子7と橋渡し部材3と橋渡し部材9を収容している。   A thin portion 5a having a thickness of 0.2 mm is formed on the upper outer periphery of the case 5 made of PPS resin. A bridging member (first bridging member) 3 and a bridging member (second bridging member) 9 are fixed inside the case 5. The bridging member 3 is disposed in the upper part of the space between the IGBT 1 and the diode 2. The bridging member 9 is disposed on the upper surface of the ceramic substrate 11. The main terminal 6 is fixed to the bridging member 9 by a method such as insert molding. The bridging member 3 wraps around below the main terminal 6. It is easier to fix the signal terminal 7 and the strength can be ensured when the resin of the bridging member 3 extends to the lower side of the main terminal 6. The welding terminal 6 b is formed at the tip of the main terminal 6 and protrudes from the direct potting sealing resin member 15. The case 5 accommodates the diode 2, IGBT 1, main terminal 6, main terminal 8, signal terminal 7, bridging member 3, and bridging member 9.

図8は実施の形態2によるパワーモジュール100を表す概念上面図である。主端子6はIGBT1のソース電極1aおよびダイオード2のアノード電極2aに直接はんだ付けされている。主端子8はセラミック基板11の回路導体層12bに直接はんだ付けされている。IGBT1のドレイン電極は回路導体層12aと接続されている。ダイオード2のカソード電極は回路導体層12bと接続されている。IGBT1の制御電極1bは信号端子7とアルミ製のワイヤ4で個々に接続されている。信号端子7は、橋渡し部材3にインサートモールドなどの方法で固定されている。溶接端子8bは主端子8の先端に形成されていて、主端子8と一体化している。   FIG. 8 is a conceptual top view showing the power module 100 according to the second embodiment. The main terminal 6 is directly soldered to the source electrode 1a of the IGBT 1 and the anode electrode 2a of the diode 2. The main terminal 8 is directly soldered to the circuit conductor layer 12 b of the ceramic substrate 11. The drain electrode of the IGBT 1 is connected to the circuit conductor layer 12a. The cathode electrode of the diode 2 is connected to the circuit conductor layer 12b. The control electrode 1 b of the IGBT 1 is individually connected to the signal terminal 7 by an aluminum wire 4. The signal terminal 7 is fixed to the bridging member 3 by a method such as insert molding. The welding terminal 8 b is formed at the tip of the main terminal 8 and is integrated with the main terminal 8.

ケース5の内側はダイレクトポッティング封止樹脂部材15で充填されている。ケース5の内部には橋渡し部材3の他に橋渡し部材9が形成されている。主端子8の溶接端子8bはダイレクトポッティング封止樹脂部材15から突出している。溶接端子6bは主端子6と一体化している。溶接端子6bおよび溶接端子8bは橋渡し部材9にインサートモールドなどの方法で固定されている。溶接端子6bと溶接端子8bを使って、パワーモジュール100を外部機器に接続する。信号端子7の幅は1.5mmとした。溶接端子6bおよび溶接端子8bの幅は10mmとした。   The inside of the case 5 is filled with a direct potting sealing resin member 15. In addition to the bridging member 3, a bridging member 9 is formed inside the case 5. The welding terminal 8 b of the main terminal 8 protrudes from the direct potting sealing resin member 15. The welding terminal 6 b is integrated with the main terminal 6. The welding terminal 6b and the welding terminal 8b are fixed to the bridging member 9 by a method such as insert molding. The power module 100 is connected to an external device using the welding terminal 6b and the welding terminal 8b. The width of the signal terminal 7 was 1.5 mm. The width of the welding terminal 6b and the welding terminal 8b was 10 mm.

次に、パワーモジュール100の製造方法を説明する。図9は電力半導体素子(IGBT1およびダイオード2)が接合されたセラミック基板11に主端子6と主端子8が接合されている状態を表す平面図である。セラミック基板11の上面に形成されている回路導体層12aおよび回路導体層12bは、連通していて、そのパターンの厚さは0.4mmとし
た。セラミック基板11の大きさは40mm×25mmとし、厚さ0.635mmのものを用いた。IGBT1に形成されている4個の制御電極1bはゲート電極、温度センサー電極を含む。ダイオード2の大きさは15mm×15mmとし、厚さ0.3mmのものを用いた。IGBT1は回路導体層12aにはんだダイボンドによって接合した。ダイオード2は回路導体層12bにはんだダイボンドによって接合した。
Next, a method for manufacturing the power module 100 will be described. FIG. 9 is a plan view showing a state in which the main terminal 6 and the main terminal 8 are joined to the ceramic substrate 11 to which the power semiconductor elements (IGBT 1 and diode 2) are joined. The circuit conductor layer 12a and the circuit conductor layer 12b formed on the upper surface of the ceramic substrate 11 are in communication, and the thickness of the pattern is 0.4 mm. The ceramic substrate 11 had a size of 40 mm × 25 mm and a thickness of 0.635 mm. The four control electrodes 1b formed on the IGBT 1 include a gate electrode and a temperature sensor electrode. The size of the diode 2 was 15 mm × 15 mm and the thickness was 0.3 mm. IGBT1 was joined to the circuit conductor layer 12a by solder die bonding. The diode 2 was joined to the circuit conductor layer 12b by solder die bonding.

次いでセラミック基板11をケース5で囲む。ケース5の幅と奥行きは48mm×28mmとし、高さは12mmとした。ケース5とセラミック基板11との隙間はシリコーン製の接着剤10で埋める。信号端子7は主端子6の上に橋渡し部材3を介して固定する。主端子6はケース5の中でセラミック基板11から2mm程度浮いている。主端子6はIGBT1とダイオード2にはんだで接合する。アルミ製のワイヤ4は直径0.15mmのものを使用した。ワイヤ4は信号端子7の上に配置されているため、ワイヤボンド時に超音波を容易に印加できる。   Next, the ceramic substrate 11 is surrounded by the case 5. Case 5 had a width and depth of 48 mm x 28 mm and a height of 12 mm. A gap between the case 5 and the ceramic substrate 11 is filled with an adhesive 10 made of silicone. The signal terminal 7 is fixed on the main terminal 6 via the bridging member 3. The main terminal 6 floats about 2 mm from the ceramic substrate 11 in the case 5. The main terminal 6 is joined to the IGBT 1 and the diode 2 with solder. The aluminum wire 4 having a diameter of 0.15 mm was used. Since the wire 4 is disposed on the signal terminal 7, an ultrasonic wave can be easily applied at the time of wire bonding.

最後に、ケース5にダイレクトポッティング封止樹脂を60℃に加熱した状態で流し込む。ダイレクトポッティング封止樹脂には例えば菱電化成製のR-416を使用する。その後、加熱した状態で真空脱泡する(100℃,1.5時間)。さらに、昇温(140℃,1.5時間)して封止樹脂を硬化させると、封止が完了し、パワーモジュールが完成する。ケース5の中央部には信号端子7が配置されている。信号端子7は、ダイレクトポッティング封止樹脂部材15の硬化収縮や温度サイクルによる剥離の影響を受けにくいので、断線にいたる寿命を長くすることが出来る。   Finally, the direct potting sealing resin is poured into the case 5 while being heated to 60 ° C. For example, R-416 manufactured by Ryoden Kasei is used as the direct potting sealing resin. Thereafter, vacuum degassing is performed in a heated state (100 ° C., 1.5 hours). Further, when the sealing resin is cured by raising the temperature (140 ° C., 1.5 hours), the sealing is completed and the power module is completed. A signal terminal 7 is disposed at the center of the case 5. Since the signal terminal 7 is not easily affected by curing shrinkage of the direct potting sealing resin member 15 or peeling due to a temperature cycle, it is possible to prolong the life leading to disconnection.

ここではセラミック基板11の材料としてAlNを用いたが、アルミナやSiNなどのセラミック材料でも同様の効果が得られる。放熱性の必要性があまり高くない場合であれば、基板にガラスエポキシ基板などを用いることも可能である。ケース5の材料としてPPS樹脂を用いているが、LCP(液晶ポリマー)を用いても同様の効果が得られる。ここでは1対のダイオード2とIGBT1を内蔵している(1 in 1)でのモジュール構成を示しているが、ダイオードとIGBTを2対内蔵している(2 in 1)、6対内蔵している(6 in 1)であっても、主端子となる金属板上に信号端子を配置することで同様の効果が得られる。   Here, AlN is used as the material of the ceramic substrate 11, but the same effect can be obtained with a ceramic material such as alumina or SiN. If the necessity for heat dissipation is not so high, a glass epoxy substrate or the like can be used as the substrate. Although a PPS resin is used as the material of the case 5, the same effect can be obtained by using LCP (liquid crystal polymer). Here, the module configuration is shown in which one pair of diodes 2 and IGBTs 1 are built in (1 in 1), but two pairs of diodes and IGBTs are built in (2 in 1), and six pairs are built in. (6 in 1), the same effect can be obtained by arranging the signal terminal on the metal plate serving as the main terminal.

セラミック基板の代わりに、ベース板とセラミック基板の機能を併せ持つ金属基板を用いることで部品点数の削減が可能となり、軽量化や小型化が可能となる。ここでいう金属基板はアルミ板上に有機絶縁層と銅箔導体層を積層した物である。ここではアルミ製のワイヤボンドを用いたが、銅製ワイヤ、アルミ被覆銅ワイヤ、または金ワイヤを用いても同様の効果が得られる。また、主端子6にリボンボンドを用いたり、バスバーなどを用いても同様の効果が得られる。バスバーは金属板(IGBT1のソース電極1aおよびダイオード2のアノード電極2a)に超音波接合する。バスバーの断面は細長い長方形をしているので放熱効果を持つ他、表面積がより大きいので表面電流が大きい高速システムでより有利となる。   By using a metal substrate having both the functions of a base plate and a ceramic substrate instead of the ceramic substrate, the number of components can be reduced, and the weight and size can be reduced. Here, the metal substrate is a laminate in which an organic insulating layer and a copper foil conductor layer are laminated on an aluminum plate. Although aluminum wire bonds are used here, similar effects can be obtained by using copper wires, aluminum-coated copper wires, or gold wires. The same effect can be obtained by using a ribbon bond or a bus bar for the main terminal 6. The bus bar is ultrasonically bonded to a metal plate (the source electrode 1a of the IGBT 1 and the anode electrode 2a of the diode 2). Since the cross section of the bus bar is a long and narrow rectangle, it has a heat dissipation effect, and since the surface area is larger, it is more advantageous in a high speed system with a large surface current.

ダイレクトポッティング封止樹脂部材については、流し込んで常温硬化させる種類のものでも同様の効果が得られる。さらにゲル封止を行っても同様のパワーモジュールの形成が可能となる。また、電力半導体素子とセラミック基板の接続や、主端子と電力半導体素子の接続にはんだを用いたが、Agフィラーをエポキシ樹脂に分散させた導電性接着剤や、ナノ粒子を低温焼成させるAgナノパウダやCuナノパウダなどを用いても同様の効果が得られる。   About the direct potting sealing resin member, the same effect can be obtained even if it is of a type that is poured and cured at room temperature. Further, even if gel sealing is performed, the same power module can be formed. In addition, a solder is used to connect the power semiconductor element and the ceramic substrate, or between the main terminal and the power semiconductor element, but a conductive adhesive in which an Ag filler is dispersed in an epoxy resin, or an Ag nanopowder for firing nanoparticles at a low temperature. Similar effects can be obtained by using Cu nano powder or the like.

図10に示すように、ケース5の外周部と、主端子を支持する橋渡し部材9および信号端子を支持する橋渡し部材3を異なる部材で形成してもよい。例えば、ケース5の外周部は柔軟性に富んだPS樹脂とし、橋渡し部材3、9はPPS樹脂とすることでダイレクトポッティング封止樹脂部材の硬化収縮に対する追従性を増し、剥離をさらに抑制することが可能となる。   As shown in FIG. 10, the outer peripheral portion of the case 5, the bridging member 9 that supports the main terminal, and the bridging member 3 that supports the signal terminal may be formed of different members. For example, the outer peripheral portion of the case 5 is made of PS resin having a high flexibility, and the bridging members 3 and 9 are made of PPS resin, so that the followability to cure shrinkage of the direct potting sealing resin member is increased, and the peeling is further suppressed. Is possible.

電力半導体素子にSiCを用いた場合、電力半導体素子はその特徴を生かすべくSiの時と比較してより高温で動作させることになる。SiCデバイスを搭載するパワーモジュ
ールにおいては、電力半導体素子としてより高い信頼性が求められるため、高信頼のパワーモジュールを実現するという本発明のメリットはより効果的なものとなる。
When SiC is used for the power semiconductor element, the power semiconductor element is operated at a higher temperature than that of Si in order to take advantage of its characteristics. In a power module equipped with a SiC device, higher reliability is required as a power semiconductor element. Therefore, the merit of the present invention for realizing a highly reliable power module becomes more effective.

なお、本発明は、その発明の範囲内において、実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1 IGBT、1a ソース電極、1b 制御電極、2 ダイオード、2a アノード電極、3 橋渡し部材、4 ワイヤ、5 ケース、5a 薄肉部、6 主端子、6a ネジ止め端子、6b 溶接端子、7 信号端子、8 主端子、8a ネジ止め端子、8b 溶接端子、9 橋渡し部材、10 接着剤、11 セラミック基板、11a 余白部、11b 余白部、12a 回路導体層、12b 回路導体層、13 回路導体層、14 はんだ、15 ダイレクトポッティング封止樹脂部材、100 パワーモジュール 1 IGBT, 1a source electrode, 1b control electrode, 2 diode, 2a anode electrode, 3 bridging member, 4 wire, 5 case, 5a thin part, 6 main terminal, 6a screw terminal, 6b welding terminal, 7 signal terminal, 8 Main terminal, 8a Screw terminal, 8b Weld terminal, 9 Bridging member, 10 Adhesive, 11 Ceramic substrate, 11a Blank part, 11b Blank part, 12a Circuit conductor layer, 12b Circuit conductor layer, 13 Circuit conductor layer, 14 Solder, 15 Direct potting sealing resin member, 100 Power module

Claims (2)

第1主面には外周に第1余白部を残して第1導体層が形成されており、第2主面には外周に第2余白部を残して第2導体層が形成されているセラミック基板と、
前記セラミック基板の第2導体層に固定されているダイオードと、
制御電極を有し前記セラミック基板の第2導体層に固定されているトランジスタと、
前記セラミック基板の第2導体層に接続されている第1端子と、
前記ダイオードおよび前記トランジスタを接続する第2端子と、
前記トランジスタの制御電極とワイヤで接続されている第3端子と、
前記第2端子に固定され前記第3端子を保持する絶縁性の第1橋渡し部材と、
前記セラミック基板に固定され前記第1端子と前記第2端子を保持する絶縁性の第2橋渡し部材と、
前記セラミック基板に接着され、前記ダイオードと前記トランジスタと前記第1端子と前記第2端子と前記第3端子と前記第1橋渡し部材と前記第2橋渡し部材を収容するケースと、
前記ケースの内側に充填された封止樹脂部材と、を備え、
前記第1端子および前記第2端子は一部が前記第2橋渡し部材に固定され、前記第3端子は先端が前記封止樹脂部材から突出しているパワーモジュール。
A first conductor layer is formed on the first main surface leaving a first margin on the outer periphery, and a second conductor layer is formed on the second main surface leaving a second margin on the outer periphery. A substrate,
A diode fixed to the second conductor layer of the ceramic substrate;
A transistor having a control electrode and fixed to the second conductor layer of the ceramic substrate;
A first terminal connected to the second conductor layer of the ceramic substrate;
A second terminal connecting the diode and the transistor;
A third terminal connected to the control electrode of the transistor by a wire;
An insulating first bridging member fixed to the second terminal and holding the third terminal;
An insulating second bridging member fixed to the ceramic substrate and holding the first terminal and the second terminal;
A case that is bonded to the ceramic substrate and accommodates the diode, the transistor, the first terminal, the second terminal, the third terminal, the first bridging member, and the second bridging member;
A sealing resin member filled inside the case,
A part of the first terminal and the second terminal is fixed to the second bridging member, and a tip of the third terminal protrudes from the sealing resin member.
前記第1橋渡し部材および前記第2橋渡し部材は、前記ケースとは異なる樹脂からなることを特徴とする請求項1に記載のパワーモジュール。 The power module according to claim 1, wherein the first bridging member and the second bridging member are made of a resin different from the case.
JP2014005583A 2014-01-16 2014-01-16 Power module Active JP6124810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014005583A JP6124810B2 (en) 2014-01-16 2014-01-16 Power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014005583A JP6124810B2 (en) 2014-01-16 2014-01-16 Power module

Publications (2)

Publication Number Publication Date
JP2015133462A JP2015133462A (en) 2015-07-23
JP6124810B2 true JP6124810B2 (en) 2017-05-10

Family

ID=53900444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014005583A Active JP6124810B2 (en) 2014-01-16 2014-01-16 Power module

Country Status (1)

Country Link
JP (1) JP6124810B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109196641B (en) * 2016-06-03 2021-10-29 三菱电机株式会社 Semiconductor device module
US10212838B2 (en) * 2017-01-13 2019-02-19 Cree Fayetteville, Inc. High power multilayer module having low inductance and fast switching for paralleling power devices
JP6833986B2 (en) * 2017-05-11 2021-02-24 三菱電機株式会社 Power modules, power converters, and how to manufacture power modules
JP2019197842A (en) * 2018-05-11 2019-11-14 三菱電機株式会社 Power module, electric power conversion system, and method of manufacturing power module
JP7070373B2 (en) * 2018-11-28 2022-05-18 三菱電機株式会社 Manufacturing method of semiconductor device, semiconductor device, power conversion device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4064741B2 (en) * 2002-06-25 2008-03-19 株式会社日立製作所 Semiconductor device
JP5241177B2 (en) * 2007-09-05 2013-07-17 株式会社オクテック Semiconductor device and manufacturing method of semiconductor device
JP5202366B2 (en) * 2009-01-30 2013-06-05 本田技研工業株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2015133462A (en) 2015-07-23

Similar Documents

Publication Publication Date Title
JP5656907B2 (en) Power module
US10559538B2 (en) Power module
JP6120704B2 (en) Semiconductor device
JP2016018866A (en) Power module
JP2013016629A (en) Semiconductor module
US11776867B2 (en) Chip package
JP6124810B2 (en) Power module
WO2014097798A1 (en) Semiconductor device
JP2015220382A (en) Power module
JPWO2015029186A1 (en) Semiconductor module, semiconductor device, and automobile
US20200381370A1 (en) Power module having at least one power semiconductor
JP6057927B2 (en) Semiconductor device
JP2019067886A (en) Semiconductor device
US11251112B2 (en) Dual side cooling power module and manufacturing method of the same
JP2015046476A (en) Power semiconductor device and method of manufacturing the same
JP2016134540A (en) Power semiconductor device
JP6504962B2 (en) Power semiconductor device
JP6248803B2 (en) Power semiconductor module
JP2015220295A (en) Power module and manufacturing method of the same
JP2012209470A (en) Semiconductor device, semiconductor device module, and manufacturing method of the semiconductor device
JP7131436B2 (en) Semiconductor device and its manufacturing method
JPWO2020105556A1 (en) Semiconductor device, power conversion device and manufacturing method of semiconductor device
JP2015023226A (en) Wide gap semiconductor device
JP2013254810A (en) Metal substrate with feedthrough terminal and surface-mounted device using the same
JP6157320B2 (en) Power semiconductor device, power semiconductor module, and method of manufacturing power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151023

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160822

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160830

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161003

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20161206

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170113

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170307

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170404

R151 Written notification of patent or utility model registration

Ref document number: 6124810

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250