JPH04199663A - Pad grid array package - Google Patents

Pad grid array package

Info

Publication number
JPH04199663A
JPH04199663A JP33135690A JP33135690A JPH04199663A JP H04199663 A JPH04199663 A JP H04199663A JP 33135690 A JP33135690 A JP 33135690A JP 33135690 A JP33135690 A JP 33135690A JP H04199663 A JPH04199663 A JP H04199663A
Authority
JP
Japan
Prior art keywords
heat sink
package
recess
semiconductor chip
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33135690A
Other languages
Japanese (ja)
Inventor
Masayuki Kobayashi
Kazunari Imai
Takayuki Nagasaki
Original Assignee
Shinko Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co Ltd filed Critical Shinko Electric Ind Co Ltd
Priority to JP33135690A priority Critical patent/JPH04199663A/en
Publication of JPH04199663A publication Critical patent/JPH04199663A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To protect a package against cracks at mounting by a method wherein an empty space nearly as large as a pattern surface is provided to the rear side of a conductor pattern layer connected to a semiconductor chip, and a recess is provided to the pressing surface of a package main body.
CONSTITUTION: A heat sink 14 joined to a semiconductor chip 16 is provided to all the surface of a package main body 10, and a gap 30 is provided between the rear of a conductor pattern layer 24 and the heat sink 14. Therefore, a recess 32 is provided to the rear of the conductor pattern layer 24, the protrusion 14a of the heat sink 14 is housed in the recess 32, and the semiconductor chip 16 is joined to the protrusion 14a and supported. When the heat sink 14 is pressed down at the mounting of a package main body 10, a pressure acts on a pad 12 through the intermediary of the package main body 10, and the pad 12 is uniformly pressed down. By this setup, a package can be properly mounted as protected against cracks.
COPYRIGHT: (C)1992,JPO&Japio
JP33135690A 1990-11-29 1990-11-29 Pad grid array package Pending JPH04199663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33135690A JPH04199663A (en) 1990-11-29 1990-11-29 Pad grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33135690A JPH04199663A (en) 1990-11-29 1990-11-29 Pad grid array package

Publications (1)

Publication Number Publication Date
JPH04199663A true JPH04199663A (en) 1992-07-20

Family

ID=18242768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33135690A Pending JPH04199663A (en) 1990-11-29 1990-11-29 Pad grid array package

Country Status (1)

Country Link
JP (1) JPH04199663A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0634793A1 (en) * 1993-06-17 1995-01-18 Sun Microsystems, Inc. A low cost, thermally efficient, and surface mountable semiconductor package for a high applied power VLSI die
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0634793A1 (en) * 1993-06-17 1995-01-18 Sun Microsystems, Inc. A low cost, thermally efficient, and surface mountable semiconductor package for a high applied power VLSI die
JP2001110941A (en) * 1999-10-06 2001-04-20 Meito Chin Semiconductor device

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