JPH0226058A - Heat sink for hybrid integrated circuit - Google Patents
Heat sink for hybrid integrated circuitInfo
- Publication number
- JPH0226058A JPH0226058A JP63175039A JP17503988A JPH0226058A JP H0226058 A JPH0226058 A JP H0226058A JP 63175039 A JP63175039 A JP 63175039A JP 17503988 A JP17503988 A JP 17503988A JP H0226058 A JPH0226058 A JP H0226058A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- heat sink
- insulating plate
- recess
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 abstract description 37
- 230000008646 thermal stress Effects 0.000 abstract description 12
- 230000035882 stress Effects 0.000 abstract description 5
- 238000010008 shearing Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000002736 metal compounds Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- -1 N1aSn is generated Chemical class 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混成集積回路用ヒートシンクと半導体素子用
絶縁板との接続方法に係り、特にはんだ接続部への熱ス
トレスを緩和するのに好適な混成集積回路用ヒートシン
クに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of connecting a heat sink for a hybrid integrated circuit and an insulating plate for a semiconductor element, and is particularly suitable for alleviating thermal stress on solder joints. This invention relates to a heat sink for a hybrid integrated circuit.
従来の混成集積回路用ヒートシンク（以下ヒートシンク
と略す）は、特願昭５４−２５５８７号に記載のように
、半導体素子用絶縁板（以下絶縁板と略す）はんだ接続
部のヒートシンク形状が平担となっていた。As described in Japanese Patent Application No. 54-25587, conventional heat sinks for hybrid integrated circuits (hereinafter referred to as heat sinks) have flat heat sink shapes at the solder joints of insulating plates for semiconductor elements (hereinafter referred to as insulating plates). It had become.
一般にヒートシンクは、半導体素子の自己発熱を効率良
く外部へ放熱する必要があり、特に半導体素子は熱に弱
いため非常に重要なことである。In general, a heat sink is required to efficiently radiate the self-heated heat of a semiconductor element to the outside, and this is particularly important because semiconductor elements are sensitive to heat.
通常、ヒートシンクと絶縁板との接続は、ろう材などに
よって接続固定されるが、半導体素子や絶縁板などの自
重によりはんだのフィレット形状をコントロール出来な
く、そのため、絶縁板とはんだとの界面に応力が集中し
、繰り返し熱ストレスにより、接続界面を起点にクラッ
クが生じ半導体素子発熱の熱伝導に大きな悪影響を与え
ている。Normally, the connection between a heat sink and an insulating plate is fixed using a brazing material or the like, but the shape of the solder fillet cannot be controlled due to the weight of the semiconductor element or insulating plate, and as a result, stress is applied to the interface between the insulating plate and the solder. is concentrated and repeated thermal stress causes cracks to occur starting from the connection interface, which has a large negative impact on the heat conduction of heat generated by the semiconductor element.
更に、前記半導体素子や絶縁板などの自重により、はん
だ厚みを均一に、且つ厚く出来ない問題があった。Furthermore, there is a problem in that it is not possible to make the solder thickness uniform and thick due to the weight of the semiconductor element and the insulating plate.
本発明の目的は、繰り返し熱ストレスによるはんだ接続
部の接続寿命を延ばすため、ヒートシンクに凹部を設け
、更に凹部と同一面内に凸部を設け、絶縁板とはんだ界
面に応力集中しないフィレット形状にコントロールする
と同時に、はんだ厚みを均一に、且つ厚く確保出来るヒ
ートシンクを提供することにある。The purpose of the present invention is to provide a heat sink with a concave part and a convex part in the same plane as the concave part, in order to extend the connection life of solder joints due to repeated thermal stress, so that the heat sink has a fillet shape that does not concentrate stress at the interface between the insulating plate and the solder. To provide a heat sink that can control and at the same time ensure a uniform and thick solder thickness.
上記目的は、絶縁板をはんだ接続するヒートシンク面に
凹部を設け、更に凹部内の同一面に凸起を設ける事によ
って、はんだ接続部の耐熱疲労性が向上する。従って、
半導体素子が自己発熱した熱量を効率良くヒートシンク
へ熱伝導する事が達成できる。The above object is to improve the thermal fatigue resistance of the solder joint by providing a recess on the heat sink surface to which the insulating plate is soldered and further providing a protrusion on the same surface within the recess. Therefore,
It is possible to efficiently conduct heat generated by the semiconductor element to the heat sink.
本発明によるヒートシンクは、絶縁板をはんだ接続する
場所に凹部を設け、更に凹部内の同一面に複数個の凸部
を設けることによって、絶縁板とヒートシンク間のはん
だ形状をコントロールし、絶縁板とはんだ間の応力集中
を防止し、且つ熱応力が低減する。その結果、繰り返し
熱応力によって生ずる剪断ひずみを、はんだ接続中央付
近に傾り、その熱応力が軽減するため、はんだ接続部の
耐熱疲労性が向上する。In the heat sink according to the present invention, a recess is provided at the location where the insulating plate is soldered, and a plurality of protrusions are provided on the same surface within the recess to control the shape of the solder between the insulating plate and the heat sink. This prevents stress concentration between solders and reduces thermal stress. As a result, the shear strain caused by repeated thermal stress is tilted toward the center of the solder connection, reducing the thermal stress and improving the thermal fatigue resistance of the solder connection.
本発明の一実施例を第１図によって説明する。 An embodiment of the present invention will be described with reference to FIG.
ヒートシンク１にセラミック基板２と、トランジスタチ
ップ３がマウントされており、前記セラミック基板には
、厚膜回路が形成されており、ボンディング用パッド４
、半導体チップ５、およびチップコンデンサ６などの電
子部品がはんだ７で接続固定され電子回路を構成する。A ceramic substrate 2 and a transistor chip 3 are mounted on a heat sink 1, a thick film circuit is formed on the ceramic substrate, and a bonding pad 4 is mounted on the ceramic substrate.
, a semiconductor chip 5, and a chip capacitor 6 are connected and fixed with solder 7 to form an electronic circuit.
一方、トランジスタ部は、トランジスタチップ３、モリ
ブデン板８、絶縁基板９と積み重ね、前記絶縁基板８の
底面に、凹部１ａを設け、更に凹部内の同一面に例えば
、４ケ所の凸部１ｂを設けたヒートシンク１に各々をは
んだ１ｏを用いて接続固定しＡＱワイヤ１１を用いてト
ランジスタチップ電極３ａとパッド４を電気的に配線し
混成集積回路を構成している。On the other hand, the transistor part is stacked with a transistor chip 3, a molybdenum plate 8, and an insulating substrate 9, and a recess 1a is provided on the bottom surface of the insulating substrate 8, and further, for example, four protrusions 1b are provided on the same surface within the recess. Each is connected and fixed to a heat sink 1 using solder 1o, and transistor chip electrodes 3a and pads 4 are electrically wired using AQ wires 11 to form a hybrid integrated circuit.
このような構造において、絶縁板９はトランジスタチッ
プ３とヒートシンク１との電気的絶縁を行なうと同時に
、トランジスタチップ３で発熱した熱を速やかにヒート
シンク１へ伝熱する機能を有する。ここで、１２はセラ
ミック基板２をヒートシンク１に接着固定するための接
着剤１２である。In such a structure, the insulating plate 9 has the function of electrically insulating the transistor chip 3 and the heat sink 1, and at the same time, quickly transmitting the heat generated by the transistor chip 3 to the heat sink 1. Here, 12 is an adhesive 12 for adhesively fixing the ceramic substrate 2 to the heat sink 1.
第２図に本実施例による、はんだ厚みに対する絶縁板９
とヒートシンク１間のはんだ１０の耐熱疲労性を示す。FIG. 2 shows an insulating plate 9 according to the solder thickness according to this embodiment.
The thermal fatigue resistance of the solder 10 between the heat sink 1 and the heat sink 1 is shown.
絶縁板９とヒートシンク１の線膨張差は、約１０ ｘ
１０−６／’Ｃあるため使用時の温度変化によって、は
んだ１０に繰り返し熱応力が発生する。はんだ１０の接
続寿命予測は、一般にＣｏｆｆｉｎ−Ｍａｎｓｏｎの式
を拡張したもので予測でき本実施例では理論式に従い、
はんだ厚みを厚くして熱応力の低減を図ったものである
。The difference in linear expansion between the insulating plate 9 and the heat sink 1 is approximately 10 x
Since the temperature is 10-6/'C, thermal stress is repeatedly generated in the solder 10 due to temperature changes during use. The connection life of the solder 10 can generally be predicted by extending the Coffin-Manson equation, and in this example, according to the theoretical equation,
The solder thickness is increased to reduce thermal stress.
第２図に示すように、はんだが厚くなる程、耐熱疲労性
が向上する。しかし、実際には、はんだ厚みが増加する
ことにより、はんだ自身の熱抵抗。As shown in FIG. 2, the thicker the solder, the better the thermal fatigue resistance. However, in reality, by increasing the solder thickness, the thermal resistance of the solder itself increases.
更には、ボイド発生傾向にあるため、熱抵抗が増加する
ため、本実施例でははんだ厚みを０．２〜０．３ｍｍ程
度に管理しである。Furthermore, since there is a tendency for voids to occur, the thermal resistance increases, so in this embodiment, the solder thickness is controlled to be about 0.2 to 0.3 mm.
一方、はんだ接続メカニズムは、母材とはんだ中のＳｎ
とが相互拡散することであり、例えば、前記絶縁板９の
表面にＮｉをメタライズした場合はＮ１ａＳｎ など
の金属化合物が生成し、これによって接続される。On the other hand, the solder connection mechanism is based on Sn in the base material and solder.
For example, when the surface of the insulating plate 9 is metallized with Ni, a metal compound such as N1aSn is generated, thereby establishing the connection.
ところが、この金属化合物は大変硬く、ＮｉやＳｎに比
べて２〜３０倍の硬度となる。従って、大変脆い。更に
、線膨張差も前記ヒートシンク１側に比べ絶縁板９の方
が約２倍あるため、使用時の温度変化によって生じた熱
応力が、金属化合物の界面に集中する。以上の結果、は
んだ厚みを厚くしても前記絶縁板９界面に沿ってき裂が
進展し、接続寿命を低下させる。However, this metal compound is extremely hard, and is 2 to 30 times harder than Ni or Sn. Therefore, it is very fragile. Furthermore, since the linear expansion difference is approximately twice as large on the insulating plate 9 as on the heat sink 1 side, thermal stress caused by temperature changes during use is concentrated at the interface of the metal compound. As a result, even if the solder thickness is increased, cracks will grow along the interface of the insulating plate 9, reducing the connection life.
しかし、本実施例のように、前記絶縁板９の底面に１例
えば絶縁板９の寸法より０．２〜２ 、 ＯＩｎｍ大き
い凹部１ａをヒートシンク１に設ければ、はんだヒイレ
ットが制御出来、結果的には絶縁板９界面付近への応力
集中を分散する事が出来る。従って、寿命予測式とほぼ
一致する結果が得られ、はんだ接合部の大幅な長寿命化
が達成できる。However, as in this embodiment, if the heat sink 1 is provided with a concave portion 1a on the bottom surface of the insulating plate 9, for example, 0.2 to 2 OInm larger than the dimension of the insulating plate 9, the solder heel can be controlled. In this way, stress concentration near the interface of the insulating plate 9 can be dispersed. Therefore, a result that almost matches the life prediction formula can be obtained, and a significantly longer life of the soldered joint can be achieved.
本発明によれば、従来より使用するヒートシンクのはん
だ接続面に凹部を設け、更に凹部内の同一面に複数個の
凸部を設けることで、はんだ接続部の接続寿命が向上す
る。According to the present invention, by providing a concave portion on the solder connection surface of a conventionally used heat sink and further providing a plurality of convex portions on the same surface within the concave portion, the connection life of the solder connection portion is improved.
一方、ヒートシンクの凸凹形成は、ヒートシンクプレス
加工時に同時に形成でき、更にはんだ接続部のはんだ体
積も、従来より使用するはんだシートの厚みを変えるこ
とで可能である。On the other hand, the unevenness of the heat sink can be formed at the same time as the heat sink is pressed, and the solder volume of the solder joint can also be changed by changing the thickness of the solder sheet used in the past.
従って、コストアップの必要も殆どなく耐熱疲労性に優
れたトランジスタ実装構造を提供し得る効果がある。Therefore, there is an effect that it is possible to provide a transistor mounting structure with excellent thermal fatigue resistance without requiring almost any increase in cost.
第１図は本発明実施例の断面構造図、第２図ははんだ厚
みと耐熱疲労性の特性図である。FIG. 1 is a cross-sectional structural diagram of an example of the present invention, and FIG. 2 is a characteristic diagram of solder thickness and thermal fatigue resistance.
Claims (1)
ンクとを電気的に絶縁するため用いる半導体用絶縁板と
の接続において、前記半導体素子を接続固定する半導体
用絶縁板が、該絶縁板寸法より０．２〜２ｍｍ大きい凹
部を設けたヒートシンクに接続されたことを特徴とする
混成集積回路用ヒートシンク。 ２、特許請求の範囲第１項において、混成厚膜集積回路
用ヒートシンクの凹部と同一面内に複数個の凸部を形成
したことを特徴とする混成集積回路用ヒートシンク。[Scope of Claims] 1. An insulating plate for a semiconductor that connects and fixes a semiconductor element in connection with an insulating plate for a semiconductor used for electrically insulating an electrode of a semiconductor element and a heat sink for a hybrid thick film integrated circuit. is connected to a heat sink provided with a recess 0.2 to 2 mm larger than the dimension of the insulating plate. 2. A heat sink for a hybrid integrated circuit according to claim 1, characterized in that a plurality of convex portions are formed in the same plane as the recessed portion of the heat sink for a hybrid thick film integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63175039A JPH0226058A (en) | 1988-07-15 | 1988-07-15 | Heat sink for hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63175039A JPH0226058A (en) | 1988-07-15 | 1988-07-15 | Heat sink for hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226058A true JPH0226058A (en) | 1990-01-29 |
Family
ID=15989148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63175039A Pending JPH0226058A (en) | 1988-07-15 | 1988-07-15 | Heat sink for hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226058A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04167454A (en) * | 1990-10-31 | 1992-06-15 | Hitachi Ltd | Semiconductor device, its manufacturing, and ignition device for internal combustion engine |
| JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
| WO2013132644A1 (en) * | 2012-03-09 | 2013-09-12 | 三菱電機株式会社 | Semiconductor module |
| JP2015173299A (en) * | 2015-07-06 | 2015-10-01 | 三菱電機株式会社 | semiconductor module |
-
1988
- 1988-07-15 JP JP63175039A patent/JPH0226058A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04167454A (en) * | 1990-10-31 | 1992-06-15 | Hitachi Ltd | Semiconductor device, its manufacturing, and ignition device for internal combustion engine |
| JPWO2008078788A1 (en) * | 2006-12-26 | 2010-04-30 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
| JP5202333B2 (en) * | 2006-12-26 | 2013-06-05 | 京セラ株式会社 | Heat dissipation board and electronic device using the same |
| WO2013132644A1 (en) * | 2012-03-09 | 2013-09-12 | 三菱電機株式会社 | Semiconductor module |
| CN104160502A (en) * | 2012-03-09 | 2014-11-19 | 三菱电机株式会社 | Semiconductor module |
| US9443784B2 (en) | 2012-03-09 | 2016-09-13 | Mitsubishi Electric Corporation | Semiconductor module including plate-shaped insulating members having different thickness |
| JP2015173299A (en) * | 2015-07-06 | 2015-10-01 | 三菱電機株式会社 | semiconductor module |
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