JP2023028804A - Semiconductor device - Google Patents

Abstract

To prevent occurrence of voids in a solder that bonds a plate-shaped electrode and a disc, enhance strength against mechanical stress from the outside and improve reliability, in a semiconductor device having a configuration where a semiconductor package in which a plurality of semiconductor chips is set to the plate-shaped electrode to be sealed with a resin is bonded to the disc.SOLUTION: A semiconductor device includes two or more semiconductor chips and a plate-shaped electrode to which the two or more semiconductor chips are electrically connected via a bonding material. In the semiconductor device, the two or more semiconductor chips and the plate-shaped electrode are sealed with a resin, the plate-shaped electrode is arranged to be partially exposed outside the resin, and a non-through groove is provided on a face of the plate-shaped electrode where the two or more semiconductor chips are connected. The non-through groove is provided in a position other than a portion covered by the two or more semiconductor chips, and a protrusion is provided in a position on the back of the face of the plate-shaped electrode, the position corresponding to the non-through groove.SELECTED DRAWING: Figure 3

Description

The present invention relates to semiconductor devices.

2. Description of the Related Art A semiconductor device is known that has a configuration in which a plurality of semiconductor chips are soldered to an electrode formed of a single metal plate or the like.

Patent Literature 1 discloses a rectifying element in which a Zener diode chip is arranged at a position adjacent to a MOSFET chip on a pedestal of a base electrode (FIG. 11). The Zener diode is for having a function of surge absorption. In addition, the MOSFET chip and Zener diode, along with the control circuit chip and capacitor, are joined to the pedestal and the whole is sealed with resin.

Patent Document 2 discloses a transistor circuit chip having a switching element such as a MOSFET, a control circuit chip for controlling the switching element, a drain frame (first internal electrode), and a source frame (second internal electrode). An electronic circuit body integrally covered with a first resin including the A covered rectifying device is disclosed.

Patent Document 3 discloses a semiconductor device in which two semiconductor elements are bonded to a metal plate via solder, and the solder spreads around the outer periphery of the region of the metal plate where the solder is placed. It is disclosed that an annular groove is provided to prevent this.

In Patent Document 4, in a semiconductor device bonding structure in which a lead frame is soldered to a copper circuit pattern of an insulating substrate, the lead frame is soldered across the left and right copper circuit patterns formed on the upper surface of the insulating substrate. is disclosed. Here, on the solder joint surfaces (flat electrode surfaces) at both ends of the lead frame, one or a plurality of projecting protrusions having a protrusion height corresponding to the thickness of the solder layer are dispersedly formed. Then, the lead frame and the copper circuit pattern are soldered together in a state in which the lead frame is placed in contact with the solder joint surface of the copper circuit pattern. Patent Document 4 also discloses a lead frame soldered to an upper surface electrode of a semiconductor chip, in which protrusions are formed on one electrode surface of the lead frame.

JP 2015-116053 A JP 2017-98276 A Japanese Patent Application Laid-Open No. 2007-103909 JP-A-2005-72098

In the semiconductor device disclosed in Patent Document 3, the provision of the grooves in the metal plate partially thins the metal plate, which may reduce the strength of the metal plate. In this case, in order to secure the strength of the metal plate, it is necessary to increase the thickness of the metal plate as a whole.

In the semiconductor device disclosed in Patent Document 4, the electrode surface portion of the lead frame is relatively thick. Moreover, Patent Document 4 does not disclose a configuration in which other parts are installed on the upper surface of the lead frame.

An object of the present invention is to provide a semiconductor device having a structure in which a plurality of semiconductor chips are mounted on a plate-like electrode and a resin-sealed semiconductor package is joined to a disk, and voids in the solder joining the plate-like electrode and the disk are eliminated. The object is to prevent the occurrence of , increase strength against mechanical stress from the outside, and improve reliability.

The present invention provides a semiconductor device having two or more semiconductor chips and a plate-like electrode in which the two or more semiconductor chips are electrically connected via a bonding material. The plate-shaped electrode is sealed with resin, and the plate-shaped electrode is arranged so that a part thereof is exposed to the outside of the resin. is provided with a non-through groove, the non-through groove is provided at a position other than the portion covered with the two or more semiconductor chips, and corresponds to the non-through groove on the back surface of the surface of the plate-shaped electrode A protrusion is provided at the position.

According to the present invention, in a semiconductor device having a configuration in which a semiconductor package in which a plurality of semiconductor chips are mounted on a plate-shaped electrode and sealed with resin is joined to a disk, voids in the solder that joins the plate-shaped electrode and the disk are eliminated. can be prevented from occurring, the strength against external mechanical stress can be increased, and the reliability can be improved.

1 is a cross-sectional view showing a schematic configuration of a semiconductor module of an example; FIG. FIG. 3 is a top view showing a state of the semiconductor package according to the example before being sealed with resin; FIG. 3 is a cross-sectional view of the semiconductor package taken along line AA of FIG. 2 after being sealed with resin; 4 is a cross-sectional view showing a state in which the semiconductor package 4 of FIG. 3 is joined to a disk; FIG. 3 is a cross-sectional view showing a problem of the semiconductor package of Comparative Example 1; FIG. FIG. 10 is a cross-sectional view showing a problem of the semiconductor package of Comparative Example 2; 7 is a cross-sectional view showing a state in which the semiconductor package of FIG. 6 is connected to a disk; FIG. FIG. 10 is a cross-sectional view showing a modification of the lead frame;

TECHNICAL FIELD The present disclosure relates to a semiconductor device, and more particularly, to a technique for improving the reliability of soldered joints of a semiconductor module having external electrodes and a structure sealed with resin.

An embodiment will be described below with reference to the drawings. In addition, in each drawing, the same configurations are denoted by the same reference numerals, and detailed descriptions of overlapping portions are omitted.

FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor module. Although the semiconductor module may actually be installed in a direction different from the direction shown in this drawing, in the following description, the upper side in the drawing is defined as the vertically upward direction.

In the semiconductor module, a lead 1 is connected to the upper surface of a semiconductor package 4, and a disk 5 is connected to the lower surface thereof using solder 3, respectively. The semiconductor package 4 is covered with the sealing resin 2 together with these connection portions.

As materials for the lead 1 and the disk 5, it is desirable to use copper or a copper alloy, which has excellent electrical and thermal conductivity. In particular, the disc 5 is preferably made of a high-strength material such as a copper alloy containing zirconium, because the disc 5 receives a tightening force and a pressing force when it is press-fitted into a heat radiating fin or the like.

The thickness of the disc 5 is typically 3-4 mm.

Next, the structure of the semiconductor package will be described with reference to FIGS. 2 and 3. FIG.

FIG. 2 is a top view showing a state of the semiconductor package according to the present embodiment before being sealed with resin.

The semiconductor package shown in this figure includes source leads 6a and 6b, a diode chip 7, a MOSFET chip 8, a control IC chip 9, a capacitor 10, and lead frames 11 and 12. FIG. Here, MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor, and means a metal oxide film semiconductor field effect transistor. Also, IC is an abbreviation for Integrated Circuit and means an integrated circuit.

The diode chip 7 and MOSFET chip 8 are mounted on the top surface of the lead frame 11 . A non-penetrating groove portion 15 (non-penetrating groove) is provided on the upper surface of the lead frame 11 . In this figure, when the upper surface of the lead frame 11 is viewed from above, the diode chip 7 and the MOSFET chip 8 are substantially rectangular and arranged side by side. The groove 15 is arranged between the diode chip 7 and the MOSFET chip 8 . In other words, the groove portion 15 (non-through groove) is provided at a position other than the portion covered with the diode chip 7, MOSFET chip 8, etc. (semiconductor chip).

A control IC chip 9 and a capacitor 10 are installed on the upper surface of the lead frame 12 . A control IC chip 9 controls the MOSFET chip 8 . A capacitor 10 supplies power to the MOSFET chip 8 and the control IC chip 9 . Source lead 6 a is joined to diode chip 7 . The source lead 6b is bonded to the MOSFET chip 8. FIG.

Both the diode chip 7 and the MOSFET chip 8 are a kind of "semiconductor chip". Also, although the diode chip 7 and the MOSFET chip 8 are used in this embodiment, other semiconductor chips may be used. Also, the lead frames 11 and 12 are a kind of "plate-like electrodes".

FIG. 3 is a cross-sectional view of the semiconductor package taken along the line AA in FIG. 2 after being sealed with resin.

As shown in FIG. 3, the source lead 6a and the diode chip 7 are connected using solder 13a. The diode chip 7 and the lead frame 11 are connected using solder 13b. The source lead 6b and the MOSFET chip 8 are connected using solder 14a. The MOSFET chip 8 and the lead frame 11 are connected using solder 14b. These components are covered with a sealing resin 17 except for the source leads 6a and 6b and part of the lead frame 11. As shown in FIG. Portions of the source leads 6a and 6b and the lead frame 11 exposed to the outside of the sealing resin 17 function as external electrodes.

In other words, on the surface of the diode chip 7 or MOSFET chip 8 (semiconductor chip) opposite to the surface connected to the lead frame 11 (plate-shaped electrode), solders 13a and 14a (bonding material) are used to Electrically connected source leads 6a, 6b (another electrode) are provided.

Although not shown, the control IC chip 9 (FIG. 2) is sealed with a sealing resin 17 together with the diode chip 7, MOSFET chip 8 (semiconductor chip), and lead frames 11 and 12 (plate-shaped electrodes). there is

In this figure, the grooves 15 are provided not only between the diode chip 7 and the MOSFET chip 8 but also at both ends of the lead frame 11 . That is, the grooves 15 are provided at a total of three locations. Protrusions 16 are provided at positions corresponding to the respective grooves 15 on the rear surface of the respective grooves 15 (the lower surface of the lead frame 11). In other words, when focusing on one of the diode chip 7 and the MOSFET chip 8 (semiconductor chip), the groove portion 15 is provided outside two opposite sides of the semiconductor chip (substantially rectangular shape).

The whole of these is the semiconductor package 4 .

As described above, since the protrusions 16 are provided at positions corresponding to the grooves 15, the thickness of the lead frame 11 is not reduced, and the strength of the lead frame 11 can be ensured.

A mixture of lead (Pb) and tin (Sn) was used as the material of the solders 13a, 13b, 14a, and 14b. The materials of the solders 13a, 13b, 14a, 14b are not limited to these.

As materials for the source leads 6a, 6b and the lead frames 11, 12, it is desirable to use copper or a copper alloy, which is excellent in electrical conductivity and thermal conductivity. The thickness of the lead frames 11 and 12 is, for example, about 150 μm.

Considering that the thickness of the solder 3 is preferably about 100 μm, the depth to the deepest part of the groove 15 and the height to the ridge of the protrusion 16 are preferably about 100 μm.

Examples of the method for producing the grooves 15 and the projections 16 include half-etching, press working, and the like.

By providing the groove portion 15, it is possible to prevent the solder 13b and the solder 14b from joining. Thereby, each of the solder 13b and the solder 14b stays in a predetermined position, and the thickness of each of the solder 13b and the solder 14b can be made uniform. Thereby, the strength against the pressing force from the outside can be increased.

FIG. 4 is a cross-sectional view showing a state in which the semiconductor package 4 of FIG. 3 is joined to a disk.

As shown in FIG. 4, the lead frame 11 and the disk 5 are electrically connected using solder 3 (bonding material). Solder 3 can use the same material as solders 13a, 13b, 14a, and 14b in FIG.

Since the protrusion 16 is provided on the lower surface of the lead frame 11, the thickness of the solder 3 connecting the disc 5 and the lead frame 11 becomes uniform, and the strength against external mechanical stress can be increased. A risk of damage to the diode chip 7 and the MOSFET chip 8 can be reduced.

A comparative example will be described below.

FIG. 5 is a cross-sectional view showing a problem of the semiconductor package of Comparative Example 1. FIG.

In this figure, only the configuration different from that in FIG. 4 will be described.

In FIG. 5, a lead frame 11 is provided with a through groove 18 .

A void 19 is formed between the lead frame 11 and the disk 5 . The void 19 is formed by an organic gas generated from the sealing resin 17 when the semiconductor package 4 is joined to the disk 5 using the solder 3 in the secondary mounting process. If the lead frame 11 is provided with the through grooves 18 , the organic gas leaks from the through grooves 18 to the solder 3 side.

FIG. 6 is a cross-sectional view showing a problem of the semiconductor package of Comparative Example 2. FIG.

In this figure, since the lead frame 11 is not provided with grooves (the non-penetrating groove portion 15 and the through groove 18), the solder 13b connecting the diode chip 7 and the lead frame 11, the MOSFET chip 8 and the lead frame 11 are integrated with the solder 14b connecting the . If there is no groove between the solder 13b and the solder 14b in the lead frame 11, the solder 13b and the solder 14b are easily joined in this manner.

Furthermore, in this figure, the diode chip 7 and the MOSFET chip 8 are joined in a tilted state due to the weight of the parts and the shaking that occurs during the manufacturing process. Therefore, the solder 13b has a thin portion. When the diode chip 7 receives mechanical stress from the outside in this state, a chip crack 20 (fracture) is generated in the diode chip 7 . A chip crack 20 may also occur in the MOSFET chip 8 . When chip cracks 20 occur in this manner, the semiconductor module no longer functions.

FIG. 7 is a cross-sectional view showing a state in which the semiconductor package of FIG. 6 is connected to a disk.

In FIG. 7, the lead frame 11 and the disk 5 are connected in a non-parallel manner. Therefore, the thickness of the solder 3 varies. Also in this case, chip cracks 20 may occur in the diode chip 7 due to external mechanical stress, and the semiconductor module may not function. Solder 3 may also crack.

Therefore, it is desirable to make the thickness of the solder 3 uniform.

Modifications of the lead frame according to the embodiment will be described below.

FIG. 8 is a cross-sectional view showing a modification of the lead frame.

In this figure, the lead frame 11 is provided with grooves 15 and protrusions 16 formed by press working. When pressed, the projecting portion 16 has a larger cross-sectional radius than the groove portion 15 . Also, the thickness of the lead frame 11 at the groove 15 and the protrusion 16 is substantially uniform. Therefore, the strength of the lead frame 11 itself can be maintained.

It should be noted that the present invention is not limited to the above examples, and includes various modifications. The above-described embodiments are intended to explain the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to those having all the configurations described.

Also, part of the configuration of the embodiment can be added or replaced without departing from the scope of the present invention.

1: lead, 2: sealing resin, 3: solder, 4: semiconductor package, 5: disk, 6a, 6b: source lead, 7: diode chip, 8: MOSFET chip, 9: control IC chip, 10: capacitor, 11, 12: lead frame, 13a, 13b, 14a, 14b: solder, 15: groove, 16: projection, 17: sealing resin, 18: through groove, 19: void, 20: chip crack.

Claims (9)

two or more semiconductor chips;
A semiconductor device having a plate-shaped electrode in which the two or more semiconductor chips are electrically connected via a bonding material,
The two or more semiconductor chips and the plate-like electrodes are sealed with resin,
The plate-shaped electrode is arranged so that a part thereof is exposed to the outside of the resin,
non-penetrating grooves are provided on the surface of the plate-shaped electrode to which the two or more semiconductor chips are connected,
The non-through groove is provided at a position other than the portion covered with the two or more semiconductor chips,
A semiconductor device according to claim 1, wherein a protrusion is provided at a position corresponding to the non-penetrating groove on the rear surface of the surface of the plate-like electrode. When viewed from above the surface of the plate-shaped electrode,
The semiconductor chip has a substantially rectangular shape,
2. The semiconductor device according to claim 1, wherein said non-through groove is provided between said two adjacent semiconductor chips. When viewed from above the surface of the plate-like electrode,
The semiconductor chip has a substantially rectangular shape,
2. The semiconductor device according to claim 1, wherein said non-penetrating groove is provided outside two opposite sides of said semiconductor chip. 2. The semiconductor device according to claim 1, wherein said non-penetrating groove and said projecting portion are formed by pressing said plate-like electrode. 2. The semiconductor chip according to claim 1, wherein another electrode electrically connected via a bonding material is provided on the surface opposite to the surface connected to the plate-shaped electrode of the semiconductor chip. semiconductor device. 2. The semiconductor device according to claim 1, wherein said two or more semiconductor chips include a MOSFET chip and a diode chip. further comprising a control IC chip that controls the MOSFET chip;
7. The semiconductor device according to claim 6, wherein said control IC chip is sealed with said resin together with said semiconductor chip and said plate-shaped electrode. 2. The semiconductor device according to claim 1, further comprising a disk to which said plate-like electrodes are electrically connected via a bonding material. 2. The semiconductor device according to claim 1, wherein said protrusion has a larger cross-sectional radius than said non-penetrating groove.

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