JP2002217364A - Semiconductor mounting structure - Google Patents

Semiconductor mounting structure

Info

Publication number
JP2002217364A
JP2002217364A JP2001006577A JP2001006577A JP2002217364A JP 2002217364 A JP2002217364 A JP 2002217364A JP 2001006577 A JP2001006577 A JP 2001006577A JP 2001006577 A JP2001006577 A JP 2001006577A JP 2002217364 A JP2002217364 A JP 2002217364A
Authority
JP
Japan
Prior art keywords
semiconductor chip
convex portion
metal
bus bar
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001006577A
Other languages
Japanese (ja)
Inventor
Mikio Naruse
幹夫 成瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2001006577A priority Critical patent/JP2002217364A/en
Publication of JP2002217364A publication Critical patent/JP2002217364A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To prevent generation of cracks of solder and damage of a semiconductor chip which are to be caused by temperature change, in a mounting structure wherein a semiconductor chip is bonded to a bus bar by using solder. SOLUTION: A thin metal plate 10A is arranged between the semiconductor chip 3 and the bus bar 1 which are bonded by using solders 4a, 4b, and has the same coefficient of linear expansion as that of the bus bar 1. Upper side protrusions 11 and lower side protrusions 12 are formed on the metal plate 10A. Tops of the respective protrusions are made to abut against the rear of the semiconductor chip 3 and the bus bar 1. Since the metal plate has the same coefficient of linear expansion as that of the bus bar, stress applied to the solder 4a between the bus bar and the metal plate is small. Since the metal plate is thin, stress of the solder 4b between the metal plate and the semiconductor chip is reduced. Inclination of the metal plate is prevented by the protrusions formed on the metal plate, and thickness of the solders 4a, 4b can be controlled to be always constant.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップを金
属電極板に装着する半導体実装構造に関する。
The present invention relates to a semiconductor mounting structure for mounting a semiconductor chip on a metal electrode plate.

【0002】[0002]

【従来の技術】従来の半導体チップの実装構造として、
バスバーなど電極板に半田を介して接合するものがあ
る。この半田による接合構造は、半導体チップによって
発生する熱を逃がす役割と、半導体チップがその表裏に
電極を備えている場合にバスバーとの間の電気的な接続
を行うという役割を有しているので、半田の確実な接合
状態を確保する必要がある。
2. Description of the Related Art As a conventional semiconductor chip mounting structure,
There is a type such as a bus bar which is joined to an electrode plate via solder. Since the bonding structure using the solder has a role of releasing heat generated by the semiconductor chip and a role of making an electrical connection between the semiconductor chip and the bus bar when the semiconductor chip has electrodes on the front and back thereof. Therefore, it is necessary to ensure a reliable bonding state of the solder.

【0003】しかし、一般にCu(銅)等を使用したバ
スバーに半田を介して半導体チップを接合したもので
は、半導体チップが発熱したときや環境による雰囲気温
度の上昇・下降が繰り返して発生したとき、半導体チッ
プとバスバーの線膨張係数の差によって半田に応力が発
生し、半田に亀裂が生じたり、あるいは半導体チップ自
体が割れて機能不良になるおそれがある。上記応力を低
減するためには半田の層を厚くすればよいが、接合時に
流動性を有する半田の厚さを大きくするには限度があ
る。
[0003] However, in general, when a semiconductor chip is bonded to a bus bar using Cu (copper) or the like via solder, when the semiconductor chip generates heat or when the ambient temperature repeatedly rises and falls due to the environment, Stress may be generated in the solder due to a difference in linear expansion coefficient between the semiconductor chip and the bus bar, and the solder may be cracked, or the semiconductor chip itself may be broken and malfunction. In order to reduce the stress, the thickness of the solder layer may be increased, but there is a limit to increasing the thickness of the solder having fluidity at the time of joining.

【0004】そこでこの対策として、図13に示すよう
に、バスバー30と半導体チップ33の間に線膨張係数
が半導体チップの材料であるSi(シリコン)に近いM
o(モリブデン)あるいはW(タングステン)等を材料
とする金属板35を配置して、バスバー30と金属板3
5の間、および金属板35と半導体チップ33の間をそ
れぞれ半田37a、37bで接合した実装構造が知られ
ている。これによれば、半導体チップ33とバスバー3
0間の半田の総厚が大きくなるとともに、金属板35と
半導体チップ33の線膨張係数が近似しているので、こ
の間の半田37bに高い応力がかかることなく、また半
導体チップ33に割れが生じることもない。
Therefore, as a countermeasure, as shown in FIG. 13, the coefficient of linear expansion between the bus bar 30 and the semiconductor chip 33 is close to that of Si (silicon) which is the material of the semiconductor chip.
A metal plate 35 made of a material such as o (molybdenum) or W (tungsten) is arranged, and the bus bar 30 and the metal plate 3
5 and between the metal plate 35 and the semiconductor chip 33 are connected by solders 37a and 37b, respectively. According to this, the semiconductor chip 33 and the bus bar 3
Since the total thickness of the solder between 0 is large and the linear expansion coefficients of the metal plate 35 and the semiconductor chip 33 are close to each other, high stress is not applied to the solder 37b therebetween and the semiconductor chip 33 is cracked. Not even.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の半導体実装構造では、金属板35の平面サイズは半
導体チップ33のサイズよりも大きい一方、金属板35
とバスバー30間の半田37a自体の厚さは薄い状況下
で、金属板35の線膨張係数がバスバー30の線膨張係
数とかなり相違している。したがって、金属板35とバ
スバー30の間については半導体チップ33の発熱や環
境温度の変化に基づく線膨張係数の差が依然影響を及ぼ
し、半田37aにはバスバー30と金属板35の線膨張
係数の差による応力によって亀裂が発生する。このた
め、電気的および熱的な不具合が発生するという問題が
必ずしも解決されない。したがって、本発明は、上記従
来の問題点に鑑み、半導体チップの発熱や環境温度の変
化によって接合半田に亀裂が生じたり、半導体チップに
損傷を生じることのない半導体実装構造を提供すること
を目的とする。
However, in the above-described conventional semiconductor mounting structure, the plane size of the metal plate 35 is larger than the size of the semiconductor chip 33, while the metal plate 35 is
The linear expansion coefficient of the metal plate 35 is considerably different from the linear expansion coefficient of the bus bar 30 in a situation where the thickness of the solder 37a itself between the metal bar 35 and the bus bar 30 is small. Therefore, the difference in the linear expansion coefficient between the metal plate 35 and the bus bar 30 due to the heat generation of the semiconductor chip 33 and the change in the environmental temperature still has an effect, and the solder 37a has the linear expansion coefficient difference between the bus bar 30 and the metal plate 35. Cracks are generated by the stress caused by the difference. For this reason, the problem that electrical and thermal problems occur is not necessarily solved. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor mounting structure that does not cause cracks in a bonding solder or damage to a semiconductor chip due to heat generation of a semiconductor chip or a change in environmental temperature in view of the above conventional problems. And

【0006】[0006]

【課題を解決するための手段】このため、請求項1の本
発明は、半導体チップを金属電極板に装着する半導体実
装構造であって、半導体チップと金属電極板の間に、該
金属電極板より板厚が薄くかつ半導体チップよりも金属
電極板に近いかまたは金属電極板と同一の線膨張係数を
有する金属薄板を配置するとともに、金属電極板と金属
薄板の間および半導体チップと金属薄板の間を接合材で
接合するものとした。
According to the present invention, there is provided a semiconductor mounting structure for mounting a semiconductor chip on a metal electrode plate, wherein the semiconductor chip is mounted between the semiconductor chip and the metal electrode plate by the metal electrode plate. A thin metal plate having a thinner thickness and closer to the metal electrode plate than the semiconductor chip or having the same linear expansion coefficient as the metal electrode plate is arranged, and the space between the metal electrode plate and the metal thin plate and between the semiconductor chip and the metal thin plate are arranged. Joining was performed with a joining material.

【0007】請求項2の発明は、金属薄板に半導体チッ
プ側に突出する上側凸部と金属電極板側に突出する下側
凸部とが形成されており、上側凸部の頂部が半導体チッ
プに接し、下側凸部が金属電極板に接しているものとし
た。請求項3の発明は、さらに上記の上側凸部と下側凸
部とが、それぞれ半導体チップの周辺輪郭線の内側に位
置させて形成されているものとした。
According to a second aspect of the present invention, an upper protrusion protruding toward the semiconductor chip and a lower protrusion protruding toward the metal electrode plate are formed on the thin metal plate, and the top of the upper protrusion is formed on the semiconductor chip. The lower convex portion was in contact with the metal electrode plate. According to a third aspect of the present invention, the upper convex portion and the lower convex portion are formed so as to be positioned inside the peripheral contour of the semiconductor chip.

【0008】請求項4の発明は、金属薄板の下側凸部が
ビード状で、半導体チップの周辺輪郭線上に重なる位置
に形成され、上側凸部が下側凸部より内側に形成されて
いるものとした。下側凸部が形成された部分では、下側
凸部14の突出分だけ窪んでいるので、半導体チップの
辺縁と金属薄板の間隙が増す。
According to a fourth aspect of the present invention, the lower convex portion of the metal thin plate has a bead shape, is formed at a position overlapping the peripheral contour of the semiconductor chip, and the upper convex portion is formed inside the lower convex portion. It was taken. In the portion where the lower convex portion is formed, the concave portion is depressed by the amount of protrusion of the lower convex portion 14, so that the gap between the edge of the semiconductor chip and the thin metal plate increases.

【0009】請求項5の発明は、ビード状の下側凸部が
とくに四角形状の平面形をなすように半導体チップの周
辺輪郭線にそって連続しているものとした。また、請求
項6の発明は、上側凸部が金属薄板の辺縁まで延びる脚
部を含むものとした。
According to a fifth aspect of the present invention, the bead-shaped lower convex portion is continuous along the peripheral contour of the semiconductor chip so as to form a quadrangular planar shape. In the invention according to claim 6, the upper convex portion includes a leg extending to the edge of the metal sheet.

【0010】請求項7の発明は、金属薄板の上側凸部が
ビード状で半導体チップの周辺輪郭線の内側から金属薄
板の辺縁まで延び、下側凸部がビード状で半導体チップ
の周辺輪郭線の内側から金属薄板の対角線上を当該金属
薄板の角部まで延びているものとした。
According to a seventh aspect of the present invention, the upper convex portion of the metal thin plate has a bead shape and extends from the inside of the peripheral contour line of the semiconductor chip to the periphery of the metal thin plate, and the lower convex portion has a bead shape and has a peripheral shape of the semiconductor chip. The diagonal line of the metal sheet extends from the inside of the line to the corner of the metal sheet.

【0011】請求項8の発明は、金属電極板が銅または
アルミニウムあるいはこれらを含む合金からなり、金属
薄板が金属電極板と同金属系の材料からなるものとし
た。接合部における応力の吸収度合いと放熱性が高く、
電気的な損失も小さくなる。
According to the invention of claim 8, the metal electrode plate is made of copper or aluminum or an alloy containing them, and the thin metal plate is made of the same metal material as the metal electrode plate. High degree of stress absorption and heat dissipation at the joint,
Electrical losses are also reduced.

【0012】[0012]

【発明の効果】請求項1の発明は、半導体チップを接合
材で金属電極板に装着する半導体実装構造において、接
合部の半導体チップと金属電極板の間に、金属電極板よ
り板厚が薄くかつ金属電極板とほぼ同様の線膨張係数を
有する金属薄板を配置するものとしたので、半導体チッ
プの発熱や環境温度の変化に対する金属電極板と金属薄
板間の接合材の応力が緩和され、また金属薄板と半導体
チップ間の接合材にかかる応力も低減されて、長期の信
頼性を維持できる効果を有する。
According to the first aspect of the present invention, in a semiconductor mounting structure in which a semiconductor chip is mounted on a metal electrode plate with a bonding material, the thickness between the semiconductor chip and the metal electrode plate at the bonding portion is smaller than that of the metal electrode plate and the metal is thin. Since a metal thin plate having a coefficient of linear expansion substantially similar to that of the electrode plate is arranged, the stress of the bonding material between the metal electrode plate and the metal thin plate against heat generation of the semiconductor chip and a change in environmental temperature is reduced, and The stress applied to the bonding material between the semiconductor chip and the semiconductor chip is also reduced, which has the effect of maintaining long-term reliability.

【0013】請求項2の発明は、金属薄板に上側凸部と
下側凸部とを形成し、上側凸部の頂部15aが半導体チ
ップに接し、下側凸部が金属電極板に接しているものと
したので、さらに金属薄板の上下の接合材の厚さを一定
に管理できるという効果を有し、また半導体チップを金
属電極板に対して水平に保持できる。請求項3の発明
は、上側凸部と下側凸部とをそれぞれ半導体チップの周
辺輪郭線の内側に位置させているので、さらに金属薄板
が半導体チップの下で反ることを防止でき、加えて、金
属薄板の面積を小さくできるので金属電極板から受ける
応力も小さくできる利点を有する。
According to a second aspect of the present invention, an upper convex portion and a lower convex portion are formed on a metal thin plate, and the top portion 15a of the upper convex portion is in contact with the semiconductor chip, and the lower convex portion is in contact with the metal electrode plate. Since the thickness of the bonding material above and below the metal thin plate can be controlled to be constant, the semiconductor chip can be held horizontally with respect to the metal electrode plate. According to the third aspect of the present invention, since the upper convex portion and the lower convex portion are respectively positioned inside the peripheral contour of the semiconductor chip, the metal sheet can be further prevented from warping under the semiconductor chip. In addition, since the area of the thin metal plate can be reduced, the stress received from the metal electrode plate can be reduced.

【0014】請求項4の発明は、金属薄板の下側凸部を
ビード状とし、半導体チップの周辺輪郭線上に重なるよ
う位置させたので、半導体チップの辺縁と金属薄板の間
隙が増し接合材の厚さが増大することにより、辺縁で厳
しくなる応力の低減効果が大きい。とくに請求項5の発
明は、ビード状の下側凸部を四角形状の平面形をなすよ
うに半導体チップの周辺輪郭線にそって連続させている
ので、半導体チップの全周にそって接合材の厚さが増大
し、一層応力が低減する。
According to a fourth aspect of the present invention, since the lower convex portion of the thin metal plate is formed in a bead shape and positioned so as to overlap the peripheral contour of the semiconductor chip, the gap between the edge of the semiconductor chip and the thin metal plate increases, and the joining material is increased. When the thickness of the metal is increased, the effect of reducing the stress that becomes severe at the periphery is large. In particular, the invention according to claim 5 is characterized in that the bead-shaped lower convex portion is continuous along the peripheral contour line of the semiconductor chip so as to form a quadrangular planar shape, so that the bonding material is formed along the entire periphery of the semiconductor chip. And the stress is further reduced.

【0015】請求項6の発明は、ビード状の上側凸部が
金属薄板の辺縁まで延びる脚部を含むものとしたので、
脚部がボイドの抜け通路となって接合部に残留するボイ
ドが低減される。
According to a sixth aspect of the present invention, the bead-shaped upper convex portion includes the leg portion extending to the edge of the metal sheet.
The leg serves as a void escape passage, and voids remaining at the joint are reduced.

【0016】請求項7の発明は、金属薄板の上下のビー
ド状の凸部を放射状に辺縁または角部まで延ばし、とく
に下側凸部が対角線上を金属薄板の角部まで延びるもの
としたので、上下の凸部がそれぞれ接合材中のボイドの
抜け通路となるとともに、応力がとくに集中する角部で
半導体チップと金属薄板間の接合材の厚みが増大し、応
力が緩和される。
According to a seventh aspect of the present invention, the upper and lower bead-shaped protrusions of the metal sheet are radially extended to the edges or corners, and particularly the lower protrusions extend diagonally to the corners of the metal sheet. Therefore, the upper and lower convex portions each serve as a passage for the void in the bonding material, and the thickness of the bonding material between the semiconductor chip and the metal thin plate increases at the corner where the stress is particularly concentrated, thereby alleviating the stress.

【0017】請求項8の発明は、金属電極板が銅または
アルミニウムあるいはこれらを含む合金からなり、金属
薄板が金属電極板と同金属系の材料からなるものとした
ので、電気抵抗が小さいため電気的な損失が低減でき、
熱伝導率が大きいため半導体チップが発熱した際に金属
電極板への熱移動が容易にできて、半導体実装構造の安
定した長期信頼性を維持できる。
According to the invention of claim 8, the metal electrode plate is made of copper or aluminum or an alloy containing them, and the thin metal plate is made of the same metal-based material as the metal electrode plate. Loss can be reduced,
Since the heat conductivity is large, when the semiconductor chip generates heat, heat can be easily transferred to the metal electrode plate, and stable long-term reliability of the semiconductor mounting structure can be maintained.

【0018】[0018]

【発明の実施の形態】以下、本発明の実施の形態を実施
例により説明する。図1は本発明をインバータ回路の実
装ユニットに適用した第1の実施例を示す上面図、図2
は図1のA−A部断面図である。また、図3は本実装ユ
ニットにおけるバスバーの位置関係を示す斜視図であ
り、樹脂、放熱シート、ヒートシンクを省略している。
実装ユニット100は、全体が上方に開口したケース状
を呈する樹脂ベース2に、金属板からなるバスバー1
a、1bおよび1cをモールドして形成されている。バ
スバー1a、1bおよび1cは、Cu(銅)、Al(ア
ルミニウム)若しくはこれらを含む合金からなってい
る。バスバー1aと1bはそれぞれ樹脂ベース2の底面
に露出しており、バスバー1cはバスバー1bの上側に
一部重ねて配置され、各バスバーは互いに離間して絶縁
されている。
Embodiments of the present invention will be described below with reference to examples. FIG. 1 is a top view showing a first embodiment in which the present invention is applied to a mounting unit for an inverter circuit.
FIG. 2 is a sectional view taken along the line AA in FIG. FIG. 3 is a perspective view showing the positional relationship of the bus bars in this mounting unit, and omits the resin, the heat radiation sheet, and the heat sink.
The mounting unit 100 includes a bus bar 1 made of a metal plate and a resin base 2 having a case shape which is entirely opened upward.
a, 1b and 1c are molded. The bus bars 1a, 1b and 1c are made of Cu (copper), Al (aluminum) or an alloy containing these. The bus bars 1a and 1b are exposed on the bottom surface of the resin base 2, respectively, and the bus bar 1c is partially overlapped on the upper side of the bus bar 1b, and the bus bars are separated from each other and insulated.

【0019】MOSFETからなる半導体チップ3aと
3bが、それぞれ接合部20によって金属電極板として
のバスバー1aと1bの上面に接合されている。半導体
チップ3a、3bはそれぞれバスバーに接合される裏面
がドレイン電極とされ、上面がソース電極となってい
る。半導体チップ3aの上面とバスバー1cが金属ワイ
ヤ5aによって接続されており、また、半導体チップ3
aの上面はゲート端子6aと金属ワイヤ9aによって接
続されている。
Semiconductor chips 3a and 3b made of MOSFETs are joined to upper surfaces of bus bars 1a and 1b as metal electrode plates by joining portions 20, respectively. Each of the semiconductor chips 3a and 3b has a back surface joined to the bus bar as a drain electrode and an upper surface as a source electrode. The upper surface of the semiconductor chip 3a and the bus bar 1c are connected by a metal wire 5a.
The upper surface of a is connected to the gate terminal 6a by a metal wire 9a.

【0020】半導体チップ3bの上面とバスバー1aが
金属ワイヤ5bによって接続されており、また、半導体
チップ3bの上面はゲート端子6bと金属ワイヤ9bに
よって接続されている。これにより、図4に示されるよ
うに、半導体チップ3aと3bが直列に接続された回路
が形成される。バスバー1bが回路のP端子になり、バ
スバー1cがN端子、バスバー1aが出力のINV端子
となる。
The upper surface of the semiconductor chip 3b and the bus bar 1a are connected by a metal wire 5b, and the upper surface of the semiconductor chip 3b is connected by a gate terminal 6b and a metal wire 9b. Thus, as shown in FIG. 4, a circuit in which the semiconductor chips 3a and 3b are connected in series is formed. The bus bar 1b serves as a P terminal of the circuit, the bus bar 1c serves as an N terminal, and the bus bar 1a serves as an output INV terminal.

【0021】バスバー1a、1bが露出した樹脂ベース
2の底面には、電気的な絶縁性を有する放熱シート7を
介してヒートシンク8が取り付けられている。これによ
り、半導体チップ3a、3bが動作する際に発生する熱
はヒートシンク8に伝達され、放熱される。
A heat sink 8 is attached to the bottom surface of the resin base 2 from which the bus bars 1a and 1b are exposed via a heat insulating sheet 7 having electrical insulation. As a result, heat generated when the semiconductor chips 3a and 3b operate is transmitted to the heat sink 8 and radiated.

【0022】図5は半導体チップ3a、3bの接合部を
拡大して示す断面図である。なお、接合部の構造は両半
導体チップとも同じであるから、以下、半導体チップお
よびバスバーの参照番号を3および1として説明する。
接合部20は、バスバー1と半導体チップ3の間に金属
薄板10を配置し、金属薄板10とバスバー1の間を接
合材としての半田4aで接合し、半導体チップ3と金属
薄板10の間を同じく接合材としての半田4bで接合し
ている。金属薄板10の平面サイズは半導体チップ3よ
りも若干大きく設定されている。
FIG. 5 is an enlarged cross-sectional view showing the junction between the semiconductor chips 3a and 3b. Since the structure of the bonding portion is the same for both semiconductor chips, the semiconductor chip and the bus bar will be described below with reference numerals 3 and 1.
In the joining portion 20, the metal thin plate 10 is arranged between the bus bar 1 and the semiconductor chip 3, and the metal thin plate 10 and the bus bar 1 are joined with the solder 4a as a joining material, and the semiconductor chip 3 and the metal thin plate 10 are joined. Similarly, they are joined with solder 4b as a joining material. The plane size of the thin metal plate 10 is set slightly larger than that of the semiconductor chip 3.

【0023】金属薄板10はバスバー1と同一のCu、
Alまたはこれらを含む合金からなり、その板厚はバス
バー1より薄く設定されている。金属薄板10の材料で
あるCuやAlは、図6の特性表に示されるように、他
の材料MoやWに比べて比較的ヤング率が小さく、熱伝
導率が大きく、また電気抵抗率も小さい。ヤング率の値
が小さいほど柔らかく、発生した応力の吸収度合いが大
きい。熱伝導率が大きいほど熱を伝えやすいため放熱や
熱拡散に有効である。また、電気抵抗率の値が小さいほ
ど電気的な損失が小さい。電気的な損失分は熱に変わ
り、これによりバスバー1および金属薄板10自体が発
熱源になり、半導体チップ3から発生した熱の放熱を妨
げる要因となるので、接合部の材料として電気抵抗率は
できるだけ小さいことが望ましい。
The metal sheet 10 is made of the same Cu as the bus bar 1,
It is made of Al or an alloy containing them, and its plate thickness is set thinner than the bus bar 1. As shown in the characteristic table of FIG. 6, Cu and Al, which are the materials of the metal sheet 10, have a relatively small Young's modulus, a large thermal conductivity, and a high electrical resistivity as compared with other materials Mo and W. small. The smaller the value of the Young's modulus, the softer and the greater the degree of absorption of the generated stress. The higher the thermal conductivity, the easier it is to conduct heat, which is effective for heat dissipation and heat diffusion. Further, the smaller the value of the electric resistivity, the smaller the electric loss. The electric loss is converted into heat, and the bus bar 1 and the thin metal plate 10 themselves become heat sources, thereby hindering the heat radiation from the semiconductor chip 3. It is desirable to be as small as possible.

【0024】本実施例は以上のように構成され、バスバ
ー1(1a、1b)と半導体チップ3(3a、3b)の
接合部として、バスバー1と半導体チップ3の間にバス
バー1と同じ線膨張係数を有する金属薄板10を配置
し、金属薄板10とバスバー1の間および半導体チップ
3と金属薄板10の間を半田で接合するものとしたの
で、応力が2層の半田に分散されるとともに、とくに金
属薄板10とバスバー1の線膨張係数が同じのため半導
体チップ3の発熱や環境温度の変化に対するバスバー1
と金属薄板10の間における半田の応力が緩和される。
The present embodiment is constructed as described above, and has the same linear expansion as the bus bar 1 between the bus bar 1 and the semiconductor chip 3 as a joint between the bus bar 1 (1a, 1b) and the semiconductor chip 3 (3a, 3b). Since the thin metal plate 10 having a coefficient is arranged and the thin metal plate 10 and the bus bar 1 and the semiconductor chip 3 and the thin metal plate 10 are joined by solder, the stress is dispersed to the two layers of solder. In particular, since the coefficient of linear expansion of the metal sheet 10 and the bus bar 1 is the same, the bus bar 1 against heat generation of the semiconductor chip 3 and a change in the environmental temperature.
The stress of the solder between the metal sheet 10 and the metal sheet 10 is reduced.

【0025】また、半田1層で半導体チップをバスバー
に接合した場合に接合相手であるバスバーが薄いほど接
合部にかかる応力が低減されることから、金属薄板10
と半導体チップ3の間についても、金属薄板10の厚さ
をバスバー1より薄くしてあり、また当該金属薄板10
は半導体チップ3と同程度の大きさでバスバー1に対し
て小さいので、線膨張係数に差があるにもかかわらず、
半田4bにかかる応力もいっそう低減される。したがっ
て、半導体チップとバスバー間の応力がバランス良く緩
和、低減されるので、金属薄板10を挟む上下の半田に
亀裂が発生することなく、電気的および熱的な不具合が
回避される。
Further, when the semiconductor chip is joined to the bus bar with one layer of solder, the stress applied to the joining portion is reduced as the joining partner of the bus bar becomes thinner.
Also between the semiconductor chip 3 and the semiconductor chip 3, the thickness of the metal sheet 10 is made thinner than the bus bar 1, and the metal sheet 10
Is about the same size as the semiconductor chip 3 and smaller than the bus bar 1, so that despite the difference in linear expansion coefficient,
The stress applied to the solder 4b is further reduced. Therefore, the stress between the semiconductor chip and the bus bar is alleviated and reduced in a well-balanced manner, so that cracks do not occur in the upper and lower solders sandwiching the thin metal plate 10, and electrical and thermal problems are avoided.

【0026】つぎに、本発明の第2の実施例について説
明する。これは、バスバーと半導体チップの間に配置す
る金属薄板に凸部を設けたものである。図7は本実施例
における接合部を示す断面図であり、図8は金属薄板の
詳細を示す図である。図8の(a)は平面図、(b)は
側面図、(c)は(a)におけるB−B部断面図であ
る。なお、図7は図8の(a)におけるC−C部の断面
に相当する。本実施例の金属薄板10Aは、第1の実施
例における金属薄板10と同じくバスバー1と同じ線膨
張係数を有する材料からなり、その上下にドット状の凸
部が形成されている。
Next, a second embodiment of the present invention will be described. In this case, a metal sheet disposed between a bus bar and a semiconductor chip is provided with a projection. FIG. 7 is a cross-sectional view showing a joint in this embodiment, and FIG. 8 is a view showing details of a metal thin plate. 8A is a plan view, FIG. 8B is a side view, and FIG. 8C is a sectional view taken along line BB in FIG. FIG. 7 corresponds to a cross section taken along the line CC in FIG. The metal sheet 10A of the present embodiment is made of a material having the same linear expansion coefficient as the bus bar 1 like the metal sheet 10 of the first embodiment, and has dot-shaped convex portions formed on the upper and lower sides.

【0027】半導体チップ3側に突出する上側凸部11
は互いに同一の高さで、金属薄板10A上に仮想的に描
いた格子の中央部の交点位置4個所に設けられ、バスバ
ー1側に突出する下側凸部12も互いに同一の高さで、
上側凸部11を囲む外側の交点位置8個所に設けられて
いる。これらの上側凸部11および下側凸部12は、図
8の(a)に示すように、半導体チップ3を金属薄板1
0Aの中央に重ねたときいずれも半導体チップ3の周辺
輪郭内に位置している。
Upper convex portion 11 protruding toward semiconductor chip 3
Are provided at four intersections at the center of the grid virtually drawn on the metal sheet 10A, and the lower projections 12 projecting toward the bus bar 1 are also at the same height,
It is provided at eight locations of the outer intersections surrounding the upper convex portion 11. As shown in FIG. 8A, the upper convex portion 11 and the lower convex portion 12 connect the semiconductor chip 3 to the metal thin plate 1.
All of them are located in the peripheral contour of the semiconductor chip 3 when they are superimposed on the center of 0A.

【0028】とくに図7に示すように、上側凸部11の
頂点は半導体チップ3の裏面に接し、下側凸部12の頂
点はバスバー1に接して、金属薄板10Aとバスバー1
の間は半田4aで接合され、金属薄板10Aと半導体チ
ップ3の間は半田4bで接合されている。上側凸部11
の高さと下側凸部12の高さは同一とされ、これにより
金属薄板10Aを挟む上下の半田の厚さは同一となって
いる。その他の構成は第1の実施例と同じである。
Particularly, as shown in FIG. 7, the apex of the upper convex portion 11 contacts the back surface of the semiconductor chip 3, the apex of the lower convex portion 12 contacts the bus bar 1, and the thin metal plate 10A and the bus bar 1 contact each other.
Are joined by solder 4a, and the thin metal plate 10A and the semiconductor chip 3 are joined by solder 4b. Upper convex part 11
And the height of the lower protruding portion 12 are the same, so that the thickness of the upper and lower solders sandwiching the thin metal plate 10A is the same. Other configurations are the same as those of the first embodiment.

【0029】本実施例は以上のように構成され、バスバ
ー1と半導体チップ3の接合部として、バスバー1と半
導体チップ3の間に上側凸部11および下側凸部12を
備える金属薄板10Aを配置し、金属薄板10Aとバス
バー1の間および半導体チップ3と金属薄板10Aの間
を半田で接合するものとしたので、第1の実施例と同じ
効果を有するとともに、各凸部11、12の頂点を半導
体チップ3およびバスバー1に当接させることにより金
属薄板10Aの傾きが抑えられ、また金属薄板10Aを
挟む上下の半田の厚さを常に一定に管理できるという効
果を有する。
The present embodiment is constructed as described above. As a joining portion between the bus bar 1 and the semiconductor chip 3, a metal sheet 10A having an upper convex portion 11 and a lower convex portion 12 between the bus bar 1 and the semiconductor chip 3 is provided. Since it is arranged and joined between the metal thin plate 10A and the bus bar 1 and between the semiconductor chip 3 and the metal thin plate 10A by solder, it has the same effect as that of the first embodiment, and has the same effect as the first embodiment. By bringing the apex into contact with the semiconductor chip 3 and the bus bar 1, the inclination of the thin metal plate 10A is suppressed, and the thickness of the upper and lower solders sandwiching the thin metal plate 10A can be constantly controlled.

【0030】図9、図10は本発明の第3の実施例を示
す。図9は接合部を示す断面図、図10は金属薄板の詳
細を示す図である。図10の(a)は平面図、(b)は
側面図である。図9は図10の(a)におけるD−D部
の断面に相当する。本実施例の金属薄板10Bは、第1
の実施例における金属薄板10と同じくバスバー1と同
じ線膨張係数を有する材料からなり、その上下にビード
状の凸部が形成されている。
FIGS. 9 and 10 show a third embodiment of the present invention. FIG. 9 is a cross-sectional view showing a joint, and FIG. 10 is a view showing details of a thin metal plate. 10A is a plan view, and FIG. 10B is a side view. FIG. 9 corresponds to a cross section taken along the line DD in FIG. The metal sheet 10B of the present embodiment is
As in the case of the thin metal plate 10 of this embodiment, the bus bar 1 is made of a material having the same linear expansion coefficient as that of the metal thin plate 10, and bead-shaped projections are formed on the upper and lower sides.

【0031】半導体チップ3側に突出する上側凸部13
は金属薄板10Bの中央部に四角形状に設けられ、バス
バー1側に突出する下側凸部14は上側凸部13を囲む
外側に同じく四角形状に設けられている。上側凸部13
および下側凸部14はそれぞれ全周にわたって高さを一
定に保持し、また上側凸部13の高さと下側凸部14の
高さは同一に設定されている。上側凸部13は、半導体
チップ3を金属薄板10Bの中央に重ねたとき半導体チ
ップ3の周辺輪郭内に位置し、下側凸部14は図10の
(a)に示すように、仮想線で示す半導体チップ3の周
辺輪郭線上に重なるように設定されている。
Upper convex portion 13 protruding toward semiconductor chip 3
Is provided in the center of the thin metal plate 10 </ b> B in a square shape, and the lower convex portion 14 protruding toward the bus bar 1 is also provided in a rectangular shape outside the upper convex portion 13. Upper convex part 13
The lower projection 14 and the lower projection 14 keep the height constant over the entire circumference, and the height of the upper projection 13 and the height of the lower projection 14 are set to be the same. The upper convex portion 13 is located within the peripheral contour of the semiconductor chip 3 when the semiconductor chip 3 is superimposed on the center of the thin metal plate 10B, and the lower convex portion 14 is represented by a virtual line as shown in FIG. It is set so as to overlap the peripheral contour of the semiconductor chip 3 shown.

【0032】とくに図9に示すように、上側凸部13の
頂点は半導体チップ3の裏面に接し、下側凸部14の頂
点はバスバー1に接して、金属薄板10Aとバスバー1
の間は半田4aで接合され、金属薄板10Aと半導体チ
ップ3の間は半田4bで接合されている。金属薄板10
を金属薄板10Bに変更した以外の、その他の構成は第
1の実施例と同じである。
In particular, as shown in FIG. 9, the apex of the upper convex portion 13 contacts the back surface of the semiconductor chip 3, the apex of the lower convex portion 14 contacts the bus bar 1, and the thin metal plate 10A and the bus bar 1
Are joined by solder 4a, and the thin metal plate 10A and the semiconductor chip 3 are joined by solder 4b. Metal sheet 10
The other configuration is the same as that of the first embodiment except that the structure is changed to the metal sheet 10B.

【0033】本実施例は、以上のように構成され、バス
バー1と半導体チップ3の接合部として、バスバー1と
半導体チップ3の間にそれぞれ四角形状を形成したビー
ド状の上側凸部13および下側凸部14を備える金属薄
板10Bを配置して、金属薄板10Bとバスバー1の間
および半導体チップ3と金属薄板10Bの間を半田で接
合し、とくに下側凸部14を半導体チップ3の周辺輪郭
線上に重なるものとしたので、半導体チップ3の周辺輪
郭線にそって当該半導体チップに接合する半田4bの厚
さが、下側凸部14の突出分(すなわち半導体チップ3
側から見たときの窪み分)だけ増大する。この結果、第
2の実施例と同じ効果を有するとともに、通常なら応力
が集中する半導体チップ3の周辺端部の応力が一層緩和
される。
The present embodiment is constructed as described above, and as a joint portion between the bus bar 1 and the semiconductor chip 3, a bead-shaped upper convex portion 13 having a square shape formed between the bus bar 1 and the semiconductor chip 3, and a lower portion. A metal thin plate 10B having a side convex portion 14 is arranged, and the metal thin plate 10B and the bus bar 1 and the semiconductor chip 3 and the metal thin plate 10B are joined by soldering. The thickness of the solder 4b joined to the semiconductor chip 3 along the peripheral contour line of the semiconductor chip 3 is determined by the thickness of the lower convex portion 14 (that is, the semiconductor chip 3).
(When viewed from the side). As a result, the same effect as that of the second embodiment is obtained, and the stress at the peripheral end of the semiconductor chip 3 where the stress is normally concentrated is further reduced.

【0034】なお、第3の実施例では金属薄板10Bの
中央部の上側凸部13をビード状で四角形状としたが、
中央部は第2の実施例と同様にドット状としてもよい。
In the third embodiment, the upper convex portion 13 at the center of the thin metal plate 10B is formed in a bead square shape.
The central portion may be dot-shaped as in the second embodiment.

【0035】つぎに本発明の第4の実施例について説明
する。これは、バスバーと半導体チップの間に配置する
金属薄板の凸部の形状を異ならせたものである。図11
は第4の実施例における金属薄板を示し、(a)は平面
図、(b)は側面図である。金属薄板10Cに設けられ
る上側凸部15および下側凸部16はいずれもビード状
に形成されている。金属薄板10Cはバスバーと同じ線
膨張係数を有する材料からなる。
Next, a fourth embodiment of the present invention will be described. This is one in which the shape of the convex portion of the thin metal plate arranged between the bus bar and the semiconductor chip is different. FIG.
7A and 7B show a metal sheet according to a fourth embodiment, wherein FIG. 7A is a plan view and FIG. 7B is a side view. Both the upper convex portion 15 and the lower convex portion 16 provided on the thin metal plate 10C are formed in a bead shape. The metal sheet 10C is made of a material having the same linear expansion coefficient as the bus bar.

【0036】上側凸部15は、金属薄板10Cの中央部
において、金属薄板10Cの辺縁に平行な頂部15aと
頂部15aの中間から辺縁まで延びる脚部15bからな
るT字形をなし、各辺縁に対応して4つ形成されてい
る。各上側凸部15の頂部15aは互いに接続していな
いが、4本の頂部15aで全体として四角形状を呈して
いる。また、各上側凸部15の脚部15bの先端には金
属薄板10Cの各辺縁の2等分点に位置している。
The upper protruding portion 15 has a T-shape at the center of the metal sheet 10C, comprising a top 15a parallel to the edge of the metal sheet 10C and a leg 15b extending from the middle of the top 15a to the edge. Four are formed corresponding to the edges. Although the tops 15a of the respective upper protrusions 15 are not connected to each other, the four tops 15a have a rectangular shape as a whole. Further, the tip of the leg portion 15b of each upper convex portion 15 is located at a bisecting point of each edge of the thin metal plate 10C.

【0037】下側凸部16は、図11の(a)に仮想線
で示す半導体チップ3の周辺輪郭線上に重なるように、
金属薄板10Cの各辺縁近傍に沿って延びている。この
下側凸部16は辺縁ごとに上側凸部15の脚部15bで
分断された2本が配置され、全体として上側凸部15の
頂部15aによる四角形状を囲む四角形状を呈してい
る。金属薄板10Bを金属薄板10Cに変更した以外
の、その他の構成は第3の実施例と同じである。
The lower convex portion 16 is formed so as to overlap with the peripheral contour of the semiconductor chip 3 indicated by a virtual line in FIG.
The metal sheet 10C extends along the vicinity of each edge. The lower convex portion 16 is provided with two portions separated by a leg 15b of the upper convex portion 15 for each edge, and has a square shape surrounding the square shape of the top portion 15a of the upper convex portion 15 as a whole. The other configuration is the same as that of the third embodiment except that the metal sheet 10B is changed to the metal sheet 10C.

【0038】本実施例によれば、下側凸部16が半導体
チップ3の周辺輪郭線上に重なるように設けられている
ので、第3の実施例と同様に、半導体チップ3の周辺輪
郭線にそった半田4bの厚さが、下側凸部16の突出分
だけ増大し、半導体チップ3の周辺端部の応力が緩和さ
れる。さらに、上側凸部15がT字形をなしてその脚部
15bが金属薄板10Cの辺縁まで延びているので、金
属薄板10Cの下側に発生するボイド(空気泡)の抜け
通路となり、接合部に残留するボイドが低減される効果
を有している。
According to the present embodiment, since the lower protruding portion 16 is provided so as to overlap the peripheral contour of the semiconductor chip 3, the lower convex part 16 is provided on the peripheral contour of the semiconductor chip 3 as in the third embodiment. The thickness of the solder 4b is increased by the amount of protrusion of the lower convex portion 16, and the stress at the peripheral end of the semiconductor chip 3 is reduced. Further, since the upper convex portion 15 has a T-shape and its leg portion 15b extends to the edge of the thin metal plate 10C, it serves as a passage for voids (air bubbles) generated below the thin metal plate 10C, and becomes a joint. This has the effect of reducing voids remaining in the substrate.

【0039】図12は金属薄板の凸部の形状をさらに異
ならせた第5の実施例を示す図である。図の(a)は平
面図、(b)は側面図である。金属薄板10Dに設けら
れる上側凸部17および下側凸部18はいずれもビード
状に形成されている。金属薄板10Dはバスバーと同じ
線膨張係数を有する材料からなる。上側凸部17は、金
属薄板10Dの中心近傍から辺縁に対して直角方向に辺
縁まで延びており、各辺縁に対応して4つ形成されてい
る。そしてその先端は各辺縁の2等分点に位置してい
る。
FIG. 12 is a view showing a fifth embodiment in which the shape of the convex portion of the thin metal plate is further changed. (A) of the figure is a plan view, and (b) is a side view. Both the upper convex portion 17 and the lower convex portion 18 provided on the thin metal plate 10D are formed in a bead shape. The metal sheet 10D is made of a material having the same linear expansion coefficient as the bus bar. The upper convex portions 17 extend from the vicinity of the center of the thin metal plate 10D to the edges in a direction perpendicular to the edges, and are formed in four corresponding to the edges. The tip is located at the bisecting point of each edge.

【0040】下側凸部18は、金属薄板10Dの各角か
ら対角線上に延び、その中心に向かう先端は、金属薄板
10Dの中心から上側凸部17の中心側先端よりも外側
で止まっている。上側凸部17および下側凸部18の各
中心側先端は、いずれも図12の(a)に仮想線で示す
半導体チップ3の周辺輪郭線よりも内側(中央側)に位
置している。以上のように、上側凸部17および下側凸
部18は全体として放射状に辺縁および角まで延びた形
となっている。これにより、接合部に生じるボイドは、
例えば半田付け温度が半田の融点以上になった状態で真
空引きを行うことにより効果的に抜くことができる。ま
た、下側凸部18は半導体チップ3の角部に重なってい
る。金属薄板10Bを金属薄板10Dに変更した以外
の、その他の構成は第3の実施例と同じである。
The lower protruding portion 18 extends diagonally from each corner of the thin metal plate 10D, and the tip toward the center thereof is stopped outside the center of the upper protruding portion 17 from the center of the thin metal plate 10D. . Each of the center-side distal ends of the upper convex portion 17 and the lower convex portion 18 is located on the inner side (center side) of the peripheral contour of the semiconductor chip 3 indicated by a virtual line in FIG. As described above, the upper convex portion 17 and the lower convex portion 18 extend radially to the edges and corners as a whole. As a result, the void generated at the joint is
For example, it is possible to remove the solder effectively by performing vacuum evacuation while the soldering temperature is equal to or higher than the melting point of the solder. The lower protruding portion 18 overlaps a corner of the semiconductor chip 3. The other configuration is the same as that of the third embodiment except that the metal sheet 10B is changed to the metal sheet 10D.

【0041】本実施例によれば、バスバーと同じ線膨張
係数を有する金属薄板をバスバーと半導体チップの間に
配置した点、および金属薄板に上下の凸部を備える点
で、第2の実施例と同じ効果を有するとともに、上側凸
部17および下側凸部18が全て放射状に辺縁および角
まで延びているので、接合部に残留するボイドの低減効
果が大きい。そしてさらに、下側凸部18が半導体チッ
プ3の角部に重なっており、応力がとくに集中する半導
体チップ3の角部において半導体チップ3と金属薄板間
の半田の厚みが増大するので、応力が緩和され、半導体
チップ3への応力による影響が低減される。
According to the present embodiment, the second embodiment is different from the second embodiment in that a thin metal plate having the same linear expansion coefficient as that of the bus bar is arranged between the bus bar and the semiconductor chip, and that the thin metal plate has upper and lower convex portions. In addition to the same effect as described above, since the upper convex portion 17 and the lower convex portion 18 all extend radially to the edges and corners, the effect of reducing voids remaining at the joint is large. Further, since the lower protruding portion 18 overlaps the corner of the semiconductor chip 3 and the thickness of the solder between the semiconductor chip 3 and the thin metal plate increases at the corner of the semiconductor chip 3 where the stress is particularly concentrated, the stress is reduced. As a result, the influence of the stress on the semiconductor chip 3 is reduced.

【0042】なお、各実施例において、金属薄板の材質
をバスバー1と同一としたが、これに限定されず、例え
ばバスバーと同金属系の金属薄板などバスバーの線膨張
係数と近いかまたは同一の線膨張係数を有すれば適宜材
料成分を変更することができる。また、第3および第4
の実施例では、上側凸部や下側凸部がそれぞれ4角形を
描くように形成したが、そのほか略円形を描くようにし
たり、平面形状については種々の変形例が可能である。
また、各実施例はインバータ回路の実装ユニットに適用
した例を示したが、このほか本発明は金属電極板に半導
体チップを半田で接合する種々の実装ユニットに適用す
ることができる。
In each embodiment, the material of the thin metal plate is the same as that of the bus bar 1. However, the present invention is not limited to this. For example, the coefficient of linear expansion of the bus bar is the same as or the same as that of the bus bar. As long as the material has a linear expansion coefficient, the material components can be changed as appropriate. In addition, the third and fourth
In the embodiment, the upper convex portion and the lower convex portion are each formed so as to draw a quadrangle, but other than that, a substantially circular shape can be drawn, and various modifications can be made to the planar shape.
In addition, although each embodiment shows an example in which the present invention is applied to a mounting unit of an inverter circuit, the present invention can be applied to various mounting units in which a semiconductor chip is joined to a metal electrode plate by soldering.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例を示す上面図である。FIG. 1 is a top view showing a first embodiment of the present invention.

【図2】図1におけるA−A部断面図である。FIG. 2 is a sectional view taken along the line AA in FIG.

【図3】実施例におけるバスバーの位置関係を示す斜視
図である。
FIG. 3 is a perspective view showing a positional relationship of a bus bar in the embodiment.

【図4】実施例を適用したインバータの1相分の回路図
である。
FIG. 4 is a circuit diagram of one phase of an inverter to which the embodiment is applied.

【図5】半導体チップの接合部を拡大して示す断面図で
ある。
FIG. 5 is an enlarged cross-sectional view showing a bonding portion of a semiconductor chip.

【図6】金属材料とシリコンの特性を示す図である。FIG. 6 is a diagram showing characteristics of a metal material and silicon.

【図7】第2の実施例を示す接合部の断面図である。FIG. 7 is a cross-sectional view of a joint showing a second embodiment.

【図8】第2の実施例における金属薄板の詳細を示す図
である。
FIG. 8 is a view showing details of a metal thin plate in the second embodiment.

【図9】第3の実施例を示す接合部の断面図である。FIG. 9 is a cross-sectional view of a joint showing a third embodiment.

【図10】第3の実施例における金属薄板の詳細を示す
図である。
FIG. 10 is a diagram showing details of a thin metal plate in a third embodiment.

【図11】第4の実施例における金属薄板を示す図であ
る。
FIG. 11 is a view showing a metal sheet according to a fourth embodiment.

【図12】第5の実施例における金属薄板を示す図であ
る。
FIG. 12 is a view showing a thin metal plate according to a fifth embodiment.

【図13】従来例を示す図である。FIG. 13 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1、1a、1b バスバー(金属電極板) 1c バスバー 2 樹脂ベース 3、3a、3b 半導体チップ 4a、4b 半田(接合材) 5a、5b、9a、9b 金属ワイヤ 6a、6b ゲート端子 7 放熱シート 8 ヒートシンク 10、10A、10B、10C、10D 金属薄板 11、13、15、17 上側凸部 12、14、16、18 下側凸部 15a 頂部 15b 脚部 20 接合部 100 実装ユニット 1, 1a, 1b Bus bar (metal electrode plate) 1c Bus bar 2 Resin base 3, 3a, 3b Semiconductor chip 4a, 4b Solder (joining material) 5a, 5b, 9a, 9b Metal wire 6a, 6b Gate terminal 7 Heat dissipation sheet 8 Heat sink 10, 10A, 10B, 10C, 10D Metal sheet 11, 13, 15, 17 Upper convex part 12, 14, 16, 18 Lower convex part 15a Top part 15b Leg part 20 Joint part 100 Mounting unit

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップを金属電極板に装着する半
導体実装構造であって、半導体チップと金属電極板の間
に、該金属電極板より板厚が薄くかつ半導体チップより
も金属電極板に近いかまたは金属電極板と同一の線膨張
係数を有する金属薄板を配置するとともに、前記金属電
極板と金属薄板の間および前記半導体チップと金属薄板
の間を接合材で接合したことを特徴とする半導体実装構
造。
1. A semiconductor mounting structure in which a semiconductor chip is mounted on a metal electrode plate, wherein between the semiconductor chip and the metal electrode plate, the thickness is smaller than the metal electrode plate and closer to or closer to the metal electrode plate than the semiconductor chip. A semiconductor mounting structure, wherein a metal thin plate having the same linear expansion coefficient as the metal electrode plate is arranged, and the metal electrode plate and the metal thin plate and the semiconductor chip and the metal thin plate are bonded with a bonding material. .
【請求項2】 前記金属薄板には、前記半導体チップ側
に突出する上側凸部と、前記金属電極板側に突出する下
側凸部とが形成されており、前記上側凸部の頂部が半導
体チップに接し、前記下側凸部が金属電極板に接してい
ることを特徴とする請求項1記載の半導体実装構造。
2. The metal thin plate has an upper convex portion protruding toward the semiconductor chip and a lower convex portion protruding toward the metal electrode plate, and a top of the upper convex portion is formed of a semiconductor. 2. The semiconductor mounting structure according to claim 1, wherein said lower convex portion is in contact with a chip, and said lower convex portion is in contact with a metal electrode plate.
【請求項3】 前記上側凸部と下側凸部とが、それぞれ
半導体チップの周辺輪郭線の内側に位置させて形成され
ていることを特徴とする請求項2記載の半導体実装構
造。
3. The semiconductor mounting structure according to claim 2, wherein the upper convex portion and the lower convex portion are formed so as to be located inside a peripheral contour of the semiconductor chip.
【請求項4】 前記金属薄板の下側凸部がビード状で、
前記半導体チップの周辺輪郭線上に重なる位置に形成さ
れ、前記上側凸部が前記下側凸部より内側に形成されて
いることを特徴とする請求項2記載の半導体実装構造。
4. A lower convex portion of the thin metal plate has a bead shape,
3. The semiconductor mounting structure according to claim 2, wherein the semiconductor chip is formed at a position overlapping on a peripheral contour line of the semiconductor chip, and the upper convex portion is formed inside the lower convex portion.
【請求項5】 前記下側凸部が、四角形状の平面形をな
すように前記半導体チップの周辺輪郭線にそって連続し
ていることを特徴とする請求項4記載の半導体実装構
造。
5. The semiconductor mounting structure according to claim 4, wherein the lower convex portion is continuous along a peripheral contour of the semiconductor chip so as to form a quadrangular planar shape.
【請求項6】 前記上側凸部が前記金属薄板の辺縁まで
延びる脚部を含むことを特徴とする請求項4記載の半導
体実装構造。
6. The semiconductor mounting structure according to claim 4, wherein said upper convex portion includes a leg portion extending to an edge of said metal sheet.
【請求項7】 前記金属薄板の上側凸部がビード状で、
前記半導体チップの周辺輪郭線の内側から金属薄板の辺
縁まで延び、前記下側凸部がビード状で、前記半導体チ
ップの周辺輪郭線の内側から金属薄板の対角線上を当該
金属薄板の角部まで延びていることを特徴とする請求項
2記載の半導体実装構造。
7. An upper convex portion of the thin metal plate has a bead shape,
The corner of the metal sheet extends from inside the peripheral contour of the semiconductor chip to the edge of the metal sheet, the lower convex portion has a bead shape, and diagonally on the diagonal line of the metal sheet from the inside of the peripheral contour of the semiconductor chip. The semiconductor mounting structure according to claim 2, wherein the semiconductor mounting structure extends to at least one of the plurality of semiconductor devices.
【請求項8】 前記金属電極板が銅またはアルミニウム
あるいはこれらを含む合金からなり、金属薄板が金属電
極板と同金属系の材料からなることを特徴とする請求項
1、2、3、4、5、6または7記載の半導体実装構
造。
8. The method according to claim 1, wherein the metal electrode plate is made of copper or aluminum or an alloy containing them, and the thin metal plate is made of the same metal material as the metal electrode plate. 8. The semiconductor mounting structure according to 5, 6, or 7.
JP2001006577A 2001-01-15 2001-01-15 Semiconductor mounting structure Withdrawn JP2002217364A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

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Publication Number Publication Date
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Country Link
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