JP4810898B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4810898B2
JP4810898B2 JP2005189112A JP2005189112A JP4810898B2 JP 4810898 B2 JP4810898 B2 JP 4810898B2 JP 2005189112 A JP2005189112 A JP 2005189112A JP 2005189112 A JP2005189112 A JP 2005189112A JP 4810898 B2 JP4810898 B2 JP 4810898B2
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main surface
conductor pattern
pattern
insulating substrate
insulating layer
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JP2007012726A (en
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祐二 飯塚
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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Description

本発明は、インバータ装置などに適用するパワー半導体モジュール、例えばＩＧＢＴモジュールを対象とした半導体装置のパッケージ構造に関する。   The present invention relates to a package structure of a semiconductor device intended for a power semiconductor module applied to an inverter device or the like, for example, an IGBT module.

近年、頭記のインバータ装置は産業用から家電製品まで適用範囲が拡大しており、これに伴うパワー半導体モジュールの小形化，高信頼性の要求に対応するために、放熱性の高いパッケージの開発が重要課題となっている。
ここで、パワー半導体モジュールの一般的なパッケージ構造を図５に示す。図において、１はモジュールの支持板を兼ねた放熱用金属ベース、２はアルミナなどのセラミック板３の表，裏両面に導体パターン（銅箔）４，５を形成して前記金属ベース１に載置接合した絶縁基板（例えばDirect Copper Bonding基板）、６は絶縁基板２の主面側に形成した導体パターン(回路パターン)４にマウントした半導体チップ（例えばＩＧＢＴ(Insulated Gate-Bipolar Transistor)）、７は半導体チップ６の上面側電極（エミッタ，ゲート）とこれに対応する主面側の回路パターンとの間に配線したワイヤリード、８は外囲樹脂ケース、９はヒートシンク（放熱フィン）であり、通電に伴い半導体チップ６に生じた発熱は絶縁基板２，金属ベース１を伝熱経路としてヒートシンク９に伝熱して系外に放熱される。 In recent years, the application range of the inverter devices described above has expanded from industrial to household appliances, and in order to meet the demands for miniaturization and high reliability of power semiconductor modules, the development of packages with high heat dissipation has been developed. Has become an important issue.
Here, a general package structure of the power semiconductor module is shown in FIG. In the figure, 1 is a heat radiating metal base that also serves as a module support plate, 2 is a conductor plate (copper foil) 4, 5 formed on the front and back surfaces of a ceramic plate 3 such as alumina, and is mounted on the metal base 1. Insulating substrate (for example, Direct Copper Bonding substrate), 6 is a semiconductor chip (for example, IGBT (Insulated Gate-Bipolar Transistor)) mounted on a conductor pattern (circuit pattern) 4 formed on the main surface side of insulating substrate 2, 7 Is a wire lead wired between the upper surface side electrode (emitter, gate) of the semiconductor chip 6 and the corresponding circuit pattern on the main surface side, 8 is an enclosing resin case, 9 is a heat sink (radiation fin), The heat generated in the semiconductor chip 6 due to energization is transferred to the heat sink 9 through the insulating substrate 2 and the metal base 1 as a heat transfer path, and is dissipated outside the system.

一方、上記したパワー半導体モジュールの絶縁基板２に関して、絶縁基板２の熱抵抗を低めてパッケージの放熱性を向上するために、金属に比べて伝熱性の低いセラミック板３の厚みを薄くし、逆に導体パターン４，５の銅箔を厚くして半導体チップ６の発生熱流束を絶縁基板２の面方向に分散させ、セラミック板３の単位面積当たりの熱流束を低めて熱抵抗を低減させるようにした絶縁基板が提唱され、その開発が進められている（例えば、非特許文献１参照）。
西村,望月,高橋,「新絶縁基板を用いた次世代ＩＧＢＴモジュール技術」,富士時報,富士電機ホールディングス株式会社,平成１６年９月１０日，第７７巻，第５号，ｐ．３２１−３２５ On the other hand, with respect to the insulating substrate 2 of the power semiconductor module described above, in order to reduce the thermal resistance of the insulating substrate 2 and improve the heat dissipation of the package, the thickness of the ceramic plate 3 having a lower heat conductivity than metal is reduced. The copper foils of the conductor patterns 4 and 5 are thickened to disperse the heat flux generated by the semiconductor chip 6 in the plane direction of the insulating substrate 2 so as to reduce the heat flux per unit area of the ceramic plate 3 and reduce the thermal resistance. An insulating substrate is proposed and is being developed (see, for example, Non-Patent Document 1).
Nishimura, Mochizuki, Takahashi, “Next Generation IGBT Module Technology Using New Insulating Substrate”, Fuji Time Report, Fuji Electric Holdings Co., Ltd., September 10, 2004, Vol. 77, No. 5, p. 321-325

ところで、前述の絶縁基板（非特許文献１参照）について、熱抵抗の低減効果を有効に発揮させるには、絶縁基板の導体パターンについて次記のような設計上の配慮が必要である。すなわち、絶縁基板２の主面側に形成した導体パターン４については、半導体チップ６をマウントするパターン面域がチップを中心としてその周囲に広がる広い投影面積を確保することが必要であり、このパターンの投影面積が小さく、またパターンが分断していたりパターンの輪郭が複雑に入り組んだりしていると、半導体チップから生じた熱流束の面方向への広がりが制限され、結果として導体パターンの厚みを厚くしたことによる熱抵抗化の低減効果が十分に発揮できなくなる。
これに対し、現状では半導体モジュールのパッケージ小形化の要求から絶縁基板の外形サイズが制約されることに加えて、従来構造の絶縁基板は主面側の導体パターン４が、半導体チップ６をマウントするパターンとワイヤ７を接続するパターンとに分けてセラミック板３の面上に分散形成されていることから、半導体チップに生じた熱流束の面方向への広がりが制限を受けるようになる。 By the way, for the above-described insulating substrate (see Non-Patent Document 1), in order to effectively exhibit the effect of reducing the thermal resistance, the following design considerations are necessary for the conductor pattern of the insulating substrate. That is, with respect to the conductor pattern 4 formed on the main surface side of the insulating substrate 2, it is necessary to ensure a wide projected area in which the pattern surface area for mounting the semiconductor chip 6 extends around the chip. If the projected area is small, the pattern is divided, or the outline of the pattern is complicated, the spread of the heat flux generated from the semiconductor chip in the surface direction is restricted, and as a result, the thickness of the conductor pattern is reduced. The effect of reducing thermal resistance due to the increase in thickness cannot be sufficiently exhibited.
On the other hand, at present, in addition to the limitation of the outer size of the insulating substrate due to the demand for downsizing of the package of the semiconductor module, in the conventional insulating substrate, the conductor pattern 4 on the main surface side mounts the semiconductor chip 6. Since the pattern and the pattern for connecting the wire 7 are divided and formed on the surface of the ceramic plate 3, the spread of the heat flux generated in the semiconductor chip in the surface direction is restricted.

すなわち、図６（ａ）は２素子組のＩＧＢＴモジュールを例にした従来の組立構造図、図６（ｂ）はその等価回路図であり、６ａはＩＧＢＴ、６ｂはＦＷＤ（Free Wheeling Diode）、Ｃ１，Ｃ２Ｅ１，Ｅ２はＩＧＢＴのコレクタ，エミッタに対応する主回路端子、Ｇ１，Ｇ２はゲート端子の記号を表し、上アームのＩＧＢＴと下アームのＩＧＢＴが図示の導体パターン，ワイヤリードを介して直列に接続されている。なお、１０は外部端子であり、該端子は図４に示した外囲ケース８にインサート成形してケースから外部に引き出すようにしている。
ここで、絶縁基板２の主面側に形成した導体パターンは、図示のように上アームと下アームのＩＧＢＴ６ａ，ＦＷＤ６ｂを組別に分けてマウントするパターン４ａ，４ｂと、前記の各端子に対応するリード接続用の配線用パターン４ｃ，４ｄ，４ｅと切り離してセラミック板３の面上にパターン形成されている。 6A is a conventional assembly structure example of a 2-element IGBT module, FIG. 6B is an equivalent circuit diagram thereof, 6a is an IGBT, 6b is an FWD (Free Wheeling Diode), C1, C2E1 and E2 are main circuit terminals corresponding to the collector and emitter of the IGBT, G1 and G2 represent symbols of the gate terminal, and the upper arm IGBT and the lower arm IGBT are connected in series via the illustrated conductor pattern and wire lead. It is connected to the. Reference numeral 10 denotes an external terminal, which is insert-molded into the outer case 8 shown in FIG. 4 and pulled out from the case.
Here, the conductor pattern formed on the main surface side of the insulating substrate 2 corresponds to the patterns 4a and 4b for mounting the upper arm and the lower arm IGBT 6a and FWD 6b separately as shown in the drawing, and the above-described terminals. A pattern is formed on the surface of the ceramic plate 3 separately from the wiring patterns 4c, 4d, and 4e for lead connection.

図６（ａ）から判るように、従来の絶縁基板２ではその主面側の導体パターンが複数のパターン４ａ〜４ｅに分けてセラミック板３の面上に分断形成されており、特にＩＧＢＴ６ａ，ＦＷＤ６ｂの半導体チップをマウントするパターン４ａ，４ｂについて見ると、ワイヤリード７の配線経路との関連付けからパターン輪郭が入り組んだ形状になっており、また下アームのパターン４ｂには上アームのパターン４ａの側方に向けて延在する狭隘なパターン部を形成し、ここに上アームのＩＧＢＴ，ＦＷＤの上面電極から引き出したリードワイヤ７を接続して上アームと下アームの回路を直列接続するようにしている。
このために、半導体チップ（ＩＧＢＴ６ａ，ＦＷＤ６ｂ）からの熱流束は、パターン４ａ，４ｂの投影面積，輪郭形状に規制されて絶縁基板２の面方向へ十分に広がることができず、このままでは非特許文献１に述べられている熱抵抗の低減，熱放散性の向上効果を十分に発揮させることが困難となる。 As can be seen from FIG. 6A, in the conventional insulating substrate 2, the conductor pattern on the main surface side is divided into a plurality of patterns 4a to 4e and divided on the surface of the ceramic plate 3, and particularly, the IGBT 6a, FWD 6b. When the patterns 4a and 4b for mounting the semiconductor chip are seen, the pattern outline is intricately associated with the wiring path of the wire lead 7, and the lower arm pattern 4b is on the side of the upper arm pattern 4a. A narrow pattern portion extending toward the direction is formed, and a lead wire 7 drawn from the upper electrode of the upper arm IGBT and FWD is connected to the upper arm and the lower arm circuit in series. Yes.
For this reason, the heat flux from the semiconductor chip (IGBT 6a, FWD 6b) is restricted by the projected area and contour shape of the patterns 4a, 4b and cannot sufficiently spread in the surface direction of the insulating substrate 2, and is not patented as it is. It becomes difficult to fully exhibit the effects of reducing thermal resistance and improving heat dissipation described in Document 1.

本発明は上記の点に鑑みなされたものであり、半導体チップをマウントした絶縁基板について、その主面側に形成した導体パターンの構築に工夫の手を加えることにより、絶縁基板の熱抵抗低減，放熱性向上と併せて、パッケージのコンパクト化が図れるように改良した半導体装置を提供することを目的とする。   The present invention has been made in view of the above points, and for the insulating substrate on which the semiconductor chip is mounted, the heat resistance of the insulating substrate can be reduced by contriving the construction of the conductor pattern formed on the main surface side thereof. An object of the present invention is to provide an improved semiconductor device so that the package can be made compact together with the improvement of heat dissipation.

上記目的を達成するために、本発明によれば、半導体チップがマウントされた主面導体パターンを有する絶縁基板と、前記半導体チップの上面電極とリード配線されている、前記主面導体パターン上に絶縁層を介して層設された複数の配線用パターンと、を備え、全ての前記配線用パターンが、それぞれセラミック絶縁層の上面に形成され、該セラミック絶縁層のメタライズされた裏面を前記主面導体パターンにろう付けして層設されていることを特徴とする半導体装置とし（請求項１）、具体的には次記のような態様で構成することができる。
（１）前記各項の半導体装置において、前記主面導体パターンと導電接続する配線用パターンは、その絶縁層に形成したスルーホールを介して前記主面導体パターンに接続されている（請求項２）。
また、本発明によれば、セラミック基板の両面に、このセラミック基板より厚い主面導体パターンおよび導体パターンが形成されてなり、この主面導体パターンにＩＧＢＴがマウントされた絶縁基板と、前記ＩＧＢＴの上面電極とリード配線されている、前記主面導体パターン上に絶縁層を介して層設された複数の配線用パターンと、を備え、全ての前記配線用パターンが前記主面導体パターン上に層設されていることを特徴とする半導体装置とする（請求項３）。 To achieve the above object, according to the present invention, an insulating substrate having a main surface conductor pattern on which a semiconductor chip is mounted, and an upper surface electrode of the semiconductor chip are lead-wired on the main surface conductor pattern. A plurality of wiring patterns arranged via an insulating layer, and all the wiring patterns are respectively formed on the upper surface of the ceramic insulating layer, and the metallized back surface of the ceramic insulating layer is the main surface. The semiconductor device is characterized in that it is formed by brazing the conductor pattern (claim 1). Specifically, it can be configured in the following manner.
(1) In the semiconductor device of each of the above items, the wiring pattern conductively connected to the main surface conductor pattern is connected to the main surface conductor pattern through a through hole formed in the insulating layer. ).
Further, according to the present invention, a main surface conductor pattern and a conductor pattern thicker than the ceramic substrate are formed on both surfaces of the ceramic substrate, and the IGBT is mounted on the main surface conductor pattern; A plurality of wiring patterns layered on the main surface conductor pattern via an insulating layer, wherein all the wiring patterns are layered on the main surface conductor pattern. A semiconductor device is provided (claim 3).

上記の構成によれば、半導体チップをマウントする絶縁基板の主面導体パターンは、配線用パターンに制約されることなく、基板上の面域を最大に使ってパターン形成できる。これにより、主面導体パターンの投影面積を拡大して半導体チップからの熱流束を基板の面方向へ十分に分散させて絶縁基板の熱抵抗低減、放熱性の向上が図れる。
また、配線用パターンはセラミック絶縁層を介して絶縁基板の主面側に層設することで、そのセラミック絶縁層が補強材の役目を果たして絶縁基板の剛性，強度を高めることができてパッケージの信頼性が向上する。
加えて、前記の絶縁層を噴射成膜法（エアロゾルデポジッション法）により形成することで、基板との一体性を高めて信頼性，放熱性がより一層向上する。
さらに、前記の配線用パターンを導体箔として絶縁層の上面からはみ出すように延長して形成し、この延長部分を外部端子として使用するようにしたことで、外囲ケースの外部端子が不要となって部品点数の削減とともに、パッケージをコンパクトに構成できる。 According to said structure, the main surface conductor pattern of the insulated substrate which mounts a semiconductor chip can be pattern-formed using the maximum surface area on a board | substrate, without being restrict | limited to the pattern for wiring. As a result, the projected area of the main surface conductor pattern can be enlarged and the heat flux from the semiconductor chip can be sufficiently dispersed in the surface direction of the substrate to reduce the thermal resistance of the insulating substrate and improve the heat dissipation.
In addition, the wiring pattern is layered on the main surface side of the insulating substrate via the ceramic insulating layer, so that the ceramic insulating layer can serve as a reinforcing material to increase the rigidity and strength of the insulating substrate. Reliability is improved.
In addition, by forming the insulating layer by a spray film formation method (aerosol deposition method), the integrity with the substrate is improved, and the reliability and heat dissipation are further improved.
Furthermore, the wiring pattern is extended as a conductive foil so as to protrude from the upper surface of the insulating layer, and this extended portion is used as an external terminal, so that the external terminal of the outer case is not required. As a result, the number of parts can be reduced and the package can be made compact.

以下、本発明の実施の形態を、図１，図２，図３に示した２素子組ＩＧＢＴモジュールの実施例、および図４に示した最小構成の半導体装置の実施例に基づいて説明する。なお、図示の各実施例において、図５，図６（ａ）に対応する部材には同じ符号を付してその説明は省略する。また、図１〜図４において、（ａ）は平面図、（ｂ）は（ａ）のＸ−Ｘ断面図である。   Hereinafter, embodiments of the present invention will be described based on the example of the two-element set IGBT module shown in FIG. 1, FIG. 2, and FIG. 3, and the example of the semiconductor device having the minimum configuration shown in FIG. In the illustrated embodiments, members corresponding to those in FIGS. 5 and 6A are denoted by the same reference numerals and description thereof is omitted. Moreover, in FIGS. 1-4, (a) is a top view, (b) is XX sectional drawing of (a).

図１（ａ），（ｂ）において、絶縁基板２に対してその主面側にはセラミック板３の面域を略二分するように主面導体パターン（銅箔）４ａ，４ｂが形成され、各導体パターン４ａ，４ｂの中央には図６（ｂ）の上アーム，下アームに対応するＩＧＢＴ６ａ，ＦＷＤ６ｂの半導体チップがマウントされている。また、導体パターン４ａ，４ｂの周縁部には前記半導体チップの上面電極（ＩＧＢＴのエミッタ，ゲート電極、ＦＷＤのカソード電極）に対応する配線用パターン４ｃ〜４ｆがセラミック絶縁層１１を介して２階建て式に層設されている。なお、図示の配線用パターン４ｃ〜４ｅは図６（ａ）における各配線用パターンに対応し、配線用パターン４ｆは図６（ａ）における導体パターン４ｂの狭隘延長部に対応しており、各配線用パターンと半導体チップの上面電極との間にワイヤリード７を配線するようにしている。   1A and 1B, main surface conductor patterns (copper foils) 4a and 4b are formed on the main surface side of the insulating substrate 2 so as to bisect the surface area of the ceramic plate 3, In the center of each of the conductor patterns 4a and 4b, semiconductor chips of IGBTs 6a and FWD6b corresponding to the upper arm and the lower arm of FIG. 6B are mounted. Further, wiring patterns 4c to 4f corresponding to the upper surface electrodes (IGBT emitter, gate electrode, FWD cathode electrode) of the semiconductor chip are arranged on the second floor through the ceramic insulating layer 11 at the peripheral portions of the conductor patterns 4a, 4b. It is layered in a building style. The illustrated wiring patterns 4c to 4e correspond to the wiring patterns in FIG. 6A, the wiring pattern 4f corresponds to the narrow extension of the conductor pattern 4b in FIG. Wire leads 7 are arranged between the wiring pattern and the upper surface electrode of the semiconductor chip.

上記のように配線用パターン４ｃ〜４ｆを、半導体チップをマウントする絶縁基板２の主面導体パターン４ａ，４ｂの上に層設することにより、主面導体パターン４ａ，４ｂは、配線用パターン４ｃ〜４ｆに制約されることなく、セラミック板３の面域を最大に使って形成できる。これにより、先記の非特許文献１で開示されているように、主面導体パターンの投影面積を拡大して半導体チップからの熱流束を面方向に十分分散させて絶縁基板の熱抵抗を低減し、パッケージの熱放散性を向上できる。
ここで、前記の配線用パターン４ｃ〜４ｅは、絶縁基板２と同様な工法でセラミック絶縁層１１の上面にあらかじめ成膜しておき、このセラミック絶縁層１１を半導体モジュールの組立工程に合わせて次記のような接合方法で絶縁基板２の主面に層設することができる。すなわち、セラミック絶縁層１１の裏面には、あらかじめ絶縁基板２の裏面側導体パターン５と同様な工法で銅箔を成膜するか、もしくはメタライズしておき、絶縁基板２の主面に半導体チップをマウントする工程で、同時にセラミック絶縁層１１をろう付けする。あるいは、絶縁基板２の製造工程でセラミック絶縁層１１を接合する。 By arranging the wiring patterns 4c to 4f on the main surface conductor patterns 4a and 4b of the insulating substrate 2 on which the semiconductor chip is mounted as described above, the main surface conductor patterns 4a and 4b become the wiring pattern 4c. The surface area of the ceramic plate 3 can be maximized without being limited to ˜4f. As a result, as disclosed in the aforementioned Non-Patent Document 1, the projected area of the main surface conductor pattern is enlarged to sufficiently disperse the heat flux from the semiconductor chip in the surface direction, thereby reducing the thermal resistance of the insulating substrate. In addition, the heat dissipation of the package can be improved.
Here, the wiring patterns 4c to 4e are formed in advance on the upper surface of the ceramic insulating layer 11 by a method similar to that for the insulating substrate 2, and the ceramic insulating layer 11 is next processed according to the assembly process of the semiconductor module. A layer can be formed on the main surface of the insulating substrate 2 by the bonding method described above. That is, on the back surface of the ceramic insulating layer 11, a copper foil is formed in advance by the same method as the back surface side conductor pattern 5 of the insulating substrate 2 or metallized, and a semiconductor chip is placed on the main surface of the insulating substrate 2. In the mounting step, the ceramic insulating layer 11 is simultaneously brazed. Alternatively, the ceramic insulating layer 11 is bonded in the manufacturing process of the insulating substrate 2.

また、前記工法とは別に、セラミック層１１を接着剤（熱硬化性）で絶縁基板２の主面に固着することも可能である。さらに、絶縁基板２主面に微細粒子化したセラミック粉末を常温下で噴射する噴射成膜法（エアロゾルデポジッション法）によりセラミック絶縁層１１を成膜した上で、このセラミック絶縁層１１の上面にウエット処理によるメタルコーティングを施して配線用パターン４ａ〜４ｆを形成する方法もある。なお、この噴射成膜法は先記のろう付け法に比べて絶縁基板２に熱履歴が作用することもなく、かつ絶縁基板との一体性を高めることができて高信頼性の確保に有利な工法と言える。
また、図１に戻って、図示実施例では配線用パターン４ｆをセラミック絶縁層１１とともに主面導体パターン４ａと４ｂの間に跨がって層設した上で、セラミック絶縁層１１に形成したスルーホール１２を介して配線用パターン４ｆを下アーム（図６（ｂ）の等価回路参照）に対応する主面導体パターン４ｂに導電接続するようにしている。 In addition to the construction method, the ceramic layer 11 can be fixed to the main surface of the insulating substrate 2 with an adhesive (thermosetting). Further, after the ceramic insulating layer 11 is formed on the main surface of the insulating substrate 2 by a spray film forming method (aerosol deposition method) in which finely divided ceramic powder is injected at room temperature, the upper surface of the ceramic insulating layer 11 is formed. There is also a method of forming the wiring patterns 4a to 4f by performing metal coating by wet processing. This spray film formation method is advantageous in ensuring high reliability because the thermal history does not act on the insulating substrate 2 and the integrity with the insulating substrate can be improved as compared with the brazing method described above. It can be said that it is a simple construction method.
Returning to FIG. 1, in the illustrated embodiment, the wiring pattern 4 f is layered between the main surface conductor patterns 4 a and 4 b together with the ceramic insulating layer 11, and then the through pattern formed in the ceramic insulating layer 11. The wiring pattern 4f is conductively connected to the main surface conductor pattern 4b corresponding to the lower arm (see the equivalent circuit of FIG. 6B) through the hole 12.

そして、前記の絶縁基板２の主面導体パターン４ａ，４ｂにマウントしたＩＧＢＴ６ａ，ＦＷＤ６ｂの各半導体チップの上面電極と配線用パターン４ｃ〜４ｆとの間にワイヤリード７を図示のように配線し、続く工程では図５のように絶縁基板２を放熱用金属ベース１に載置接合し、さらに外囲ケース８を組み付けた上で、絶縁基板２の各パターン２ａ〜２ｅを外部端子１０に配線し、最後に外囲ケース８の内部を樹脂封止して半導体モジュールが完成する。   Then, wire leads 7 are wired between the upper surface electrodes of the semiconductor chips of the IGBTs 6a and FWD6b mounted on the main surface conductor patterns 4a and 4b of the insulating substrate 2 and the wiring patterns 4c to 4f as shown in the figure. In the subsequent process, the insulating substrate 2 is placed and bonded to the heat radiating metal base 1 as shown in FIG. 5, and the outer casing 8 is assembled. Finally, the inside of the outer casing 8 is sealed with resin to complete the semiconductor module.

参考例１Reference example 1

次に、先記実施例１の参考例を図２（ａ），（ｂ）に示す。すなわち、図１の実施例では、配線用パターン２ｆと主面導体パターン４ｂとの導電接続手段として、配線用パターン２ｆのセラミック絶縁層１１にスルーホール１２を設けているのに対して、この参考例ではリボン状のリード（銅箔）１３を採用し、該リードの両端を配線用パターン４ｆ，主面導体パターン４ｂに超音波接合して図６（ｂ）の等価回路に示した上アームと下アームとの間を直列接続するようにしている。   Next, a reference example of the first embodiment is shown in FIGS. That is, in the embodiment of FIG. 1, the through hole 12 is provided in the ceramic insulating layer 11 of the wiring pattern 2f as a conductive connection means between the wiring pattern 2f and the main surface conductor pattern 4b. In the example, a ribbon-like lead (copper foil) 13 is employed, and both ends of the lead are ultrasonically joined to the wiring pattern 4f and the main surface conductor pattern 4b, and the upper arm shown in the equivalent circuit of FIG. The lower arm is connected in series.

参考例２Reference example 2

図３（ａ），（ｂ）は本発明の参考例を示すものである。この参考例はパッケージのコンパクト化，外部端子の部品削減化を狙いに、絶縁層１１の上面に形成して絶縁基板２の周縁部分に層設した配線用パターン４ｃ，４ｄ，４ｅについて、そのパターンを導体箔（銅，アルミ箔）として絶縁層１１の上面から側方にはみ出すように延長して形成する（図中の配線用パターン４ｄ参照）。そして、モジュールの組立工程では絶縁層１１から側方に延在する延長部分を絶縁基板２の輪郭に合わせて上方に起立させるように直角に折り曲げた上で、その先端部を外囲ケース８（図５参照）から外方に突き出して樹脂封止し、その導体箔を外部端子（Ｇ１，Ｇ２，Ｅ２）として使用するようにする。なお、この実施例では、主面導体パターン４ａ，４ｂのから引き出した外部端子（Ｃ１，Ｃ２Ｅ１）についても、前記と同様な箔状の延長部分を形成しておき、この延長部を起立させて外部端子として使用するようにしている。   3 (a) and 3 (b) show a reference example of the present invention. In this reference example, the wiring patterns 4c, 4d, and 4e formed on the upper surface of the insulating layer 11 and layered on the peripheral portion of the insulating substrate 2 with the aim of reducing the size of the package and reducing the number of external terminal components. Is extended as a conductor foil (copper, aluminum foil) so as to protrude laterally from the upper surface of the insulating layer 11 (see the wiring pattern 4d in the figure). Then, in the module assembling process, the extended portion extending laterally from the insulating layer 11 is bent at a right angle so as to rise upward in accordance with the contour of the insulating substrate 2, and the front end portion of the outer casing 8 ( The outer surface of the conductive foil is sealed with resin, and the conductive foil is used as external terminals (G1, G2, E2). In this embodiment, the external terminals (C1, C2E1) drawn out from the main surface conductor patterns 4a, 4b are also formed with the same foil-shaped extension as described above, and the extension is raised. It is used as an external terminal.

これにより、外囲ケースにインサート成形する外部端子が不要となり、その分だけ部品点数の削減，パッケージの小形，コンパクト化が図れる。   This eliminates the need for an external terminal to be insert-molded in the outer case, thereby reducing the number of parts, making the package smaller and more compact.

次に、絶縁基板に１個の半導体チップをマウントした最小構成の半導体装置についての実施例を図４に示す。
図４（ａ），（ｂ）において、絶縁基板２に対してその主面側にはセラミック基板３の面域に主面導体パターン（銅箔）４ａが形成され、その導体パターン４ａの中央には半導体チップとしてＩＧＢＴ６ａがマウントされている。また、導体パターン４ａの周縁部には半導体チップの上面電極（半導体チップがＩＧＢＴの場合はエミッタ電極，ゲート電極、半導体チップがＦＷＤである場合にはカソード）に対応する配線用パターン４ｄ，４ｅがセラミック絶縁層１１を介して層設されている。ここで、配線用パターン４ｄ，４ｅはＩＧＢＴ６ａを中央にしてその左右両側に対向する辺に振り分けて平行に設けられており、外部端子１０（Ｅ，Ｃ，Ｇ）は配線用パターン４ｄ，４ｅのパターンエンドと対向する絶縁基板２の上辺側に一列に並べて設けられている。そして、各配線用パターン４ｄ，４ｅとＩＧＢＴ６ａの上面電極（エミッタ電極，ゲート電極）との間にワイヤリード７を配線している。 Next, FIG. 4 shows an embodiment of a semiconductor device having a minimum configuration in which one semiconductor chip is mounted on an insulating substrate.
4 (a) and 4 (b), a main surface conductor pattern (copper foil) 4a is formed in the surface area of the ceramic substrate 3 on the main surface side of the insulating substrate 2, and at the center of the conductor pattern 4a. IGBT 6a is mounted as a semiconductor chip. Further, wiring patterns 4d and 4e corresponding to the upper surface electrode of the semiconductor chip (emitter electrode and gate electrode when the semiconductor chip is IGBT, and cathode when the semiconductor chip is FWD) are provided on the periphery of the conductor pattern 4a. Layered with a ceramic insulating layer 11. Here, the wiring patterns 4d and 4e are provided in parallel by being distributed to the sides facing the left and right sides with the IGBT 6a in the center, and the external terminals 10 (E, C, G) are provided on the wiring patterns 4d and 4e. They are arranged in a line on the upper side of the insulating substrate 2 facing the pattern end. A wire lead 7 is wired between the wiring patterns 4d, 4e and the upper surface electrode (emitter electrode, gate electrode) of the IGBT 6a.

上記のように構成することで、先記の実施例１と同様に、主面導体パターン４ａの投影面積を拡大して半導体チップからの熱流束を面方向に十分分散させて絶縁基板２の熱抵抗を低減し、パッケージの熱放散性を向上させることができる。
なお、配線用パターン４ｄ，４ｅの形成方法，および外囲ケース８（図５参照）への組み付け等については実施例１と同様であって説明を省略する。また、配線用パターン４ｄ，４ｅを実施例３と同様に導体箔（銅箔あるいはアルミ箔）として絶縁層１１の上面から側方へはみ出すように延長して形成し、この導体箔のはみ出し延長部分を上方に起立させて外部端子として使用することも可能である。
また、上述の各実施例は、いずれも図４で述べた構成の半導体モジュール（半導体チップをマウントした絶縁基板２を放熱用金属ベース１に載置）への適用について述べたが、これに限定されるものではなく、例えば半導体チップをリードフレームにマウントしてその周域を樹脂で封止した上で、放熱フィンに直付けするようにした樹脂封止型パッケージに適用しても同様な効果を奏することができる。 With the configuration as described above, as in the first embodiment, the projected area of the main surface conductor pattern 4a is enlarged to sufficiently disperse the heat flux from the semiconductor chip in the surface direction, and the heat of the insulating substrate 2 is increased. Resistance can be reduced and heat dissipation of the package can be improved.
The method for forming the wiring patterns 4d and 4e and the assembly to the outer case 8 (see FIG. 5) are the same as those in the first embodiment, and the description thereof is omitted. Further, the wiring patterns 4d and 4e are formed as conductor foils (copper foil or aluminum foil) so as to protrude from the upper surface of the insulating layer 11 in the same manner as in Example 3, and the protruding portions of the conductor foils are extended. Can be used as an external terminal.
In each of the above-described embodiments, the application to the semiconductor module having the structure described in FIG. 4 (the insulating substrate 2 on which the semiconductor chip is mounted is placed on the metal base 1 for heat dissipation) has been described. However, the present invention is not limited to this. For example, the same effect can be obtained when a semiconductor chip is mounted on a lead frame and its peripheral area is sealed with resin, and then applied to a resin-sealed package that is directly attached to a heat radiating fin. Can be played.

本発明の実施例１に対応する半導体装置の組立構造図で、（ａ）は平面図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図BRIEF DESCRIPTION OF THE DRAWINGS It is an assembly structure figure of the semiconductor device corresponding to Example 1 of this invention, (a) is a top view, (b) is XX sectional drawing of the arrow of (a). 本発明の実施例２に対応する半導体装置の組立構造図で、（ａ）は平面図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図FIG. 6 is an assembly structure diagram of a semiconductor device corresponding to Example 2 of the present invention, where (a) is a plan view and (b) is a cross-sectional view taken along line XX in (a). 本発明の実施例３に対応する半導体装置の組立構造図で、（ａ）は平面図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図FIG. 7 is an assembly structure diagram of a semiconductor device corresponding to Example 3 of the present invention, where (a) is a plan view and (b) is a cross-sectional view taken along line XX in (a). 本発明の実施例４に対応する半導体装置の組立構造図で、（ａ）は平面図、（ｂ）は（ａ）の矢視Ｘ−Ｘ断面図FIG. 6 is an assembly structure diagram of a semiconductor device corresponding to Example 4 of the present invention, where (a) is a plan view and (b) is a cross-sectional view taken along line XX in (a). 従来におけるパワー半導体モジュールの組立構造図Assembly structure diagram of conventional power semiconductor module ２素子組ＩＧＢＴモジュールを例にした従来の半導体装置の組立構造図で、（ａ）はモジュール組立体の平面図、（ｂ）は等価回路図FIG. 2 is an assembly structure diagram of a conventional semiconductor device taking a two-element set IGBT module as an example, where (a) is a plan view of the module assembly and (b) is an equivalent circuit diagram.

１ 放熱用金属ベース
２ 絶縁基板
３ セラミック板
４ 主面側導体パターン
４ａ，４ｂ 主面導体パターン
４ｃ〜４ｆ 配線用パターン
６ 半導体チップ
６ａ ＩＧＢＴ
６ｂ ＦＷＤ
７ リードワイヤ
８ 外囲ケース
１０ 外部端子
１１ セラミック絶縁層
１２ スルーホール
１３ リボン状リード DESCRIPTION OF SYMBOLS 1 Metal base for heat dissipation 2 Insulation board 3 Ceramic board 4 Main surface side conductor pattern 4a, 4b Main surface conductor pattern 4c-4f Wiring pattern 6 Semiconductor chip 6a IGBT
6b FWD
7 Lead wire 8 Enclosing case 10 External terminal 11 Ceramic insulating layer 12 Through hole 13 Ribbon-shaped lead

Claims (3)

半導体チップがマウントされた主面導体パターンを有する絶縁基板と、
前記半導体チップの上面電極とリード配線されている、前記主面導体パターン上に絶縁層を介して層設された複数の配線用パターンと、を備え、
全ての前記配線用パターンが、それぞれセラミック絶縁層の上面に形成され、該セラミック絶縁層のメタライズされた裏面を前記主面導体パターンにろう付けして層設されていることを特徴とする半導体装置。 An insulating substrate having a main surface conductor pattern on which a semiconductor chip is mounted;
A plurality of wiring patterns layered via an insulating layer on the main surface conductor pattern, which is lead-wired to the upper surface electrode of the semiconductor chip ,
All the wiring patterns are formed on the upper surface of the ceramic insulating layer, respectively, and the metallized back surface of the ceramic insulating layer is brazed to the main surface conductor pattern and layered. . 請求項１記載の半導体装置において、前記主面導体パターンと導電接続する配線用パターンは、その絶縁層に形成したスルーホールを介して前記主面導体パターンに接続されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1 , wherein the wiring pattern conductively connected to the main surface conductor pattern is connected to the main surface conductor pattern through a through hole formed in the insulating layer. apparatus. セラミック基板の両面に、このセラミック基板より厚い主面導体パターンおよび導体パターンが形成されてなり、この主面導体パターンにＩＧＢＴがマウントされた絶縁基板と、A main surface conductor pattern and a conductor pattern thicker than the ceramic substrate are formed on both surfaces of the ceramic substrate, and an insulating substrate in which an IGBT is mounted on the main surface conductor pattern;
前記ＩＧＢＴの上面電極とリード配線されている、前記主面導体パターン上に絶縁層を介して層設された複数の配線用パターンと、を備え、A plurality of wiring patterns layered via an insulating layer on the main surface conductor pattern, which is lead-wired to the top surface electrode of the IGBT,
全ての前記配線用パターンが前記主面導体パターン上に層設されていることを特徴とする半導体装置。A semiconductor device, wherein all the wiring patterns are layered on the main surface conductor pattern.
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