WO2013179205A1 - Semiconductor die package - Google Patents

Semiconductor die package Download PDF

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Publication number
WO2013179205A1
WO2013179205A1 PCT/IB2013/054364 IB2013054364W WO2013179205A1 WO 2013179205 A1 WO2013179205 A1 WO 2013179205A1 IB 2013054364 W IB2013054364 W IB 2013054364W WO 2013179205 A1 WO2013179205 A1 WO 2013179205A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
semiconductor die
submount
assembly according
bondwires
Prior art date
Application number
PCT/IB2013/054364
Other languages
French (fr)
Inventor
Lev STESSIN
Gregory Bunin
Original Assignee
Visic Technologies Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Visic Technologies Ltd. filed Critical Visic Technologies Ltd.
Priority to TW102142718A priority Critical patent/TW201445679A/en
Publication of WO2013179205A1 publication Critical patent/WO2013179205A1/en

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Definitions

  • Embodiments of the invention relate to apparatus and methods of electrically connecting a semiconductor die to circuitry with which it is used.
  • Semiconductor devices are typically formed in arrays containing large numbers of the devices on a semiconductor wafer, such as Si, GaAs, or GaN wafer. After formation, the wafer is separated, "diced”, into pieces referred to as “dies”, each of which comprises a single copy of the device.
  • Components of the device such as sources, drains and gates of transistors, comprised in a die that require electrical connection to external circuitry with which the device is to operate are electrically connected to conductive contact pads, also referred to as die pads, that are formed on a surface of the die.
  • semiconductor wafers are relatively expensive, and to reduce costs of semiconductor dies, elements of the devices they contain are typically made as small as possible and positioned close to each other.
  • semiconductor devices in a die contain stacks of very thin layers of semiconductor materials treated with different dopants, and contact pads are usually formed as close as possible, and generally immediately above, active regions of the stacks to which they provide electrical contact.
  • a semiconductor die may be mounted to a submount, and together with the submount be encapsulated in a package by potting or molding in a protective epoxy or plastic.
  • the submount mechanically supports the die and electrically conductive "package leads" that extend from the package, or are otherwise readily accessible from outside the package, which are used to electrically connect the packaged die to an external circuit with which the die is to be used.
  • Conductive wires typically copper (Cu), aluminum (Al), or gold (Au) "bondwires” that may have diameters ranging from about 15 ⁇ (micrometers) to hundreds of ⁇ connect the package leads to the contact die pads on the die.
  • the contact pads in high power field effect transistor (FET) dies that may for example be used as switches in power supply of TVs, uninterrupted power supply (UPS) systems, electric powered vehicles, radar systems, and electric motor controllers, are usually connected to the package leads in the packages that contain them by Al bondwires having diameters between about 300 ⁇ and about 500 ⁇ .
  • the relatively large diameter, robust Al bondwires are advantageous for supporting large currents that may be switched by the dies.
  • large bondwires generally exact a penalty in reduced die lifetime and reliability.
  • Temperature changes in a die during its operation may generate large mechanical stress at a junction between a bondwire and a contact pad of the die as a result of differences in coefficients of thermal expansion (CTE) between material of the bondwire, die, and or/the pad.
  • CTE coefficients of thermal expansion
  • the "CTE" stress increases with increase in area of the junction and as a result with increase in cross section area of the bondwire, and for large bondwires may result in cracking of the die that shortens a useful lifetime of the die.
  • a process referred to as "wedge bonding" is frequently used to connect the Al bondwires to the conductive pads and the package leads.
  • wedge bonding an end of an Al bondwire is pressed to a contact region of a conductive pad or package lead to which it is to be connected simultaneously with application of ultrasonic energy.
  • the ultrasonic energy generates frictional heating at the contact region, and the heating and pressure with which the bondwire is pressed to the contact region welds the bondwire to the contact region.
  • the pads are required to be relatively large to accommodate the large diameter Al bondwires. Distancing the pads from the die's active areas generally entails using an increased amount of expensive area of a wafer to produce the die and incurring an undesirable cost penalty.
  • An aspect of an embodiment of the invention relates to providing a semiconductor die package comprising a die mounted to a submount having a contact pad connected to package leads for electrically connecting the package to an external circuit by a relatively large diameter bondwire.
  • An array of relatively small diameter bondwires electrically connects the contact pad on the submount to a contact pad located on the die.
  • a contact pad on the submount that may be connected to a package lead in accordance with an embodiment of the invention may be referred to as a "submount lead pad”.
  • Bondwires that connect the submount lead pad to a lead may be referred to as “lead bondwires” and bondwires that electrically connect a submount lead pad to a die pad, may be referred to as "die bondwires”.
  • the submount comprises an intermediate conductor that is electrically connected to the submount lead pad, and the die bondwires in the array of die bondwires are connected to the intermediate conductor.
  • the submount comprises a first insulating layer and a second insulating layer stacked over the first layer which sandwich between them the intermediate conductor.
  • the submount lead pad may be formed on a top surface of the second insulating layer and be connected to the intermediate conductor by a via.
  • the submount is formed having a recess into which the die seats.
  • the recess has a bottom formed from a heat and electrically conducting material, such as a metal.
  • all the contact pads comprised in the die that are required for operation of the die are located on a same, "top", surface of the die.
  • the die comprises a FET power transistor.
  • the power transistor is formed from nitride based semiconductor materials, such as GaN (Gallium Nitride) and AlGaN (Aluminum Gallium Nitride).
  • the FET is a high electron mobility transistor "HEMT" transistor.
  • the die comprises a GaN Schottky diode.
  • a semiconductor die assembly comprising: a semiconductor die having die pads for electrically connecting the die to external circuitry; and a submount supporting the die and comprising: a conductor electrically connected to a die pad of the semiconductor die by a plurality of relatively small diameter bondwires; and a submount pad electrically connected to the conductor and having a surface configured to be electrically connected to a relatively large diameter bondwire.
  • the submount is formed having a recess in which the semiconductor die seats.
  • the heat conducting base plate may be electrically conducting.
  • the submount pad and the base plate may be located on a same surface of the submount.
  • the die assembly comprises a layer of insulating material and wherein the submount pad comprises a first electrically conducting layer located on a surface of the insulating layer and the conductor comprises a second electrically conducting layer located on a side of the insulating layer opposite a side of the insulating layer on which the surface is located.
  • the conductor and submount pad are electrically connected by a conductive via.
  • the second conducting layer has an exposed surface located along an edge of the recess.
  • the plurality of bondwires are electrically connected to the exposed surface.
  • each of the relatively small diameter bondwires has a diameter between about 25 ⁇ (micrometers) and about 35 ⁇ .
  • the die assembly may comprise a die package having a package lead electrically connected to the submount pad by a relatively large diameter bondwire.
  • the large diameter bondwire has a diameter equal to about 500 ⁇ .
  • the die is a field effect transistor (FET) power die having a source, drain and gate.
  • FET field effect transistor
  • the power die supports a source to drain current equal to about 50 A (Amperes) or more.
  • the plurality of relatively small diameter bondwires comprises 25 bondwires.
  • FIGs. 1A and IB schematically show perspective views of a conventional semiconductor die and a conventional semiconductor package
  • FIG. 1C shows a schematic cross section of the semiconductor package shown in Fig. IB;
  • FIG. 2A schematically shows a die configured in accordance with an embodiment of the invention
  • FIG. 2B schematically shows a semiconductor submount in accordance with an embodiment of the invention
  • FIG. 2C schematically shows a cross section of the die shown in Fig. 2A mounted to the submount shown in Fig. 2B, in accordance with an embodiment of the invention
  • FIG. 2D schematically shows a perspective view of the die shown in Fig. 2A mounted to the submount shown in Fig. 2B, in accordance with an embodiment of the invention
  • FIG. 3 schematically shows another semiconductor submount, in accordance with an embodiment of the invention.
  • Fig. 4 schematically shows the die and submount shown in Fig. 2D mounted to a PCB
  • Fig. 1 A schematically shows a conventional semiconductor die 20 having die pads 21 for electrically connecting the die to a circuit (not shown) with which it may be used.
  • Fig. IB schematically shows a conventional package 30 in which a semiconductor die such as semiconductor die 20 may be packaged.
  • Package 30 has two lines of "package" leads 32, and is referred to as an inline package configuration.
  • Fig. 1 C schematically shows a cross section of a conventional inline die package 40, comprising, optionally, a Si power die 50, connected to package leads 42 and 45 and encapsulated in an overmolding 44 of a suitable epoxy or plastic.
  • Si power die 50 may comprise by way of example, a high power vertical field effect transistor or an insulated gate bipolar transistor (IGBT) (not shown).
  • the die optionally comprises source and gate pads 51, only one of which is shown in Fig. 1C, on a top surface 52 of the die and a drain pad 53 on a bottom surface 54 of the die.
  • a relatively large, optionally Al bondwire 70 electrically connects each source or gate pad 51 on top surface 52 of die 50 to a package lead 42.
  • Drain pad 53 is optionally soldered, brazed or glued directly to a lead frame 43 from which package lead 45 extends.
  • a portion 47 of lead frame 43 protrudes out from overmolding 44 so that die 50 may be directly mounted to a PCB or direct bonded copper (DBC) substrate (not shown) to provide the die with a heat sink.
  • a DBC typically comprises a layer of an electrically insulating, but heat conducting material, such as alumina (AI2O3) or aluminum nitride (A1N), sandwiched between copper layers
  • Fig. 2A schematically shows a planar GaN FET power die 80 configured for mounting to a submount in accordance with an embodiment of the invention.
  • GaN die 80 optionally has relatively small area die pads for electrically connecting to active regions (not shown) of the die.
  • the die pads, all of which are optionally located on a top surface 81 of the die include: source pads 82, drain pads 83, and gate pads 84.
  • the pads are located along edges of top surface 81, relatively distanced from active current carrying regions of the die.
  • the pads are suitable for bonding to bondwires having diameters equal to about 40 ⁇ using a wedge or ball bonding process.
  • source and drain pads 82 and 83 are rectangular and may have widths that are less than or equal to about 150 ⁇ .
  • gate pads 84 are located near corners of the die and are characterized by dimensions about equal to the widths of source and drain pads 82 and 83.
  • Fig. 2B schematically shows a perspective view of a submount 100 to which a semiconductor die such as GaN die 80 shown in Fig. 2A may be mounted in accordance with an embodiment of the invention.
  • Fig. 2C schematically shows a cross section in a plane indicated by line AA of GaN die 80 shown in Fig. 2A mounted in a recess 102 of submount 100 and encapsulated by an overmolding 121 of a suitable plastic or epoxy in a package 120 having package leads 122, in accordance with an embodiment of the invention.
  • Fig. 2D schematically shows a perspective view of GaN die 80 mounted to submount 100 shown in cross section in Fig.
  • submount 100 and GaN die 80 may be shown to better distinction in one or the other of Figs. 2B - 2D, and in the discussion below reference may be made to the figure which best shows a feature of the submount and/or GaN die and/or their relationship.
  • Submount 100 optionally comprises an insulating "picture" frame 104 mounted on a base plate 108 to form recess 102 for receiving a semiconductor die, such as GaN die 80 mounted to the submount (Fig. 2C).
  • insulating frame 104 comprises first and second picture frame shaped insulating layers 105 and 106 respectively formed optionally from polyimide or a liquid crystalline polymer.
  • Base plate 108 to which frame 104 is mounted may be formed from an electrically conducting material, such as copper, that is also a good thermal conductor.
  • Submount 100 comprises submount package lead pads 110 optionally on an upper surface 109 of insulating layer 105 of insulating picture frame 104 for electrically connecting the submount to package leads of a semiconductor package.
  • Package lead pads 110 are made sufficiently large so that relatively large diameter bondwires may be bonded in a wedge bonding process to the package leads and to the submount package lead pads.
  • Fig. 2C schematically shows submount package lead pads 110 connected to package leads 122 by relatively large, bondwires 140.
  • bondwires 140 are formed from Al and are bonded to package lead pads 110 and package leads 122 in a wedge bonding process.
  • Base plate 108 of submount 100 may seat on an optionally electrically conducting heat sink 111 that protrudes out from overmolding 121 of package 120 so that base plate 108 and thereby die 80 may be thermally and/or electrically coupled to an external heat sink.
  • Submount 100 comprises intermediate conductors 112 that are electrically connected to the submount package lead pads 110. Intermediate conductors 112 are optionally sandwiched between insulating layers 105 and 106 and are electrically connected to submount package lead pads 110 optionally by vias 113 (Fig. 2C). Intermediate conductors 112 provide contact regions 114 suitable for electrically connecting the intermediate conductors to die pads of a die mounted in recess 102 of submount 100 and thereby to connect the die pads to package leads of a package comprising submount 100.
  • each submount package lead pad 110 is connected to a different intermediate conductor 112. In an embodiment of the invention, each die pad is connected to a contact region 114 by a plurality of relatively small diameter bondwires.
  • FIG. 2C schematically shows each source pad 82 of GaN die 80 (see also Fig. 2 A) electrically connected to a contact region 114 of an intermediate conductors 112 of submount 100 by a relatively small diameter bond-wire 116.
  • the bondwire shown in Fig. 2C is one bondwire of a plurality of bondwires 116 that connect the source pads to a package lead pad 110.
  • the plurality of bondwires 116 that connect each source pad 82 to an intermediate contact regions 114 is shown in the perspective view of GaN die 80 and submount 100 in Fig. 2D.
  • 2D also shows drain pads 83 and gate pads 84 of GaN die 80 connected to intermediate conductors 112 by a plurality of small diameter bondwires 116.
  • small diameter bondwires 116 are relatively short, small diameter Copper or Gold wires that are bonded to the die pads 82, 83 and 84 and intermediate conductors 112 by a high speed automatic ball or wedge bonding process.
  • FET GaN die 80 may be square shaped having a side length equal to about 4 mm and thickness equal to about 400 ⁇ .
  • Each source pad 82 and each drain pad 83 may be bonded by about 25 bondwires 116 to a package lead pad 110.
  • Bondwires 116 may have a diameter between about 25 - 35 ⁇ , length equal to about 1 mm, and have a rated current capacity equal to about 1 A (ampere).
  • the die may support a total source to drain current equal to about 50 A, at which current it generates thermal energy at a rate of about 200 W (Watts), which is dissipated by submount 100.
  • Package lead pads 110 may be connected to package leads 122 or contact pads of a PCB or DCB by lead bondwires 140 having a diameter equal to about 500 ⁇ .
  • source drain and gate die pads 82, 83 and 84 to which small diameter bondwires 116 are bonded in accordance with an embodiment of the invention are distanced from active current regions of GaN die 80 and are located along the periphery of the die.
  • Repeated temperature changes at the bonding locations of the bondwires on die pads 82, 83 and 84 generated by changes in current flow through die as the die repeatedly switches on and switches off current are therefore relatively moderate.
  • recurrent mechanical stress at bond junctions of the die pads and bondwires due to possible mismatches in CTEs (coefficients of thermal expansion) between GaN and a material from which bondwires 116 are made are also relatively moderate.
  • bondwires 116 provide for relatively small area bond junctions between die pads 82, 83 and 84, and bondwires 116 and therefore also contributes to moderating stress at the bond junctions generated by temperature changes in the die.
  • bondwires 140 (Fig. 2C) that electrically connect package lead pads 110 and package leads 122
  • the package lead pads are not part of die 80 and during operation of the die remain relatively cool.
  • the bond junctions of bondwires 140 and pads 110 therefore suffer reduced stress due to temperature changes of the die during die operation and are relatively robust and resistant to heat cycle damage compared to large area bondwire junctions made directly to contact pads comprised in a die.
  • bondwires 140, package lead pads 110, package leads 122, and insulating layers 105 and 106 are made from materials having CTEs that are relatively close.
  • the formation of large area wire bond junctions on submount 100 rather than on GaN die 80 in accordance with an embodiment of the invention, also protects the die from damage due to mechanical and heat stress generated by a bonding process used to bond the bondwires.
  • bondwires 116 are ribbon bondwires to further reduce inductance of the configuration of bondwires 116 that connect die pads 82, 83, and 84 to submount package lead padsl 10.
  • Fig. 3 schematically shows a cross section of GaN die 80 mounted to a submount 200 which is variation of a submount in accordance with an embodiment of the invention.
  • package lead pads 202 are on a same side of the submount as a base plate 204 of the submount.
  • Intermediate conductors 206 are connected to lead pads 202 by vias 208.
  • the GaN die may be sealed in a recess 210 of the submount by a suitable potting material 212.
  • a semiconductor die mounted in a submount in accordance with an embodiment of the invention does not have to be packaged in a package as schematically shown in Fig. 2B, but may be directly connected by bondwires to a circuit with which it is used.
  • Fig. 4 schematically shows GaN die 80 mounted to submount 100 shown in Fig. 2D directly connected to pads on a PCB or DBC 220 that is used to control operation of the die by relatively large diameter bondwires 140.
  • a submount in accordance with an embodiment of the invention is not limited to being mounted with a single die or to having a recess or a single recess.
  • a submount in accordance with an embodiment of the invention may have a plurality of recesses or no recess.
  • a submount in an embodiment may also be configured to be mounted with a plurality of semiconductor dies.
  • each of the verbs, "comprise” “include” and “have”, and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb.

Abstract

A semiconductor die assembly comprising: a semiconductor die (80) having die pads for electrically connecting the die to external circuitry; and a submount (100) which supports the die (80) and has a conductor electrically connected to a die pad of the semiconductor die (80) by a plurality of relatively small diameter bondwires and a submount pad electrically connected to the conductor and having a surface configured to be electrically connected to a relatively large diameter bondwire (140).

Description

SEMICONDUCTOR DIE PACKAGE
RELATED APPLICATIONS
[0001] The present application claims the benefit under 35 U.S.C. 119(e) of U.S. Provisional Application 61/652,343 filed on May 29, 2012, the disclosure of which is incorporated herein by reference.
TECHNICAL FIELD
[0002] Embodiments of the invention relate to apparatus and methods of electrically connecting a semiconductor die to circuitry with which it is used.
BACKGROUND
[0003] Semiconductor devices (single component semiconductor architectures or multi-component semiconductor circuits), are typically formed in arrays containing large numbers of the devices on a semiconductor wafer, such as Si, GaAs, or GaN wafer. After formation, the wafer is separated, "diced", into pieces referred to as "dies", each of which comprises a single copy of the device. Components of the device, such as sources, drains and gates of transistors, comprised in a die that require electrical connection to external circuitry with which the device is to operate are electrically connected to conductive contact pads, also referred to as die pads, that are formed on a surface of the die. Semiconductor wafers are relatively expensive, and to reduce costs of semiconductor dies, elements of the devices they contain are typically made as small as possible and positioned close to each other. For example, semiconductor devices in a die contain stacks of very thin layers of semiconductor materials treated with different dopants, and contact pads are usually formed as close as possible, and generally immediately above, active regions of the stacks to which they provide electrical contact.
[0004] For conventional applications, a semiconductor die may be mounted to a submount, and together with the submount be encapsulated in a package by potting or molding in a protective epoxy or plastic. The submount mechanically supports the die and electrically conductive "package leads" that extend from the package, or are otherwise readily accessible from outside the package, which are used to electrically connect the packaged die to an external circuit with which the die is to be used. Conductive wires, typically copper (Cu), aluminum (Al), or gold (Au) "bondwires" that may have diameters ranging from about 15 μιη (micrometers) to hundreds of μιη connect the package leads to the contact die pads on the die.
[0005] The contact pads in high power field effect transistor (FET) dies that may for example be used as switches in power supply of TVs, uninterrupted power supply (UPS) systems, electric powered vehicles, radar systems, and electric motor controllers, are usually connected to the package leads in the packages that contain them by Al bondwires having diameters between about 300 μιη and about 500 μιη. The relatively large diameter, robust Al bondwires, are advantageous for supporting large currents that may be switched by the dies. However, large bondwires generally exact a penalty in reduced die lifetime and reliability. Temperature changes in a die during its operation may generate large mechanical stress at a junction between a bondwire and a contact pad of the die as a result of differences in coefficients of thermal expansion (CTE) between material of the bondwire, die, and or/the pad. The "CTE" stress increases with increase in area of the junction and as a result with increase in cross section area of the bondwire, and for large bondwires may result in cracking of the die that shortens a useful lifetime of the die.
[0006] A process referred to as "wedge bonding" is frequently used to connect the Al bondwires to the conductive pads and the package leads. In wedge bonding, an end of an Al bondwire is pressed to a contact region of a conductive pad or package lead to which it is to be connected simultaneously with application of ultrasonic energy. The ultrasonic energy generates frictional heating at the contact region, and the heating and pressure with which the bondwire is pressed to the contact region welds the bondwire to the contact region. For power dies in which the pads are very close to active regions of a power FET, the forces and heating involved in the wedge bonding process carry risks of damaging the power FET. However, the pads are required to be relatively large to accommodate the large diameter Al bondwires. Distancing the pads from the die's active areas generally entails using an increased amount of expensive area of a wafer to produce the die and incurring an undesirable cost penalty.
SUMMARY
[0010] An aspect of an embodiment of the invention relates to providing a semiconductor die package comprising a die mounted to a submount having a contact pad connected to package leads for electrically connecting the package to an external circuit by a relatively large diameter bondwire. An array of relatively small diameter bondwires electrically connects the contact pad on the submount to a contact pad located on the die.
[0011] For convenience of presentation, a contact pad on the submount that may be connected to a package lead in accordance with an embodiment of the invention may be referred to as a "submount lead pad". Bondwires that connect the submount lead pad to a lead may be referred to as "lead bondwires" and bondwires that electrically connect a submount lead pad to a die pad, may be referred to as "die bondwires".
[0012] In an embodiment of the invention, the submount comprises an intermediate conductor that is electrically connected to the submount lead pad, and the die bondwires in the array of die bondwires are connected to the intermediate conductor. Optionally, the submount comprises a first insulating layer and a second insulating layer stacked over the first layer which sandwich between them the intermediate conductor. The submount lead pad may be formed on a top surface of the second insulating layer and be connected to the intermediate conductor by a via.
[0013] In an embodiment of the invention the submount is formed having a recess into which the die seats. Optionally, the recess has a bottom formed from a heat and electrically conducting material, such as a metal. Optionally, all the contact pads comprised in the die that are required for operation of the die are located on a same, "top", surface of the die.
[0014] In an embodiment of the invention, the die comprises a FET power transistor.
Optionally, the power transistor is formed from nitride based semiconductor materials, such as GaN (Gallium Nitride) and AlGaN (Aluminum Gallium Nitride). In an embodiment of the invention, the FET is a high electron mobility transistor "HEMT" transistor. In an embodiment of the invention the die comprises a GaN Schottky diode.
[0015] There is therefore provided in accordance with an embodiment of the invention a semiconductor die assembly comprising: a semiconductor die having die pads for electrically connecting the die to external circuitry; and a submount supporting the die and comprising: a conductor electrically connected to a die pad of the semiconductor die by a plurality of relatively small diameter bondwires; and a submount pad electrically connected to the conductor and having a surface configured to be electrically connected to a relatively large diameter bondwire.
[0016] Optionally, the submount is formed having a recess in which the semiconductor die seats.
Optionally, the heat conducting base plate at the bottom of the recess on which the die seats. The heat conducting base plate may be electrically conducting. The submount pad and the base plate may be located on a same surface of the submount. [0017] In an embodiment of the invention, the die assembly comprises a layer of insulating material and wherein the submount pad comprises a first electrically conducting layer located on a surface of the insulating layer and the conductor comprises a second electrically conducting layer located on a side of the insulating layer opposite a side of the insulating layer on which the surface is located. Optionally, the conductor and submount pad are electrically connected by a conductive via. Additionally or alternatively, the second conducting layer has an exposed surface located along an edge of the recess. Optionally, the plurality of bondwires are electrically connected to the exposed surface.
[0018] In an embodiment of the invention, each of the relatively small diameter bondwires has a diameter between about 25 μιη (micrometers) and about 35 μιη. The die assembly may comprise a die package having a package lead electrically connected to the submount pad by a relatively large diameter bondwire. Optionally, the large diameter bondwire has a diameter equal to about 500 μιη.
[0019] In an embodiment of the invention, the die is a field effect transistor (FET) power die having a source, drain and gate. Optionally, the power die supports a source to drain current equal to about 50 A (Amperes) or more. Optionally, the plurality of relatively small diameter bondwires comprises 25 bondwires.
[0020] In the discussion, unless otherwise stated, adjectives such as "substantially" and "about" modifying a condition or relationship characteristic of a feature or features of an embodiment of the invention, are understood to mean that the condition or characteristic is defined to within tolerances that are acceptable for operation of the embodiment for an application for which it is intended
[0021] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
BRIEF DESCRIPTION OF FIGURES
[0022] Non-limiting examples of embodiments of the invention are described below with reference to figures attached hereto that are listed following this paragraph. Identical structures, elements or parts that appear in more than one figure are generally labeled with a same numeral in all the figures in which they appear. A label labeling an icon representing a given feature of an embodiment of the invention in a figure may be used to reference the given feature. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.
[0023] Figs. 1A and IB schematically show perspective views of a conventional semiconductor die and a conventional semiconductor package;
[0024] Fig. 1C shows a schematic cross section of the semiconductor package shown in Fig. IB;
[0025] Fig. 2A schematically shows a die configured in accordance with an embodiment of the invention;
[0026] Fig. 2B schematically shows a semiconductor submount in accordance with an embodiment of the invention;
[0027] Fig. 2C schematically shows a cross section of the die shown in Fig. 2A mounted to the submount shown in Fig. 2B, in accordance with an embodiment of the invention;
[0028] Fig. 2D schematically shows a perspective view of the die shown in Fig. 2A mounted to the submount shown in Fig. 2B, in accordance with an embodiment of the invention;
[0029] Fig. 3 schematically shows another semiconductor submount, in accordance with an embodiment of the invention; and
[0030] Fig. 4 schematically shows the die and submount shown in Fig. 2D mounted to a PCB
(Printed Circuit Board) or DBC (Direct Bonded Copper) substrate, in accordance with an embodiment of the invention.
DETAILED DESCRIPTION
[0031] Fig. 1 A schematically shows a conventional semiconductor die 20 having die pads 21 for electrically connecting the die to a circuit (not shown) with which it may be used. Fig. IB schematically shows a conventional package 30 in which a semiconductor die such as semiconductor die 20 may be packaged. Package 30 has two lines of "package" leads 32, and is referred to as an inline package configuration.
[0032] Fig. 1 C schematically shows a cross section of a conventional inline die package 40, comprising, optionally, a Si power die 50, connected to package leads 42 and 45 and encapsulated in an overmolding 44 of a suitable epoxy or plastic. Si power die 50 may comprise by way of example, a high power vertical field effect transistor or an insulated gate bipolar transistor (IGBT) (not shown). The die optionally comprises source and gate pads 51, only one of which is shown in Fig. 1C, on a top surface 52 of the die and a drain pad 53 on a bottom surface 54 of the die. A relatively large, optionally Al bondwire 70, electrically connects each source or gate pad 51 on top surface 52 of die 50 to a package lead 42. Drain pad 53 is optionally soldered, brazed or glued directly to a lead frame 43 from which package lead 45 extends. Optionally, a portion 47 of lead frame 43 protrudes out from overmolding 44 so that die 50 may be directly mounted to a PCB or direct bonded copper (DBC) substrate (not shown) to provide the die with a heat sink. A DBC typically comprises a layer of an electrically insulating, but heat conducting material, such as alumina (AI2O3) or aluminum nitride (A1N), sandwiched between copper layers
[0033] Fig. 2A schematically shows a planar GaN FET power die 80 configured for mounting to a submount in accordance with an embodiment of the invention. GaN die 80 optionally has relatively small area die pads for electrically connecting to active regions (not shown) of the die. The die pads, all of which are optionally located on a top surface 81 of the die include: source pads 82, drain pads 83, and gate pads 84. In an embodiment of the invention, the pads are located along edges of top surface 81, relatively distanced from active current carrying regions of the die. Optionally, the pads are suitable for bonding to bondwires having diameters equal to about 40 μιη using a wedge or ball bonding process. In an embodiment of the invention, source and drain pads 82 and 83 are rectangular and may have widths that are less than or equal to about 150 μιη. Optionally, gate pads 84 are located near corners of the die and are characterized by dimensions about equal to the widths of source and drain pads 82 and 83.
[0034] Fig. 2B schematically shows a perspective view of a submount 100 to which a semiconductor die such as GaN die 80 shown in Fig. 2A may be mounted in accordance with an embodiment of the invention. Fig. 2C schematically shows a cross section in a plane indicated by line AA of GaN die 80 shown in Fig. 2A mounted in a recess 102 of submount 100 and encapsulated by an overmolding 121 of a suitable plastic or epoxy in a package 120 having package leads 122, in accordance with an embodiment of the invention. Fig. 2D schematically shows a perspective view of GaN die 80 mounted to submount 100 shown in cross section in Fig. 2C, before encapsulation in overmolding 121 of package 120 in accordance with an embodiment of the invention. Various features of submount 100 and GaN die 80 may be shown to better distinction in one or the other of Figs. 2B - 2D, and in the discussion below reference may be made to the figure which best shows a feature of the submount and/or GaN die and/or their relationship.
[0035] Submount 100 optionally comprises an insulating "picture" frame 104 mounted on a base plate 108 to form recess 102 for receiving a semiconductor die, such as GaN die 80 mounted to the submount (Fig. 2C). In an embodiment of the invention, insulating frame 104 comprises first and second picture frame shaped insulating layers 105 and 106 respectively formed optionally from polyimide or a liquid crystalline polymer. Base plate 108 to which frame 104 is mounted may be formed from an electrically conducting material, such as copper, that is also a good thermal conductor. Submount 100 comprises submount package lead pads 110 optionally on an upper surface 109 of insulating layer 105 of insulating picture frame 104 for electrically connecting the submount to package leads of a semiconductor package. Package lead pads 110 are made sufficiently large so that relatively large diameter bondwires may be bonded in a wedge bonding process to the package leads and to the submount package lead pads.
[0036] By way of example, Fig. 2C schematically shows submount package lead pads 110 connected to package leads 122 by relatively large, bondwires 140. In an embodiment of the invention, bondwires 140 are formed from Al and are bonded to package lead pads 110 and package leads 122 in a wedge bonding process. Base plate 108 of submount 100 may seat on an optionally electrically conducting heat sink 111 that protrudes out from overmolding 121 of package 120 so that base plate 108 and thereby die 80 may be thermally and/or electrically coupled to an external heat sink.
[0037] Submount 100 comprises intermediate conductors 112 that are electrically connected to the submount package lead pads 110. Intermediate conductors 112 are optionally sandwiched between insulating layers 105 and 106 and are electrically connected to submount package lead pads 110 optionally by vias 113 (Fig. 2C). Intermediate conductors 112 provide contact regions 114 suitable for electrically connecting the intermediate conductors to die pads of a die mounted in recess 102 of submount 100 and thereby to connect the die pads to package leads of a package comprising submount 100. Optionally, each submount package lead pad 110 is connected to a different intermediate conductor 112. In an embodiment of the invention, each die pad is connected to a contact region 114 by a plurality of relatively small diameter bondwires.
[0038] By way of example Fig. 2C schematically shows each source pad 82 of GaN die 80 (see also Fig. 2 A) electrically connected to a contact region 114 of an intermediate conductors 112 of submount 100 by a relatively small diameter bond-wire 116. The bondwire shown in Fig. 2C is one bondwire of a plurality of bondwires 116 that connect the source pads to a package lead pad 110. The plurality of bondwires 116 that connect each source pad 82 to an intermediate contact regions 114 is shown in the perspective view of GaN die 80 and submount 100 in Fig. 2D. Fig. 2D also shows drain pads 83 and gate pads 84 of GaN die 80 connected to intermediate conductors 112 by a plurality of small diameter bondwires 116. Optionally small diameter bondwires 116 are relatively short, small diameter Copper or Gold wires that are bonded to the die pads 82, 83 and 84 and intermediate conductors 112 by a high speed automatic ball or wedge bonding process. [0039] By way of a numerical example, FET GaN die 80 may be square shaped having a side length equal to about 4 mm and thickness equal to about 400 μιη. Each source pad 82 and each drain pad 83 may be bonded by about 25 bondwires 116 to a package lead pad 110. Bondwires 116 may have a diameter between about 25 - 35 μιη, length equal to about 1 mm, and have a rated current capacity equal to about 1 A (ampere). The die may support a total source to drain current equal to about 50 A, at which current it generates thermal energy at a rate of about 200 W (Watts), which is dissipated by submount 100. Package lead pads 110 may be connected to package leads 122 or contact pads of a PCB or DCB by lead bondwires 140 having a diameter equal to about 500 μιη.
[0040] As noted above, source drain and gate die pads 82, 83 and 84 to which small diameter bondwires 116 are bonded in accordance with an embodiment of the invention are distanced from active current regions of GaN die 80 and are located along the periphery of the die. Repeated temperature changes at the bonding locations of the bondwires on die pads 82, 83 and 84 generated by changes in current flow through die as the die repeatedly switches on and switches off current are therefore relatively moderate. As a result, recurrent mechanical stress at bond junctions of the die pads and bondwires due to possible mismatches in CTEs (coefficients of thermal expansion) between GaN and a material from which bondwires 116 are made are also relatively moderate.
[0041] As noted above CTE stress increases with size of a bonding area of a bondwire and a pad to which it is bonded. The relatively small diameter of bondwires 116 provides for relatively small area bond junctions between die pads 82, 83 and 84, and bondwires 116 and therefore also contributes to moderating stress at the bond junctions generated by temperature changes in the die.
[0042] With respect to the relatively large area bond junctions of bondwires 140 (Fig. 2C) that electrically connect package lead pads 110 and package leads 122, the package lead pads are not part of die 80 and during operation of the die remain relatively cool. The bond junctions of bondwires 140 and pads 110 therefore suffer reduced stress due to temperature changes of the die during die operation and are relatively robust and resistant to heat cycle damage compared to large area bondwire junctions made directly to contact pads comprised in a die. In an embodiment of the invention, to further protect the die from thermal damage, bondwires 140, package lead pads 110, package leads 122, and insulating layers 105 and 106 are made from materials having CTEs that are relatively close. The formation of large area wire bond junctions on submount 100 rather than on GaN die 80, in accordance with an embodiment of the invention, also protects the die from damage due to mechanical and heat stress generated by a bonding process used to bond the bondwires.
[0043] It is further noted that the configuration of a plurality of closely spaced, short substantially parallel bondwires 116 provides for relatively low inductance coupling between GaN die 80 and intermediate conductors 112 of submount 100. In an embodiment of the invention bondwires 116 are ribbon bondwires to further reduce inductance of the configuration of bondwires 116 that connect die pads 82, 83, and 84 to submount package lead padsl 10.
[0044] Fig. 3 schematically shows a cross section of GaN die 80 mounted to a submount 200 which is variation of a submount in accordance with an embodiment of the invention. In submount 200 package lead pads 202 are on a same side of the submount as a base plate 204 of the submount. Intermediate conductors 206 are connected to lead pads 202 by vias 208. The GaN die may be sealed in a recess 210 of the submount by a suitable potting material 212.
[0045] A semiconductor die mounted in a submount in accordance with an embodiment of the invention does not have to be packaged in a package as schematically shown in Fig. 2B, but may be directly connected by bondwires to a circuit with which it is used. By way of example, Fig. 4 schematically shows GaN die 80 mounted to submount 100 shown in Fig. 2D directly connected to pads on a PCB or DBC 220 that is used to control operation of the die by relatively large diameter bondwires 140.
[0046] Whereas in the above description a submount is shown formed having a single recess and mounted with a single die, a submount in accordance with an embodiment of the invention is not limited to being mounted with a single die or to having a recess or a single recess. A submount in accordance with an embodiment of the invention may have a plurality of recesses or no recess. A submount in an embodiment may also be configured to be mounted with a plurality of semiconductor dies.
[0047] In the description and claims of the present application, each of the verbs, "comprise" "include" and "have", and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb.
[0048] Descriptions of embodiments of the invention in the present application are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise different features, not all of which are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of the features. Variations of embodiments of the invention that are described, and embodiments of the invention comprising different combinations of features noted in the described embodiments, will occur to persons of the art. The scope of the invention is limited only by the claims.

Claims

1. A semiconductor die assembly comprising:
a semiconductor die having die pads for electrically connecting the die to external circuitry; and
a submount supporting the die and comprising:
a conductor electrically connected to a die pad of the semiconductor die by a plurality of relatively small diameter bondwires; and
a submount pad electrically connected to the conductor and having a surface configured to be electrically connected to a relatively large diameter bondwire.
2. The semiconductor die assembly according to claim 1 wherein the submount is formed having a recess in which the semiconductor die seats.
3. The semiconductor die assembly according to claim 2 and comprising a heat conducting base plate at the bottom of the recess on which the die seats.
4. The semiconductor die assembly according to claim 3 wherein the heat conducting base plate is electrically conducting.
5. The semiconductor die assembly according to claim 4 wherein the submount pad and the base plate are located on a same surface of the submount.
6. The semiconductor die assembly according to any of claims 2-5 and comprising a layer of insulating material and wherein the submount pad comprises a first electrically conducting layer located on a surface of the insulating layer and the conductor comprises a second electrically conducting layer located on a side of the insulating layer opposite a side of the insulating layer on which the surface is located.
7. The semiconductor die assembly according to claim 6 wherein the conductor and submount pad are electrically connected by a conductive via.
8. The semiconductor die assembly according to claim 6 or claim 7 wherein the second conducting layer has an exposed surface located along an edge of the recess.
9. The semiconductor die assembly according to claim 8 wherein the plurality of bondwires are electrically connected to the exposed surface.
10. The semiconductor die assembly according to any of the preceding claims wherein each of the relatively small diameter bondwires has a diameter between about 25 μιη (micrometers) and about 35 μιη.
11. The semiconductor die assembly according to any of the preceding claims and comprising a die package having a package lead electrically connected to the submount pad by a relatively large diameter bondwire.
12. The semiconductor die assembly according to claim 11 wherein the large diameter bondwire has a diameter equal to about 500 μιη.
13. The semiconductor die assembly according to an of the preceding claims wherein the die is a field effect transistor (FET) power die having a source, drain and gate.
14. The semiconductor die assembly according to claim 13 wherein the power die supports a source to drain current equal to about 50 A (Amperes).
15. The semiconductor die assembly according to claim 14 wherein the plurality of relatively small diameter bondwires comprises 25 bondwires.
PCT/IB2013/054364 2012-05-29 2013-05-27 Semiconductor die package WO2013179205A1 (en)

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