CN113410200A - Chip packaging frame and chip packaging structure - Google Patents

Chip packaging frame and chip packaging structure Download PDF

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Publication number
CN113410200A
CN113410200A CN202010182721.4A CN202010182721A CN113410200A CN 113410200 A CN113410200 A CN 113410200A CN 202010182721 A CN202010182721 A CN 202010182721A CN 113410200 A CN113410200 A CN 113410200A
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Prior art keywords
chip
conductive layer
sub
electrically connected
layer
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CN202010182721.4A
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CN113410200B (en
Inventor
吴俊峰
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Gpower Semiconductor Inc
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Gpower Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a chip packaging frame and a chip packaging structure. Wherein the chip package frame includes: a package base; the substrate is arranged on the packaging base, is divided into at least one chip area and comprises a first conductive layer and an insulating layer which are stacked; the at least one second conducting layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and is in one-to-one correspondence with the chip area, wherein the at least one second conducting layer comprises a first sub-conducting layer, a first conducting through hole is formed in the insulating layer, and the first sub-conducting layer is electrically connected with the first conducting layer through the first conducting through hole; and the at least one electrode pin is positioned on at least one side of the packaging base and comprises a first electrode pin, and the first electrode pin is electrically connected with the first conductive layer. The invention solves the problem that the performance and stability of the packaged chip are influenced because the existing packaging structure has larger parasitic parameters, and reduces the parasitic parameters of the packaging structure.

Description

Chip packaging frame and chip packaging structure
Technical Field
The embodiment of the invention relates to the technical field of chip packaging, in particular to a chip packaging frame and a chip packaging structure.
Background
In the aspect of semiconductor electronic devices, an AlGaN/GaN High Electron Mobility Transistor (HEMT) is a wide bandgap semiconductor device having a High-concentration Two-Dimensional Electron Gas (2 DEG), has the characteristics of High output power density, High temperature resistance, strong stability and High breakdown voltage, and has great application potential in the field of power electronic devices.
The AlGaN/GaN hemt generally operates under high frequency and high power conditions, and has higher requirements on parasitic parameters and heat dissipation capability of a package structure. The current common package types are mainly single-side pin package and multi-side pin package. Due to the pin layout and the structure of the chip package frame, the single-sided pin package has high heat dissipation capacity but large parasitic parameters, while the multi-sided pin package has lower parasitic parameters but poor heat dissipation capacity. Although the multi-edge pin package has lower parasitic parameters than the single-edge pin package, the package structure still has larger parasitic parameters, which affects the performance and stability of the packaged chip. Therefore, how to further reduce the parasitic parameters of the package structure becomes one of the research directions of the chip package structure.
Disclosure of Invention
In view of the above, the present invention provides a chip package frame and a chip package structure to reduce parasitic parameters of the package structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a chip package frame, including:
a package base;
the substrate is arranged on the packaging base, is divided into at least one chip area and comprises a first conductive layer and an insulating layer which are stacked;
the at least one second conducting layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and is in one-to-one correspondence with the chip area, wherein the at least one second conducting layer comprises a first sub-conducting layer, a first conducting through hole is formed in the insulating layer, and the first sub-conducting layer is electrically connected with the first conducting layer through the first conducting through hole;
and the at least one electrode pin is positioned on at least one side of the packaging base and comprises a first electrode pin, and the first electrode pin is electrically connected with the first conductive layer.
Optionally, the at least one second conductive layer further includes a second sub-conductive layer, and the second sub-conductive layer is insulated from the first sub-conductive layer.
Optionally, the chip package frame further includes a third conductive layer disposed on the upper surface of the insulating layer and located outside the chip region, the insulating layer is provided with a second conductive through hole, and the third conductive layer is electrically connected to the first conductive layer through the second conductive through hole.
Optionally, the chip package frame further includes a fourth conductive layer, and the fourth conductive layer is located outside the chip region and insulated from the first sub-conductive layer.
On the other hand, the embodiment of the invention also provides a chip packaging structure, which comprises at least one chip and the chip packaging frame provided by the embodiment of the invention;
the chip is attached to the chip packaging frame, and chip electrodes of the chip are electrically connected with corresponding electrode pins respectively;
the at least one chip comprises a first chip, the first chip is attached to the first sub-conducting layer, and at least one surface electrode of the first chip is electrically connected with the first sub-conducting layer.
Optionally, the at least one surface electrode includes a first surface electrode disposed on the lower surface of the first chip, and the first surface electrode is in electrical contact with the first sub-conductive layer;
optionally, the area of the first sub-conductive layer is larger than the area occupied by the first chip, the at least one surface electrode includes a second surface electrode disposed on the upper surface of the first chip, and the second surface electrode is electrically connected to a portion of the first sub-conductive layer, which is located outside the area where the first chip is located, through a first bonding wire.
Optionally, the at least one second conductive layer further includes a second sub-conductive layer, and the second sub-conductive layer is insulated from the first sub-conductive layer;
the at least one chip further comprises a second chip, the second chip is attached to the second sub-conducting layer, the second chip comprises a third surface electrode arranged on the lower surface of the second chip, and the third surface electrode is in electric contact with the second sub-conducting layer.
Optionally, the chip package frame further includes a third conductive layer, the third conductive layer is disposed on the upper surface of the insulating layer and located outside the chip region, a second conductive through hole is disposed on the insulating layer, and the third conductive layer is electrically connected to the first conductive layer through the second conductive through hole;
the second chip further comprises a fourth surface electrode arranged on the upper surface of the second chip, and the fourth surface electrode is electrically connected with the third conductive layer through a second bonding wire.
Optionally, the chip package frame further includes a fourth conductive layer, and the fourth conductive layer is located outside the chip region and insulated from the first sub-conductive layer;
the fourth conducting layer comprises a third sub-conducting layer, the at least one electrode pin further comprises a second electrode pin, the at least one surface electrode further comprises a fifth surface electrode arranged on the upper surface of the first chip, the fifth surface electrode is electrically connected with the third sub-conducting layer through a third bonding wire, and the third sub-conducting layer is electrically connected with the second electrode pin through a fourth bonding wire; and/or the fourth conducting layer comprises a fourth sub-conducting layer, the at least one electrode pin further comprises a third electrode pin, the second chip further comprises a sixth surface electrode arranged on the upper surface of the second chip, the sixth surface electrode is electrically connected with the fourth sub-conducting layer through a fifth bonding wire, and the fourth sub-conducting layer is electrically connected with the third electrode pin through a sixth bonding wire.
Optionally, a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer.
Optionally, the first chip and the second chip form a cascade of codes.
The invention has the beneficial effects that: the chip packaging frame and the chip packaging structure provided by the invention have the advantages that the substrate is arranged on the packaging base and comprises the first conductive layer and the insulating layer which are laminated, the first conductive layer is electrically connected with the first electrode pin of the packaging frame, at least one second conductive layer is arranged on the upper surface of the insulating layer and is positioned in the chip area of the substrate, and meanwhile, the first sub-conductive layer in the second conductive layer is electrically connected with the first conductive layer through the first conductive through hole on the insulating layer, so that at least one surface electrode of the chip arranged on the first sub-conductive layer is electrically connected with the first sub-conductive layer, the surface electrode can be electrically connected with the first electrode pin, the surface electrode is prevented from being electrically connected with the first electrode pin directly through a bonding wire, the length of the bonding wire in the chip packaging structure can be shortened, and the parasitic parameter introduced by the bonding wire is reduced, thereby reducing the parasitic parameters of the chip package structure.
Drawings
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a schematic structural diagram of a chip package frame according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view along AA' in FIG. 1;
fig. 3 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view taken along line BB' in FIG. 3;
fig. 5 is a schematic structural diagram of another chip package frame according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view taken along line CC' of FIG. 5;
fig. 7 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
FIG. 8 is a schematic view of the structure taken along the section DD' in FIG. 7;
fig. 9 is a schematic structural diagram of another chip package frame according to an embodiment of the present invention;
FIG. 10 is a schematic sectional view taken along EE' in FIG. 9;
fig. 11 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view taken along FF' of FIG. 11;
fig. 13 is a schematic structural diagram of another chip package frame according to an embodiment of the invention;
fig. 14 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
fig. 16 is an equivalent circuit diagram of a chip package structure according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of another chip package structure according to an embodiment of the present invention;
fig. 18 is an equivalent circuit diagram of another chip package structure according to an embodiment of the present invention;
fig. 19 is an equivalent circuit diagram of another chip package structure according to an embodiment of the invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The chip packaging frame provided by the embodiment of the invention can be used for single chip packaging or multi-chip packaging, wherein the multi-chip packaging can comprise cascade chip packaging and is suitable for reducing the parasitic parameters of a packaging structure. Fig. 1 is a schematic structural diagram of a chip package frame according to an embodiment of the present invention; FIG. 2 is a schematic view of the cross-sectional structure along AA' in FIG. 1. As shown in fig. 1 and fig. 2, the chip package frame provided in this embodiment includes:
a package base 1;
the substrate 2 is arranged on the packaging base 1, is divided into at least one chip area and comprises a first conductive layer 21 and an insulating layer 22 which are stacked;
at least one second conductive layer 5, disposed on the upper surface of the insulating layer 22, located in the chip region and disposed in one-to-one correspondence with the chip region, wherein the at least one second conductive layer 5 includes a first sub-conductive layer 51, the insulating layer 22 is disposed with a first conductive via 23, and the first sub-conductive layer 51 is electrically connected to the first conductive layer 21 through the first conductive via 23;
at least one electrode pin 4 is located on at least one side of the package base 1, and includes a first electrode pin 41, and the first electrode pin 41 is electrically connected to the first conductive layer 21.
In this embodiment, the package base 1 mainly plays a role of bearing a chip to be packaged and other components, and may be a conductive base, such as a metal base, and the specific material may be copper or aluminum, or may be other metals or alloys with better thermal conductivity. The present embodiment does not limit this, and may be determined according to actual situations. The first conductive via 23 of the substrate 2 may be filled with a conductive material so that the second conductive layer 5 is electrically connected to the first conductive layer 21 through the first conductive via 23.
In this embodiment, the substrate 2 can play a role in transferring heat, and the substrate 2 can be made of a high thermal conductive insulating material, specifically, the substrate 2 can be made of polyethylene or other high polymer materials doped with a thermal conductive filler, so that it can be ensured that heat generated by the chip 3 can be rapidly transferred to the package base 1. Further, the breakdown voltage of the substrate 2 may be more than 50V, and preferably, the breakdown voltage is 100V. On the basis of ensuring that the breakdown voltage of the substrate 2 meets the conditions, the thickness of the substrate 2 is as thin as possible, preferably, the thickness of the substrate 2 is smaller than 0.5 micrometer, so that heat generated by the chip 3 can be further ensured to be transferred to the packaging base 1 as far as possible, and good heat dissipation of the chip 3 is realized.
The chip which can be packaged by the chip packaging frame provided by the embodiment can comprise various types of chips, such as diodes or triodes, and the chip packaging structure can only package one or more chips of the same type, and can also package other types of chips at the same time. The chip areas can be divided according to the actual layout of the chips to be packaged, each chip area is provided with a second conducting layer 5, and the chips to be packaged are attached to the second conducting layers 5. At least one electrode pin 4 is used for leading out an electrode of the chip to realize the electric connection with an external circuit.
In the chip package frame provided by this embodiment, the substrate 2 is disposed on the package base 1, the substrate 2 includes the first conductive layer 21 and the insulating layer 22, and the first conductive layer 21 is electrically connected to at least one electrode pin 4 of the chip package frame, and the at least one second conductive layer 5 is disposed on the upper surface of the insulating layer 22 and located in the chip region of the substrate 2, and meanwhile, the first sub-conductive layer 51 in the second conductive layer 5 is electrically connected to the first conductive layer 21 through the first conductive via 23 on the insulating layer 22, so that at least one surface electrode of the chip disposed on the first sub-conductive layer 51 is electrically connected to the first sub-conductive layer 51, that is, the surface electrode can be electrically connected to any one of the first electrode pins 41 of the at least one electrode pin 4, thereby avoiding the surface electrode being electrically connected to the first electrode pin 41 directly through a bonding wire, and further, the length of a bonding wire in the chip packaging structure can be shortened, so that parasitic parameters introduced by the bonding wire are reduced, and the parasitic parameters of the chip packaging structure are reduced.
Optionally, the first conductive layer 21 of the present invention is electrically connected to at least one electrode pin 4 of the chip package frame, which may be implemented by disposing the first electrode pin 41 to be in direct electrical contact with the first conductive layer 21, or may be implemented by electrically contacting the first conductive layer 21 with the package base 1, and then electrically connecting the package base 1 with the first electrode pin 41 of the chip package frame.
Correspondingly, the embodiment of the invention further provides a chip packaging structure, and fig. 3 is a schematic structural diagram of the chip packaging structure provided by the embodiment of the invention; fig. 4 is a schematic cross-sectional view taken along BB' in fig. 3. As shown in fig. 3 and 4, the chip package structure provided in this embodiment includes: at least one chip 3 and the chip package frame provided by the above embodiments;
at least one chip 3 is attached to the chip packaging frame, and chip electrodes of at least one chip 3 are electrically connected with corresponding electrode pins 4 respectively;
at least one chip 3 comprises a first chip 31, the first chip 31 is attached to the first sub-conductive layer 51, and at least one surface electrode of the first chip 31 is electrically connected with the first sub-conductive layer 51.
In this embodiment, referring to fig. 4, the at least one surface electrode may include a first surface electrode 310 disposed on the lower surface of the first chip 31, the first surface electrode 310 is electrically contacted with the first sub-conductive layer 51, and in this embodiment, the first surface electrode 310 is preferably directly contacted with the first sub-conductive layer 51. Because the first sub-conductive layer 51 is electrically connected with the first conductive layer 21 through the first conductive through hole 23, and the first conductive layer 21 is electrically connected with the first electrode pin 41, the first surface electrode 310 and the first electrode pin 41 can be electrically connected by setting the first surface electrode 310 to be electrically contacted with the first sub-conductive layer 51 without setting a bonding wire for connecting the first surface electrode 310 and the first electrode pin 41, and the use of the bonding wire is avoided, so that the parasitic parameters introduced by the bonding wire are reduced, and the performance and the stability of the packaged chip are improved. It should be understood that, in the present invention, at least one electrode pin 4 at least includes the first electrode pin 41, and the position of the first electrode pin 41 is arbitrary, and the drawings of the present invention are only an example and are not limited to the example, and it is sufficient to ensure that the first electrode pin 41 is electrically connected to the first sub-conductive layer 51.
Alternatively, referring to fig. 3 and 4, the area of the first sub-conductive layer 51 is larger than the area occupied by the first chip 31, at least one surface electrode includes a second surface electrode 311 disposed on the upper surface of the first chip 31, and the second surface electrode 311 passes through the first bonding wire L1And is electrically connected to a portion of the first sub-conductive layer 51 outside the area where the first chip 31 is located. Thereby, the second surface electrode 311 passes through the first bonding wire L1The second surface electrode 311 is electrically connected to the first sub-conductive layer 51 of the chip region where the first chip 31 is located, that is, the second surface electrode 311 is electrically connected to at least one electrode pin 4, and the distance from the second surface electrode 311 to the first sub-conductive layer 51 is smaller than the distance from the second surface electrode 311 to the first electrode pin 41, so that the first bonding wire L1Is shorter than the length of the bonding wire L0 (see fig. 3) directly connecting the first surface electrode 310 and the first electrode lead 41, thereby shortening the length of the bonding wire that electrically connects the second surface electrode 311 and the first electrode lead 41, thereby reducing parasitic parameters introduced by the bonding wire and thus reducing the coreParasitic parameters of the chip package structure.
In consideration of the overall layout of each chip in the chip package structure, such as the need of insulation between partial chips or between chip electrodes of partial chips, in another embodiment of the present invention, fig. 5 is a schematic structural diagram of another chip package frame provided in an embodiment of the present invention; fig. 6 is a schematic cross-sectional view taken along line CC' in fig. 5. As shown in fig. 5 and 6, the at least one second conductive layer further includes a second sub-conductive layer 52, and the second sub-conductive layer 52 is insulated from the first sub-conductive layer 51. Illustratively, the first sub-conductive layer 51 and the second sub-conductive layer 52 are located in different chip regions, the first sub-conductive layer 51 and the second sub-conductive layer 52 are disposed at an interval, the insulating layer 22 under the first sub-conductive layer 51 is provided with a first conductive via 23, the first sub-conductive layer 51 is electrically connected to the first conductive layer 21 through the first conductive via 23, meanwhile, the insulating layer under the second sub-conductive layer 52 is not provided with a conductive via, at this time, the second sub-conductive layer 52 is insulated from the first conductive layer 21, so that the second sub-conductive layer 52 is insulated from the first sub-conductive layer 51.
Correspondingly, the embodiment further provides a chip packaging structure, and fig. 7 is a schematic structural diagram of another chip packaging structure provided in the embodiment of the present invention; fig. 8 is a schematic view of the structure taken along the section DD' in fig. 7. As shown in fig. 7 and fig. 8, based on the chip package structure provided in the above embodiment, in this embodiment, at least one chip further includes a second chip 32, the second chip 32 is attached on the second sub-conductive layer 52, the second chip 32 includes a third surface electrode 320 disposed on the lower surface of the second chip 32, and the third surface electrode 320 is in electrical contact with the second sub-conductive layer 52.
The chip package structure provided in this embodiment is based on the chip package frames shown in fig. 5 and fig. 6, and the first chip 31 and the second chip 32 are integrally arranged, so that the first surface electrode 310 of the first chip 31 and the third surface electrode 320 of the second chip 32 can be electrically insulated. Meanwhile, when the third surface electrode 320 does not need to be electrically connected to the chip electrodes of other chips, the area of the second sub-conductive layer 52 may be the same as the area occupied by the second chip 32, and the third surface electrode 320 may function as a buffer layer, which facilitates the mounting of the third surface electrode 320; when the third surface electrode 320 needs to be electrically connected to chip electrodes of other chips, the area of the second sub-conductive layer 52 may be larger than the same area occupied by the second chip 32, and the chip electrodes of the other chips may be electrically connected to the portion of the second sub-conductive layer 52 outside the second chip 32, so as to electrically connect the chip electrodes of the other chips to the third surface electrode 320.
Optionally, based on the above embodiment, in another embodiment of the present invention, fig. 9 is a schematic structural diagram of another chip package frame provided in the embodiment of the present invention; fig. 10 is a schematic sectional view along EE' in fig. 9. As shown in fig. 9 and 10, the chip package frame further includes a third conductive layer 6, the third conductive layer 6 is disposed on the upper surface of the insulating layer 22 and located outside the chip region, a second conductive via 24 is disposed on the insulating layer 22, and the third conductive layer 6 is electrically connected to the first conductive layer 21 through the second conductive via 24.
Considering that the surface electrode of the chip (e.g., the first chip) located on the first sub-conductive layer 51 may be electrically connected to the first electrode pin, and the upper surface electrode of the chip on another second conductive layer may also be electrically connected to the first electrode pin, but the lower surface electrode of the chip (e.g., the third surface electrode of the second chip) needs to be insulated from the first surface electrode of the first chip, a third conductive layer 6 needs to be disposed outside the chip region and near the chip, so that the third conductive layer 6 is electrically connected to the first conductive layer 21 through the second conductive through hole 24 on the insulating layer 22, so as to electrically connect the upper surface electrode of the chip to the third conductive layer 6, and thus the upper surface electrode of the chip is electrically connected to the first electrode pin. Therefore, the length of a bonding wire for electrically connecting the upper surface electrode of the chip and the first electrode pin is shortened, the parasitic parameters introduced by the bonding wire are reduced, and the parasitic parameters of the chip packaging structure are reduced.
Correspondingly, the present embodiment further provides a chip package structure, and fig. 11 is a schematic structural diagram of another chip package structure provided in the embodiment of the present invention; FIG. 12 is a schematic sectional view taken along FF' of FIG. 11. As shown in fig. 11 and 12, the chip package provided based on the above embodimentsIn this embodiment, the second chip 32 further includes a fourth surface electrode 321 disposed on the upper surface of the second chip 32, and the fourth surface electrode 321 passes through the second bonding wire L2Electrically connected to the third conductive layer 6. Thereby passing through the second bonding wire L2The fourth surface electrode 321 is directly electrically connected to the third conductive layer 6, that is, the fourth surface electrode 321 is electrically connected to the first electrode pin, and compared with the bonding wire directly electrically connecting the fourth surface electrode 321 to the first electrode pin, the second bonding wire L is2The length of the chip packaging structure is greatly shortened, so that parasitic parameters introduced by bonding wires are reduced, and the parasitic parameters of the chip packaging structure are reduced.
Optionally, based on the above embodiment, in another embodiment of the present invention, fig. 13 is a schematic structural diagram of another chip package frame provided in the embodiment of the present invention. As shown in fig. 13, the chip package frame further includes a fourth conductive layer located outside the chip region and insulated from the first sub-conductive layer.
Considering that there is a surface electrode electrically connected to other electrode pins except the first electrode pin 41 on the chip, at present, the surface electrode still needs to be directly electrically connected to the corresponding electrode pin through a bonding wire, and especially for the case that the surface electrode is far from the corresponding electrode pin due to the chip layout, the length of the corresponding bonding wire is long, which may introduce a large parasitic parameter, which seriously affects the performance of the chip. Therefore, in this embodiment, by providing the fourth conductive layer, the fourth conductive layer can be extended from the vicinity of the corresponding surface electrode to a position close to the corresponding electrode pin on the insulating layer according to the actual layout of the chip, and the surface electrode and the fourth conductive layer are electrically connected through two segments of bonding wires, and the fourth conductive layer and the corresponding electrode pin are electrically connected, so that the surface electrode and the corresponding electrode pin are electrically connected. Therefore, the bonding position of the bonding wire can be reasonably designed, so that the total length of the two segments of bonding wires is smaller than the length of the bonding wire directly connecting the surface electrode and the corresponding electrode pin, the length of the bonding wire is further shortened, and the parasitic parameters of the chip packaging structure are reduced.
In this embodiment, the fourth conductive layers corresponding to different chips may be insulated from each other, for example, the surface electrodes of different chips are connected to different electrode pins, as shown in fig. 13, the fourth conductive layer may include a third sub-conductive layer 71 and a fourth sub-conductive layer 72, and the third sub-conductive layer 71 and the fourth sub-conductive layer 72 are insulated from each other; the fourth conductive layers corresponding to different chips can also be electrically connected, for example, the surface electrodes of different chips are connected with the same electrode pin. The fourth conductive layer may be disposed according to an actual layout of the chip, as long as the total length of the bonding wire connecting the surface electrode and the fourth conductive layer and the bonding wire connecting the fourth conductive layer and the corresponding electrode pin is smaller than the length of the bonding wire directly connecting the surface electrode and the corresponding electrode pin.
Correspondingly, the present embodiment further provides a chip package structure, and fig. 14 is a schematic structural diagram of another chip package structure provided in the embodiment of the present invention. As shown in fig. 14, the fourth conductive layer includes a third sub-conductive layer 71, the at least one electrode lead 4 further includes a second electrode lead 42, the at least one surface electrode further includes a fifth surface electrode 312 disposed on the upper surface of the first chip 31, and the fifth surface electrode 312 passes through the third bonding wire L3Electrically connected to the third sub-conductive layer 71, the third sub-conductive layer 71 passing through a fourth bonding wire L4And is electrically connected to the second electrode pin 42. At this time, the third bonding line L3And a fourth bonding line L4Is less than the length of the bonding wire directly electrically connecting the fifth surface electrode 312 and the second electrode lead 42, thereby shortening the length of the bonding wire and reducing the parasitic parameters of the chip package structure.
And/or the fourth conductive layer includes a fourth sub-conductive layer 72, the at least one electrode pin 4 further includes a third electrode pin 43, the second chip 32 further includes a sixth surface electrode 322 disposed on the upper surface of the second chip 32, and the sixth surface electrode 322 passes through the fifth bonding wire L5Electrically connected to the fourth sub-conductive layer 72, the fourth sub-conductive layer 72 passing through a sixth bonding wire L6And is electrically connected to the third electrode pin 43. At this time, the fifth bonding wire L5And a sixth bonding wire L6Is less than the sum of the lengths of the direct electrical connection of the sixth surface electrode 322 and the third electrodeThe length of the bonding wire of the pole lead 43 is shortened, and thus the parasitic parameters of the chip packaging structure are reduced.
Alternatively, in the above embodiments, the first chip 31 and the second chip 32 may form a cascade chip. Illustratively, as shown in fig. 15, the first chip 31 includes a first gate G1, a first source S1 and a first drain D1 on an upper surface of the first chip 31, and a substrate electrode (not shown) on a lower surface of the first chip 31, the second chip 32 includes a second gate G2 and a second source S2 on an upper surface of the second chip 32, and a second drain (not shown) on a lower surface of the second chip 32,
specifically, referring to fig. 15 and 16, the first gate G1 of the first chip 31 is electrically connected to the second source S2 of the second chip 32, the first gate G1 of the first chip 31 and the second source S2 of the second chip 32 are both electrically connected to the source pin S of the electrode pins 4, the first source S1 of the first chip 31 is electrically connected to the second drain D2 of the second chip 32, the second gate G2 of the second chip 32 is electrically connected to the gate pin G of the pin electrode 4, and the first drain D1 of the first chip 31 is electrically connected to the drain pin D of the pin electrode 4, so that the cascade of codes of the first chip 31 and the second chip 32 is realized.
On the basis of the above embodiment, in the present embodiment, the substrate electrode of the first chip 31 is the first surface electrode in the above embodiment, the first gate G1 is the second surface electrode in the above embodiment, and the first drain D1 is the fifth surface electrode in the above embodiment; the second drain of the second chip 32 is the third surface electrode in the above embodiment, the second source S2 is the fourth surface electrode in the above embodiment, and the second gate G2 is the sixth surface electrode in the above embodiment. Thus, based on the above embodiments, by forming the first chip 31 and the second chip 32 into a cascade chip, parasitic parameters of the cascade chip can be reduced.
Optionally, a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer. Thereby, the resistance matching or the capacitance matching of the chip can be realized.
Illustratively, referring to FIG. 17, the third conductorA resistor R is electrically connected between the layer 6 and the second sub-conductive layer 52, and an equivalent circuit diagram of the chip package structure is shown in fig. 18. The second drain D2 and the second source S2 of the second chip 32 are electrically connected through a resistor R, so that a leakage path is increased, the resistance matching of the second chip 32 is optimized, and the stability of the cascode chip is improved. Optionally, the resistance of the resistor R is 107Omega or 108Omega is of order to ensure that its leakage capability is greater than the leakage between the drain and source of the second chip 32.
In addition, in another embodiment of the present invention, referring to fig. 17, a capacitor C is electrically connected between the third conductive layer 6 and the second sub-conductive layer 52, and an equivalent circuit diagram of the chip package structure is shown in fig. 19. And the capacitor C is used for matching the capacitor of the cascade chip, so that the voltage resistance of the cascade chip is improved. Optionally, the capacitance of the capacitor C is 100pF to 1000pF, and the withstand voltage is greater than 50V.
Optionally, in each of the above embodiments, the plurality of electrode pins may be located on the same side of the chip package frame, that is, a single-side pin-packaged chip package structure is formed, so that the parasitic parameters of the chip package structure are reduced, and the heat dissipation effect of the chip package structure is further improved.
In addition, in terms of semiconductor electronic devices, the AlGaN/GaN high electron mobility transistor is a wide bandgap semiconductor device with high-concentration two-dimensional electron gas, has the characteristics of high output power density, high temperature resistance, strong stability and high breakdown voltage, and has great application potential in the field of power electronic devices, and therefore, in each of the above embodiments, the first chip 31 may be an AlGaN/GaN high electron mobility transistor. In the application of power electronic devices, in order to prevent the devices from being turned on by mistake, the devices are usually required to be normally-off devices, the normally-off devices of the AlGaN/GaN high electron mobility transistors are not easy to implement, and the gate drive compatibility problem exists. Therefore, in the embodiments where the first chip 31 and the second chip 32 form a cascode cascade, the first chip 31 may be a high-voltage depletion AlGaN/GaN high electron mobility transistor, and the second chip 32 may be a low-voltage enhancement silicon field effect transistor. Therefore, the dynamic performance of the normally-off device can be ensured while the pressure resistance of the normally-off device is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (12)

1. A chip package frame, comprising:
a package base;
the substrate is arranged on the packaging base, is divided into at least one chip area and comprises a first conductive layer and an insulating layer which are stacked;
the at least one second conducting layer is arranged on the upper surface of the insulating layer, is positioned in the chip area and is in one-to-one correspondence with the chip area, wherein the at least one second conducting layer comprises a first sub-conducting layer, a first conducting through hole is formed in the insulating layer, and the first sub-conducting layer is electrically connected with the first conducting layer through the first conducting through hole;
and the at least one electrode pin is positioned on at least one side of the packaging base and comprises a first electrode pin, and the first electrode pin is electrically connected with the first conductive layer.
2. The chip package frame of claim 1, wherein the at least one second conductive layer further comprises a second sub-conductive layer insulated from the first sub-conductive layer.
3. The chip package frame according to claim 2, further comprising a third conductive layer disposed on the upper surface of the insulating layer outside the chip area, wherein a second conductive via is disposed on the insulating layer, and the third conductive layer is electrically connected to the first conductive layer through the second conductive via.
4. The chip package frame according to any one of claims 1-3, further comprising a fourth conductive layer outside the chip area and insulated from the first sub-conductive layer.
5. A chip packaging structure, comprising at least one chip and the chip packaging frame according to any one of claims 1 to 4;
the chip is attached to the chip packaging frame, and chip electrodes of the chip are electrically connected with corresponding electrode pins respectively;
the at least one chip comprises a first chip, the first chip is attached to the first sub-conducting layer, and at least one surface electrode of the first chip is electrically connected with the first sub-conducting layer.
6. The chip package structure according to claim 5, wherein the at least one surface electrode comprises a first surface electrode disposed on the lower surface of the first chip, the first surface electrode being in electrical contact with the first sub-conductive layer.
7. The chip package structure according to claim 5, wherein an area of the first sub-conductive layer is larger than an area occupied by the first chip, the at least one surface electrode includes a second surface electrode disposed on the first chip upper surface, and the second surface electrode is electrically connected to a portion of the first sub-conductive layer outside an area where the first chip is located through a first bonding wire.
8. The chip packaging structure according to claim 5, wherein the at least one second conductive layer further comprises a second sub-conductive layer insulated from the first sub-conductive layer;
the at least one chip further comprises a second chip, the second chip is attached to the second sub-conducting layer, the second chip comprises a third surface electrode arranged on the lower surface of the second chip, and the third surface electrode is in electric contact with the second sub-conducting layer.
9. The chip package structure according to claim 8, wherein the chip package frame further comprises a third conductive layer disposed on the upper surface of the insulating layer outside the chip area, the insulating layer having a second conductive via disposed thereon, the third conductive layer being electrically connected to the first conductive layer through the second conductive via;
the second chip further comprises a fourth surface electrode arranged on the upper surface of the second chip, and the fourth surface electrode is electrically connected with the third conductive layer through a second bonding wire.
10. The chip package structure according to claim 9, wherein the chip package frame further comprises a fourth conductive layer located outside the chip area and insulated from the first sub-conductive layer;
the fourth conducting layer comprises a third sub-conducting layer, the at least one electrode pin further comprises a second electrode pin, the at least one surface electrode further comprises a fifth surface electrode arranged on the upper surface of the first chip, the fifth surface electrode is electrically connected with the third sub-conducting layer through a third bonding wire, and the third sub-conducting layer is electrically connected with the second electrode pin through a fourth bonding wire; and/or the fourth conducting layer comprises a fourth sub-conducting layer, the at least one electrode pin further comprises a third electrode pin, the second chip further comprises a sixth surface electrode arranged on the upper surface of the second chip, the sixth surface electrode is electrically connected with the fourth sub-conducting layer through a fifth bonding wire, and the fourth sub-conducting layer is electrically connected with the third electrode pin through a sixth bonding wire.
11. The chip package structure according to claim 9, wherein a resistor or a capacitor is electrically connected between the third conductive layer and the second sub-conductive layer.
12. The chip packaging structure according to claim 8, wherein the first chip and the second chip form a cascade.
CN202010182721.4A 2020-03-16 2020-03-16 Chip packaging frame and chip packaging structure Active CN113410200B (en)

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