WO2018091852A1 - Integrated circuit formed by two chips that are connected in series - Google Patents

Integrated circuit formed by two chips that are connected in series Download PDF

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Publication number
WO2018091852A1
WO2018091852A1 PCT/FR2017/053167 FR2017053167W WO2018091852A1 WO 2018091852 A1 WO2018091852 A1 WO 2018091852A1 FR 2017053167 W FR2017053167 W FR 2017053167W WO 2018091852 A1 WO2018091852 A1 WO 2018091852A1
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WIPO (PCT)
Prior art keywords
integrated circuit
chip
gate
contact
terminal
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Application number
PCT/FR2017/053167
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French (fr)
Inventor
Laurent Guillot
Domenico Lo Verde
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Exagan
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Publication of WO2018091852A1 publication Critical patent/WO2018091852A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4811—Connecting to a bonding area of the semiconductor or solid-state body located at the far end of the body with respect to the bonding area outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • the present invention relates to an integrated circuit comprising a chip formed of a high voltage transistor in depletion mode and a chip formed of a transistor in enrichment mode, connected in series.
  • HEMT transistors high electron mobility transistors produced on III-N semiconductor materials are conventionally "normally on”, that is to say they have a negative threshold voltage and can conduct current with a gate voltage at 0V. These components with negative threshold voltages are called depletion mode components ("depletion mode” or “D-mode” according to the English terminology).
  • E-mode Enrichment Mode
  • Such a hybrid device typically comprises a D-mode HEMT transistor developed on III-N semiconductor materials and a transistor MOSFET (E-mode metal / oxide / semiconductor field effect transistor) developed on silicon. For example, as illustrated in FIG.
  • chips 1,2 respectively comprising the components HEMT and MOSFET can be coupled to form a cascode 3 type integrated circuit: the drain 2a and the source 2b of the MOSFET chip E-mode 2 are respectively connected to the source 1b and the gate 1a of the HEMT D-mode 1 chip; this electrical connection is made in the case 4 of the integrated circuit 3 comprising the two electronic chips 1,2, usually by wire connection 5 ("wire bonding" according to the English terminology) between different grid contact pads 1c, 2c, source lb, 2b and drain 1a, 2a accessible on each of the chips 1, 2.
  • wire connection 5 wire bonding
  • the gate contact pad 2c of the MOSFET chip 2 is connected in the housing 4 of the integrated circuit 3 to a gate pin 3c.
  • the source contact pad 2b of the MOSFET chip 2 is connected in the box 4 to a source pin 3b.
  • the drain contact pad of the chip HEMT 1 is connected, still in the housing 4, to a drain pin 3a.
  • the connections between the contact pads of the chips and the pins are made by wire connection or by means of electrical connection clips.
  • the three pins 3a, 3b, 3c constitute the electrical terminals of the integrated circuit 3 towards the outside of the housing 4.
  • the interconnections in particular the wired connections
  • fast switching is one of the expected advantages of a HEMT chip.
  • it is therefore necessary to minimize the inductances and parasitic resistances related to the interconnections in a cascode arrangement.
  • Document US9171837 presents a solution for reducing the inductances in a box with three electrical terminals, implementing a cascode integrated circuit comprising a substrate on which a first depletion mode transistor and a second MOSFET transistor are mounted; the substrate comprises conductive tracks providing the connection between the source of the first transistor and the drain of the second transistor.
  • An object of the present invention is to propose an alternative solution to the solutions of the state of the art.
  • An object of the invention is notably to propose an integrated circuit comprising an interconnection substrate, a chip formed of a high voltage transistor in depletion mode and a chip formed of a transistor in enrichment mode, in which the inductances and parasitic resistance related to interconnections are reduced.
  • the present invention relates to an integrated circuit comprising:
  • a box comprising at least three electrical terminals, a gate terminal, a source terminal and a drain terminal, and comprising a conductive structural plate connected to one of the three terminals,
  • An interconnection substrate having a front face and a rear face disposed on the structural plate
  • the integrated circuit is remarkable in that: • The first and second contact pads, respectively formed on a front face of the first chip and on a front face of the second chip, are in contact with conductive tracks formed on the front face interconnect substrate; at least one conductive track being configured to connect the first source contact pad with the second drain contact pad;
  • the interconnect substrate comprises at least one through conductive via to connect at least one determined conductive track with the structural plate.
  • the determined conductive track is the one in contact with the second source contact pad, the terminal of the box connected to the structural plate forming the source terminal of the integrated circuit;
  • the conductive track in contact with the first drain contact pad and the conductive track in contact with the second gate contact pad are respectively connected to the drain terminal and to the gate terminal of the box;
  • connections between the conductive tracks and the drain and gate terminals are made by means of electrical connection clips
  • the determined conductive track is the one in contact with the first drain contact pad, the terminal of the box connected to the structural plate forming the drain terminal of the integrated circuit; the conductive track in contact with the second gate contact pad and the conductive track in contact with the second source contact pad are respectively connected to the gate terminal and the source terminal of the housing;
  • connections between the conductive tracks and the gate and source terminals are made by means of electrical connection clips
  • At least one conductive track is configured to connect the first gate contact pad with the second source contact pad to connect the first and second cascode chips
  • the conductive track in contact with the first gate contact pad is connected to an additional terminal of the housing;
  • the enrichment mode device included in the second chip comprises an enhancement mode transistor having a gate electrode connected to the gate contact pad of the second chip;
  • the enrichment mode device included in the second chip comprises an enhancement mode transistor and a control component, a gate electrode of the enhancement mode transistor being connected to an input of the control component and an output of the control component being connected to the grid contact pad of the second chip;
  • the integrated circuit comprises a third chip comprising a passive or active component
  • the third chip comprises a high voltage transistor in depletion mode, and third gate, source and drain contact pads; the third contact pads formed on a front face of the third chip, being in contact with conductive tracks formed on the front face of the interconnect substrate; the conductive tracks being configured to connect the first and third chips in parallel.
  • FIG. 1 shows an integrated circuit in a box according to the state of the art
  • FIGS. 2a to 2c show elements of the integrated circuit according to the invention
  • FIG. 3 shows a sectional view of an integrated circuit according to the invention
  • Figures 4a to 4d show sectional views of a first embodiment of the integrated circuit according to the invention
  • FIG. 5 shows a sectional view of a second embodiment of the invention.
  • the figures are schematic representations which, for purposes of readability, are not to scale.
  • the thicknesses of the layers or components along the z axis are not scaled with respect to the lateral dimensions along the x and y axes.
  • the sectional views may in certain cases represent elements included in several vertical planes (plane (y, z) in the figures) different.
  • the invention relates to an integrated circuit 100 comprising a housing 10, an insulating portion 15 for encapsulating the electronic components of the integrated circuit is formed by an electrical insulating material, typically resin.
  • the box 10 comprises at least three electrical terminals, a gate terminal 11, a source terminal 12 and a drain terminal 13, as illustrated in FIG. 2a.
  • electrical terminal is meant in particular a pin or a metal pad or any other means for forming an external electrical contact of the integrated circuit 100: this external contact may then be connected to other elements, for example on a printed circuit.
  • the housing 10 also comprises a conductive structural plate 14.
  • the structural plate 14 is intended to support the electronic components of the integrated circuit 100.
  • the structural plate 14 is connected to one of the three terminals 11, 12, 13; in the case illustrated in FIG. 2a, the structural plate 14 is connected to the source terminal 12.
  • by “connected” is meant electrically connected: either directly, that is to say by direct contact between the two elements connected, either indirectly, that is to say by means of an intermediate element, itself in contact with the electrically connected elements; said intermediate element may for example be an electrical connection clip or one or a plurality of connection (s) wire (s).
  • the structural plate 14 is usually encapsulated, as are the electronic components of the integrated circuit 100, in the insulating part 15 of the housing 10.
  • the integrated circuit 100 also comprises an interconnection substrate 20 having a front face 21 and a rear face 22.
  • the interconnection substrate 20 is composed of a base 23 formed by an electrical insulating material and having, for example, a plate shape ( Figure 2b).
  • the insulating material of the base 23 is chosen from ceramics, such as aluminum nitride, or other suitable materials.
  • the interconnection substrate 20 comprises conductive tracks 24 on its front face 21, which extend on the base 23.
  • FIG. 2b is a diagrammatic representation which in no way limits the configurations or distributions in the plane (x, y) that can be adopted for conduction tracks 24.
  • These may be formed by a metallic material such as copper or other suitable materials.
  • the interconnection substrate 20 further comprises at least one via via 25, that is to say going from the front face 21 to the rear face 22 of the interconnection substrate 20, to 23.
  • the conductive via 25 may for example be formed by a material such as copper or other suitable materials.
  • the interconnection substrate 20 also comprises a conductive pad 26 on its rear face 22, in contact with the conductive via 25.
  • the interconnection substrate 20 is arranged on the structural plate In particular, the conductive pad 26 is in direct contact with or assembled by means of an electrically conductive material on the structural plate 14: thus the conductive via 25 makes it possible to connect at least one determined conductive track 24a with the structural plate. 14.
  • connection via at least one conductive via 25 makes it possible to significantly reduce the connection length between the determined conductive track 24a (which is intended to be in contact with at least one contact pad of the first 30 and / or the second 40 chip) and the structural plate 14 electrically connected to a terminal of the integrated circuit 100.
  • the inductors and parasitic resistances being proportional to the geometry of the connection for a given conductive material, the reduction of the connection length results in particular in a reduction of these parasitic elements. In addition, it can also result in a reduction of electromagnetic interference (EMI) emissions.
  • EMI electromagnetic interference
  • the integrated circuit 100 comprises at least a first chip 30 comprising a high voltage transistor in depletion mode, and at least a second chip 40 comprising a device in enrichment mode.
  • the high-voltage transistor in depletion mode may consist of a HEMT transistor developed on GaN.
  • the device in enrichment mode may consist of a field effect MOS transistor (MOSFET) developed on silicon; it may also consist of a device comprising a MOSFET coupled with a control component (driver).
  • MOSFET field effect MOS transistor
  • the first chip 30 and the second chip 40 respectively comprise first gate contact pads 31, source 32 and drain 33, and second gate contact pads 41, source 42 and drain 43. These first and second contact pads are respectively formed on the front face 34 of the first chip 30 and the front face 44 of the second chip 40 ( Figure 2c).
  • the contact pads are composed of an electrically conductive metallic material, for example copper or other suitable materials. In particular, the metal material forming the contact pads is able to be assembled or welded.
  • the contact pads of a chip according to the invention may be in various forms: either in the form of raised blocks with respect to the surface of the front face of the chip, or in the form of balls ("bumps" according to the English terminology) also in the form of relief relative to the surface of the front face of the chip.
  • the first 31,32,33 and second contact pads 41,42,43 may be arranged in different ways on the respective front faces 34,44 of the first 30 and second 40 chips, according to the different embodiments and variants according to the invention. 'invention.
  • the first chip 30 and the second chip 40 are disposed on the interconnection substrate 20, in particular according to the invention, their front faces 34,44 are vis-à-vis with the front face 21 of the interconnection substrate 20 the first 31,32,33 and second contact pads 41,42,43 are in contact with the conductive tracks 24 of the interconnection substrate 20.
  • the assembly of the first 31,32,33 and second 41,42,43 pads on the conductive tracks 24 may be achieved by a metal bonding method for example by thermo-compression or a welding process or soldering between the materials forming the contact pads and the conductive tracks. It is thus possible to obtain a good quality electrical contact between the contact pads of the chips 30, 40 and the interconnection substrate 20, with a greatly reduced conduction path, for example with respect to wire connections.
  • At least one conductive track 24b is configured to connect the first source contact pad 32 with the second drain contact pad 43: such a configuration enables the high-voltage transistor to be put in series in depletion mode and the device enrichment mode, according to an arrangement said cascade.
  • FIG. 3 illustrates a sectional view of an integrated circuit 100 according to the invention.
  • the first contact pads 31, 32, 33 of the first chip 30 and the second contact pads 41, 42, 43 of the second chip 40 are in contact with the conductive tracks 24 (including in particular the tracks referenced 24a, 24b) of the interconnection substrate 20.
  • the conductive via 25 electrically connects the conductive track 24a and the conductive pad 26 on the rear face of the interconnection substrate 20.
  • the conductive pad 26 is assembled by metal bonding, soldering or brazing on the structural plate 14, also establishing with it an electrical contact.
  • Figure 3 does not show the insulating portion 15 of the housing 10, nor the at least three electrical terminals 11,12,13.
  • the conductive track 24b connecting the first source contact pad 32 and the second drain contact pad 43 is not entirely visible: it extends in the plane (x, y) perpendicular to the sectional plane of Figure 3, to form the electrical connection between the two contact pads 32,43.
  • the determined conductive track 24a is the one in contact with the second source contact pad 42, the terminal of the box connected to the structural plate 14 then forms the source terminal 12 of the integrated circuit 100.
  • a conductive track 24c in contact with the first drain contact pad 33 and another conductive track 24d in contact with the second gate contact pad 41 are respectively connected to the drain terminal 13 (not shown in FIG. 4a) and to the gate terminal 11 of the box 10 of the integrated circuit 100.
  • the gate terminal 11 is represented in FIG. 4a in the same section plane as the source terminal 12 for more readability; in fact, it is situated in a neighboring plane (y, z), in accordance with the diagram of FIG. 2a.
  • connections between the conductive tracks 24 and the drain terminals 13 and gate 11 are formed by means of electrical connection clips 16.
  • the electrical connection clips 16 are usually formed by metal strips, for example copper, aluminum or other suitable material, welded to one and the other of the elements to be connected. They have the advantage of a low inductance and a low resistance of access, compared to wired connections.
  • a conductive track 24e in contact with the first gate contact pad 31 is connected to an additional terminal 111 of the box 10.
  • the box 10 comprises in this case four electrical terminals, the three previously mentioned and an additional gate terminal 111, for independently controlling the gate of the high voltage transistor in depletion mode of the first chip 30 (connected to the additional terminal 111), and the gate of the device in enrichment mode of the second chip 40 (connected to the gate terminal 11).
  • the additional grid terminal 111 is shown in Figure 4b in the same section plane as the source terminal 12 for more readability; in reality it is located in a vertical plane (y, z) neighbor.
  • the box 10 comprises only three terminals 11, 12, 13 and at least one conductive track 24 is configured to connect the first contact pad gate 31 with the second source contact pad 42: in the example of FIG. 4c, this means that the conductive track 24e is connected to the track 24a, in the plane (x, y) on the front face 21 of the substrate 20.
  • the conductive track 24e in contact with the first gate contact pad 31 is connected to the rear face 35 of the first chip 30, by means of an electrical connection clip 17, to put said face back to the ground.
  • This clip 17 has the additional advantage of promoting heat dissipation at the rear face 35 of the first chip 30.
  • the housing 10 has only three terminals 11, 12, 13 and the determined conductive track 24 a is configured to connect the first contact pad of gate 31 with the second source contact pad 42.
  • a conductive via 25 or a plurality of conductive vias 25 connects the determined conducting track 24a and the conductive pad 26 on the rear face of the interconnection substrate 20.
  • the track conductive 24a in contact with the first gate contact pad 31 is connected to the rear face 35 of the first chip 30, by means of an electrical connection clip 17 (not shown), for putting said rear face 35 to ground .
  • the determined conductive track 24a is the one in contact with the first stud of drain contact 33, the terminal of the box connected to the structural plate 14 then forms the drain terminal 13 of the integrated circuit 100.
  • the conductive track 24d in contact with the second gate contact pad 41 and a 24f conductive track in contact with the second source contact pad 42 are respectively connected to the gate terminal 11 and the source terminal 12 (not shown) of the housing 10 of the integrated circuit 100.
  • connection between the conductive tracks 24d, 24f and the gate terminals 11 and source 12 are made by means of electrical connection clips 16 having the advantage of a low inductance and a low access resistance, compared to wired connections.
  • the conductive track 24e in contact with the first gate contact pad 31 is connected to an additional terminal of the housing 10 (not shown).
  • the box 10 comprises in this case four electrical terminals, the three previously mentioned and an additional gate terminal, for independently controlling the gate of the high voltage transistor in depletion mode of the first chip 30 (connected to the additional terminal), and the gate the device in enrichment mode of the second chip 40 (connected to the gate terminal 11).
  • the housing 10 comprises only three terminals 11, 12, 13 and at least one conductive track 24 is configured to connect the first gate contact pad 31 with the second source contact pad 42: in the example of FIG. 5, this means that the conductive track 24e is connected to the track 24f, in the plane (x, y) on the front face 21 of the interconnection substrate 20.
  • the conductive track 24e in contact with the first gate stud 31 is connected to the rear face 35 of the first chip 30 (not shown), by means of an electrical connection clip 17, to put said rear face 35 to ground.
  • the enrichment mode device included in the second chip 40 may comprise an enhancement mode transistor including a gate electrode is connected to the second gate contact pad 41 of the second chip 40.
  • the gate terminal 11 of the box 10, connected to the second gate contact pad 41 then makes it possible to send an electrical signal for controlling the gate of the transistor in enrichment mode (for example, a silicon MOSFET).
  • the enrichment mode device included in the second chip 40 may comprise an enhancement mode transistor and a control component: in this case, a gate electrode of the enhancement mode transistor is connected to an input of the control component and a output of the control component is connected to the second gate contact pad 41 of the second chip 40.
  • the gate terminal 11 of the housing 10, connected to the second gate contact pad 41 here makes it possible to send an electrical signal to the component of ordered ; the latter is then able to process this signal to control the gate of the transistor in enrichment mode.
  • the integrated circuit 100 may comprise, in addition to the first 30 and the second chip 40, a third chip comprising a passive or active component.
  • the third chip may comprise a high voltage transistor in depletion mode, and third gate, source and drain contact pads.
  • the third contact pads formed on a front face of the third chip are in contact with conductive tracks 24 formed on the front face 21 of the interconnection substrate 20: said conductive tracks 24 are configured to connect the first 30 and the third chip in parallel.
  • Such a configuration has the particular advantage of minimizing the interconnections and thus reduce parasitic inductances and resistances as well as emissions of EMI.

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  • General Physics & Mathematics (AREA)
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Abstract

The invention relates to an integrated circuit comprising: a package including at least three electrical terminals, a gate terminal, a source terminal and a drain terminal, and including a conductive structural plate connected to one of the three terminals; an interconnecting substrate having a front side and a back side which is placed on the structural plate; and, placed on the interconnecting substrate, at least one first chip comprising a high-voltage depletion-mode transistor, and at least one second chip comprising an enhancement-mode device, the first and second chips including first and second drain, source and gate contact pads, respectively; this integrated circuit is noteworthy in that: the first and second contact pads, respectively formed on a front side of the first chip and on a front side of the second chip, make contact with conductive tracks formed on the front side of the interconnecting substrate; at least one conductive track being configured so as to connect the first source contact pad with the second drain contact pad; the interconnecting substrate comprises at least one conductive through-via for connecting at least one defined conductive track to the structural plate.

Description

CIRCUIT INTEGRE FORME DE DEUX PUCES CONNECTEES EN SERIE  INTEGRATED CIRCUIT FORMED OF TWO CHIPS CONNECTED IN SERIES
DOMAINE DE L' INVENTION FIELD OF THE INVENTION
La présente invention concerne un circuit intégré comprenant une puce formée d'un transistor à haute tension en mode déplétion et une puce formée d'un transistor en mode enrichissement, connectées en série. The present invention relates to an integrated circuit comprising a chip formed of a high voltage transistor in depletion mode and a chip formed of a transistor in enrichment mode, connected in series.
ARRIERE PLAN TECHNOLOGIQUE DE L' INVENTION BACKGROUND OF THE INVENTION
Les transistors HEMT (transistors à haute mobilité électronique) élaborés sur des matériaux semi-conducteurs III- N sont classiquement « normally on », c'est-à-dire qu'ils présentent une tension de seuil négative et peuvent conduire le courant avec une tension de grille à 0V. Ces composants avec tensions de seuil négatives sont appelés composants en mode déplétion (« depletion mode » ou « D-mode » selon la terminologie anglo-saxonne) . HEMT transistors (high electron mobility transistors) produced on III-N semiconductor materials are conventionally "normally on", that is to say they have a negative threshold voltage and can conduct current with a gate voltage at 0V. These components with negative threshold voltages are called depletion mode components ("depletion mode" or "D-mode" according to the English terminology).
Il est préférable pour les applications d'électronique de puissance d'avoir des composants dits « normally off », c'est-à-dire présentant une tension de seuil positive : ces composants ne peuvent pas conduire le courant lorsque la tension de grille est à 0V et sont communément appelés composants en mode enrichissement (« E-mode ») .  It is preferable for power electronics applications to have so-called "normally off" components, that is, having a positive threshold voltage: these components can not conduct the current when the gate voltage is at 0V and are commonly referred to as Enrichment Mode ("E-mode") components.
La fabrication de composants à haute tension sur matériaux semi-conducteurs III-N en E-mode s'avère complexe. Une alternative à un composant E-mode haute tension simple est de combiner un composant D-mode à haute tension avec un composant E-mode. Un tel dispositif hybride comprend typiquement un transistor HEMT D-mode élaboré sur matériaux semi-conducteurs III-N et un transistor MOSFET (Transistor métal/oxyde/semi-conducteur à effet de champ) E-mode élaboré sur silicium. Par exemple, comme illustré sur la figure 1, des puces 1,2 comprenant respectivement les composants HEMT et MOSFET peuvent être couplées pour former un circuit intégré de type cascode 3 : le drain 2a et la source 2b de la puce MOSFET E- mode 2 sont respectivement connectés à la source lb et à la grille le de la puce HEMT D-mode 1 ; cette connexion électrique se fait dans le boitier 4 du circuit intégré 3 comprenant les deux puces électroniques 1,2, habituellement par connexion filaire 5 (« wire bonding » selon la terminologie anglo-saxonne) entre différents plots de contact de grille le, 2c, de source lb,2b et de drain la, 2a accessibles sur chacune des puces 1,2. Dans un circuit intégré cascode 3, la grille 2c de la puce MOSFET 2 contrôle la mise en mode passant ou bloquant du circuit intégré 3. The manufacture of high voltage components on III-N semiconductor materials in E-mode is complex. An alternative to a simple high voltage E-mode component is to combine a high voltage D-mode component with an E-mode component. Such a hybrid device typically comprises a D-mode HEMT transistor developed on III-N semiconductor materials and a transistor MOSFET (E-mode metal / oxide / semiconductor field effect transistor) developed on silicon. For example, as illustrated in FIG. 1, chips 1,2 respectively comprising the components HEMT and MOSFET can be coupled to form a cascode 3 type integrated circuit: the drain 2a and the source 2b of the MOSFET chip E-mode 2 are respectively connected to the source 1b and the gate 1a of the HEMT D-mode 1 chip; this electrical connection is made in the case 4 of the integrated circuit 3 comprising the two electronic chips 1,2, usually by wire connection 5 ("wire bonding" according to the English terminology) between different grid contact pads 1c, 2c, source lb, 2b and drain 1a, 2a accessible on each of the chips 1, 2. In a cascode 3 integrated circuit, the gate 2c of the MOSFET chip 2 controls the setting in or out of the integrated circuit 3.
Le plot de contact de grille 2c de la puce MOSFET 2 est connecté dans le boitier 4 du circuit intégré 3 à une broche de grille 3c. Le plot de contact de source 2b de la puce MOSFET 2 est connecté dans le boitier 4 à une broche de source 3b. Enfin, le plot de contact de drain de la puce HEMT 1 est connecté, toujours dans le boitier 4, à une broche de drain 3a. Habituellement, les connexions entre les plots de contact des puces et les broches sont faits par connexion filaire ou à l'aide de clips de raccordement électrique. Les trois broches 3a, 3b, 3c constituent les terminaux électriques du circuit intégré 3 vers l'extérieur du boitier 4.  The gate contact pad 2c of the MOSFET chip 2 is connected in the housing 4 of the integrated circuit 3 to a gate pin 3c. The source contact pad 2b of the MOSFET chip 2 is connected in the box 4 to a source pin 3b. Finally, the drain contact pad of the chip HEMT 1 is connected, still in the housing 4, to a drain pin 3a. Usually, the connections between the contact pads of the chips and the pins are made by wire connection or by means of electrical connection clips. The three pins 3a, 3b, 3c constitute the electrical terminals of the integrated circuit 3 towards the outside of the housing 4.
Dans un circuit intégré de type cascode, les interconnexions (notamment les connexions filaires) entre les différents composants vont ralentir la vitesse de commutation, alors qu'une commutation rapide est un des avantages attendus d'une puce HEMT. Pour conserver des vitesses de commutation importantes, il est donc nécessaire de minimiser les inductances et résistances parasites liées aux interconnexions dans un arrangement cascode.  In a cascode type integrated circuit, the interconnections (in particular the wired connections) between the different components will slow down the switching speed, whereas fast switching is one of the expected advantages of a HEMT chip. To maintain high switching speeds, it is therefore necessary to minimize the inductances and parasitic resistances related to the interconnections in a cascode arrangement.
Le document US9171837 présente une solution pour réduire les inductances dans un boitier à trois terminaux électriques, mettant en œuvre un circuit intégré cascode comprenant un substrat sur lequel un premier transistor en mode déplétion et un second transistor MOSFET sont montés ; le substrat comprend des pistes conductrices procurant la connexion entre la source du premier transistor et le drain du second transistor. Document US9171837 presents a solution for reducing the inductances in a box with three electrical terminals, implementing a cascode integrated circuit comprising a substrate on which a first depletion mode transistor and a second MOSFET transistor are mounted; the substrate comprises conductive tracks providing the connection between the source of the first transistor and the drain of the second transistor.
OBJET DE L' INVENTION OBJECT OF THE INVENTION
Un objet de la présente invention est de proposer une solution alternative aux solutions de l'état de l'art. Un objet de l'invention est notamment de proposer un circuit intégré comprenant un substrat d' interconnexion, une puce formée d'un transistor à haute tension en mode déplétion et une puce formée d'un transistor en mode enrichissement, dans lequel les inductances et résistances parasites liées aux interconnexions sont réduites. An object of the present invention is to propose an alternative solution to the solutions of the state of the art. An object of the invention is notably to propose an integrated circuit comprising an interconnection substrate, a chip formed of a high voltage transistor in depletion mode and a chip formed of a transistor in enrichment mode, in which the inductances and parasitic resistance related to interconnections are reduced.
BREVE DESCRIPTION DE L' INVENTION La présente invention concerne un circuit intégré comprenant : BRIEF DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit comprising:
• un boitier comportant au moins trois terminaux électriques, un terminal de grille, un terminal de source et un terminal de drain, et comportant une plaque structurelle conductrice connectée à l'un des trois terminaux,  A box comprising at least three electrical terminals, a gate terminal, a source terminal and a drain terminal, and comprising a conductive structural plate connected to one of the three terminals,
• un substrat d' interconnexion présentant une face avant et une face arrière disposée sur la plaque structurelle, An interconnection substrate having a front face and a rear face disposed on the structural plate,
• et, disposées sur le substrat d'interconnexion, au moins une première puce comprenant un transistor à haute tension en mode déplétion, et au moins une deuxième puce comprenant un dispositif en mode enrichissement, la première et la deuxième puces comportant respectivement des premiers et des deuxièmes plots de contact de grille, de source et de drain; Le circuit intégré est remarquable en ce que : • Les premiers et deuxièmes plots de contacts, respectivement formés sur une face avant de la première puce et sur une face avant de la deuxième puce, sont en contact avec des pistes conductrices formées sur la face avant du substrat d' interconnexion ; au moins une piste conductrice étant configurée de manière à connecter le premier plot de contact de source avec le deuxième plot de contact de drain; And disposed on the interconnection substrate, at least a first chip comprising a high voltage transistor in depletion mode, and at least a second chip comprising an enrichment mode device, the first and the second chips respectively comprising first and second chips; second gate, source and drain contact pads; The integrated circuit is remarkable in that: • The first and second contact pads, respectively formed on a front face of the first chip and on a front face of the second chip, are in contact with conductive tracks formed on the front face interconnect substrate; at least one conductive track being configured to connect the first source contact pad with the second drain contact pad;
· Le substrat d'interconnexion comprend au moins un via conducteur traversant pour connecter au moins une piste conductrice déterminée avec la plaque structurelle.  · The interconnect substrate comprises at least one through conductive via to connect at least one determined conductive track with the structural plate.
Selon d'autres caractéristiques avantageuses et non limitatives de l'invention, prises seules ou selon toute combinaison techniquement réalisable : According to other advantageous and nonlimiting features of the invention, taken alone or in any technically feasible combination:
• la piste conductrice déterminée est celle en contact avec le deuxième plot de contact de source, le terminal du boitier connecté à la plaque structurelle formant le terminal de source du circuit intégré ; The determined conductive track is the one in contact with the second source contact pad, the terminal of the box connected to the structural plate forming the source terminal of the integrated circuit;
• la piste conductrice en contact avec le premier plot de contact de drain et la piste conductrice en contact avec le deuxième plot de contact de grille sont respectivement connectées au terminal de drain et au terminal de grille du boitier ;  The conductive track in contact with the first drain contact pad and the conductive track in contact with the second gate contact pad are respectively connected to the drain terminal and to the gate terminal of the box;
• les connexions entre les pistes conductrices et les terminaux de drain et de grille sont réalisées au moyen de clips de raccordement électrique ;  The connections between the conductive tracks and the drain and gate terminals are made by means of electrical connection clips;
• la piste conductrice déterminée est celle en contact avec le premier plot de contact de drain, le terminal du boitier connecté à la plaque structurelle formant le terminal de drain du circuit intégré ; la piste conductrice en contact avec le deuxième plot de contact de grille et la piste conductrice en contact avec le deuxième plot de contact de source sont respectivement connectées au terminal de grille et au terminal de source du boitier ; The determined conductive track is the one in contact with the first drain contact pad, the terminal of the box connected to the structural plate forming the drain terminal of the integrated circuit; the conductive track in contact with the second gate contact pad and the conductive track in contact with the second source contact pad are respectively connected to the gate terminal and the source terminal of the housing;
les connexions entre les pistes conductrices et les terminaux de grille et de source sont réalisées au moyen de clips de raccordement électrique ; the connections between the conductive tracks and the gate and source terminals are made by means of electrical connection clips;
au moins une piste conductrice est configurée de manière à connecter le premier plot de contact de grille avec le deuxième plot de contact de source, pour connecter la première et la deuxième puce en cascode ; at least one conductive track is configured to connect the first gate contact pad with the second source contact pad to connect the first and second cascode chips;
la piste conductrice en contact avec le premier plot de contact de grille est connectée à un terminal additionnel du boitier ; the conductive track in contact with the first gate contact pad is connected to an additional terminal of the housing;
le dispositif en mode enrichissement inclus dans la deuxième puce comprend un transistor en mode enrichissement dont une électrode de grille est connectée au plot de contact de grille de la deuxième puce ; the enrichment mode device included in the second chip comprises an enhancement mode transistor having a gate electrode connected to the gate contact pad of the second chip;
le dispositif en mode enrichissement inclus dans la deuxième puce comprend un transistor en mode enrichissement et un composant de commande, une électrode de grille du transistor en mode enrichissement étant connectée à une entrée du composant de commande et une sortie du composant de commande étant connectée au plot de contact de grille de la deuxième puce ; the enrichment mode device included in the second chip comprises an enhancement mode transistor and a control component, a gate electrode of the enhancement mode transistor being connected to an input of the control component and an output of the control component being connected to the grid contact pad of the second chip;
le circuit intégré comprend une troisième puce comportant un composant passif ou actif ; the integrated circuit comprises a third chip comprising a passive or active component;
la troisième puce comporte un transistor à haute tension en mode déplétion, et des troisièmes plots de contact de grille, de source et de drain ; les troisièmes plots de contacts formés sur une face avant de la troisième puce, étant en contact avec des pistes conductrices formées sur la face avant du substrat d' interconnexion ; les pistes conductrices étant configurées de manière à connecter la première et la troisième puce en parallèle. the third chip comprises a high voltage transistor in depletion mode, and third gate, source and drain contact pads; the third contact pads formed on a front face of the third chip, being in contact with conductive tracks formed on the front face of the interconnect substrate; the conductive tracks being configured to connect the first and third chips in parallel.
BREVE DESCRIPTION DES DESSINS BRIEF DESCRIPTION OF THE DRAWINGS
D'autres caractéristiques et avantages de l'invention ressortiront de la description détaillée qui va suivre en référence aux figures annexées sur lesquelles : Other features and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:
la figure 1 présente un circuit intégré dans un boitier selon l'état de la technique ;  FIG. 1 shows an integrated circuit in a box according to the state of the art;
les figures 2a à 2c présentent des éléments du circuit intégré conforme à l'invention ;  FIGS. 2a to 2c show elements of the integrated circuit according to the invention;
- la figure 3 présente une vue en coupe d'un circuit intégré conforme à l'invention ;  - Figure 3 shows a sectional view of an integrated circuit according to the invention;
les figures 4a à 4d présentent des vues en coupe d'un premier mode de réalisation du circuit intégré selon 1 ' invention ;  Figures 4a to 4d show sectional views of a first embodiment of the integrated circuit according to the invention;
- la figure 5 présente une vue en coupe d'un deuxième mode de réalisation selon l'invention.  - Figure 5 shows a sectional view of a second embodiment of the invention.
DESCRIPTION DETAILLEE DE L' INVENTION DETAILED DESCRIPTION OF THE INVENTION
Dans la partie descriptive, les mêmes références sur les figures pourront être utilisées pour des éléments de même nature . In the descriptive part, the same references in the figures can be used for elements of the same nature.
Les figures sont des représentations schématiques qui, dans un objectif de lisibilité, ne sont pas à l'échelle. En particulier, les épaisseurs des couches ou des composants selon l'axe z ne sont pas à l'échelle par rapport aux dimensions latérales selon les axes x et y. Par ailleurs, pour permettre une visualisation plus aisée des connexions dans le circuit intégré selon l'invention, les vues en coupe pourront dans certains cas représenter des éléments compris dans plusieurs plans verticaux (plan (y,z) sur les figures) différents . The figures are schematic representations which, for purposes of readability, are not to scale. In particular, the thicknesses of the layers or components along the z axis are not scaled with respect to the lateral dimensions along the x and y axes. Moreover, to allow an easier visualization of the connections in the integrated circuit according to the invention, the sectional views may in certain cases represent elements included in several vertical planes (plane (y, z) in the figures) different.
L'invention concerne un circuit intégré 100 comprenant un boitier 10 dont une partie isolante 15 destinée à encapsuler les composants électroniques du circuit intégré est formée par un matériau isolant électrique, typiquement de la résine. Le boitier 10 comporte au moins trois terminaux électriques, un terminal de grille 11, un terminal de source 12 et un terminal de drain 13, comme illustré sur la figure 2a. Par terminal électrique, on entend notamment une broche ou un plot métallique ou tout autre moyen permettant de former un contact électrique externe du circuit intégré 100 : ce contact externe pourra ensuite être connecté à d'autres éléments, par exemple sur un circuit imprimé. The invention relates to an integrated circuit 100 comprising a housing 10, an insulating portion 15 for encapsulating the electronic components of the integrated circuit is formed by an electrical insulating material, typically resin. The box 10 comprises at least three electrical terminals, a gate terminal 11, a source terminal 12 and a drain terminal 13, as illustrated in FIG. 2a. By electrical terminal is meant in particular a pin or a metal pad or any other means for forming an external electrical contact of the integrated circuit 100: this external contact may then be connected to other elements, for example on a printed circuit.
Le boitier 10 comporte également une plaque structurelle 14 conductrice. La plaque structurelle 14 est destinée à supporter les composants électroniques du circuit intégré 100. La plaque structurelle 14 est connectée à l'un des trois terminaux 11,12,13 ; dans le cas illustré sur la figure 2a, la plaque structurelle 14 est connectée au terminal de source 12. Dans la présente description, par « connecté », on entend électriquement connecté : soit directement, c'est-à- dire par contact direct entre les deux éléments connectés, soit indirectement, c'est-à-dire au moyen d'un élément intermédiaire, lui-même en contact avec les éléments électriquement connectés ; ledit élément intermédiaire pourra par exemple être un clip de raccordement électrique ou encore une ou une pluralité de connexion (s) filaire(s) . La plaque structurelle 14 est habituellement encapsulée, de même que les composants électroniques du circuit intégré 100, dans la partie isolante 15 du boitier 10. Le circuit intégré 100 comprend également un substrat d'interconnexion 20 présentant une face avant 21 et une face arrière 22. Le substrat d'interconnexion 20 est composé d'une base 23 formée par un matériau isolant électrique et présentant par exemple une forme de plaque (figure 2b) . A titre d'exemple, le matériau isolant de la base 23 est choisi parmi les céramiques, telles que le nitrure d'aluminium, ou autres matériaux appropriés. The housing 10 also comprises a conductive structural plate 14. The structural plate 14 is intended to support the electronic components of the integrated circuit 100. The structural plate 14 is connected to one of the three terminals 11, 12, 13; in the case illustrated in FIG. 2a, the structural plate 14 is connected to the source terminal 12. In the present description, by "connected" is meant electrically connected: either directly, that is to say by direct contact between the two elements connected, either indirectly, that is to say by means of an intermediate element, itself in contact with the electrically connected elements; said intermediate element may for example be an electrical connection clip or one or a plurality of connection (s) wire (s). The structural plate 14 is usually encapsulated, as are the electronic components of the integrated circuit 100, in the insulating part 15 of the housing 10. The integrated circuit 100 also comprises an interconnection substrate 20 having a front face 21 and a rear face 22. The interconnection substrate 20 is composed of a base 23 formed by an electrical insulating material and having, for example, a plate shape (Figure 2b). By way of example, the insulating material of the base 23 is chosen from ceramics, such as aluminum nitride, or other suitable materials.
Le substrat d'interconnexion 20 comporte des pistes conductrices 24 sur sa face avant 21, qui s'étendent sur la base 23. Rappelons que la figure 2b est une représentation schématique qui ne limite en rien les configurations ou répartitions dans le plan (x,y) que l'on pourra adopter pour les pistes de conduction 24. Ces dernières pourront être formées par un matériau métallique tel que le cuivre ou autres matériaux appropriés.  The interconnection substrate 20 comprises conductive tracks 24 on its front face 21, which extend on the base 23. Recall that FIG. 2b is a diagrammatic representation which in no way limits the configurations or distributions in the plane (x, y) that can be adopted for conduction tracks 24. These may be formed by a metallic material such as copper or other suitable materials.
Selon la présente invention, le substrat d'interconnexion 20 comprend en outre au moins un via conducteur 25 traversant, c'est-à-dire allant de la face avant 21 jusqu'à la face arrière 22 du substrat d'interconnexion 20, à travers la base 23. Le via conducteur 25 pourra par exemple être formé par un matériau tel que le cuivre ou autres matériaux adaptés. Avantageusement, le substrat d'interconnexion 20 comporte également un pavé conducteur 26 sur sa face arrière 22, en contact avec le via conducteur 25. Dans le circuit intégré 100 selon l'invention, le substrat d'interconnexion 20 est disposé sur la plaque structurelle 14 conductrice, en particulier, le pavé conducteur 26 est en contact direct avec ou assemblé au moyen d'un matériau conducteur électrique sur la plaque structurelle 14 : ainsi le via conducteur 25 permet de connecter au moins une piste conductrice déterminée 24a avec la plaque structurelle 14. Cette connexion par au moins un via conducteur 25 permet de réduire significativement la longueur de connexion entre la piste conductrice déterminée 24a (qui est destinée à être en contact avec au moins un plot de contact de la première 30 et/ou de la deuxième 40 puce) et la plaque structurelle 14 électriquement reliée à un terminal du circuit intégré 100. Les inductances et résistances parasites étant proportionnelles à la géométrie de la connexion pour un matériau conducteur donné, la réduction de la longueur de connexion résulte notamment en une diminution de ces éléments parasites. Par ailleurs, elle peut également résulter en une réduction d'émission d'interférences électromagnétiques (EMI). According to the present invention, the interconnection substrate 20 further comprises at least one via via 25, that is to say going from the front face 21 to the rear face 22 of the interconnection substrate 20, to 23. The conductive via 25 may for example be formed by a material such as copper or other suitable materials. Advantageously, the interconnection substrate 20 also comprises a conductive pad 26 on its rear face 22, in contact with the conductive via 25. In the integrated circuit 100 according to the invention, the interconnection substrate 20 is arranged on the structural plate In particular, the conductive pad 26 is in direct contact with or assembled by means of an electrically conductive material on the structural plate 14: thus the conductive via 25 makes it possible to connect at least one determined conductive track 24a with the structural plate. 14. This connection via at least one conductive via 25 makes it possible to significantly reduce the connection length between the determined conductive track 24a (which is intended to be in contact with at least one contact pad of the first 30 and / or the second 40 chip) and the structural plate 14 electrically connected to a terminal of the integrated circuit 100. The inductors and parasitic resistances being proportional to the geometry of the connection for a given conductive material, the reduction of the connection length results in particular in a reduction of these parasitic elements. In addition, it can also result in a reduction of electromagnetic interference (EMI) emissions.
Le circuit intégré 100 comprend au moins une première puce 30 comprenant un transistor à haute tension en mode déplétion, et au moins une deuxième puce 40 comprenant un dispositif en mode enrichissement. A titre d'exemple, le transistor à haute tension en mode déplétion pourra consister en un transistor HEMT élaboré sur GaN. A titre d'exemple, le dispositif en mode enrichissement pourra consister en un transistor MOS à effet de champ (MOSFET) élaboré sur Silicium ; il pourra également consister en un dispositif comprenant un MOSFET couplé avec un composant de commande (driver) . The integrated circuit 100 comprises at least a first chip 30 comprising a high voltage transistor in depletion mode, and at least a second chip 40 comprising a device in enrichment mode. For example, the high-voltage transistor in depletion mode may consist of a HEMT transistor developed on GaN. By way of example, the device in enrichment mode may consist of a field effect MOS transistor (MOSFET) developed on silicon; it may also consist of a device comprising a MOSFET coupled with a control component (driver).
La première puce 30 et la deuxième puce 40 comportent respectivement, des premiers plots de contact de grille 31, de source 32 et de drain 33, et des deuxièmes plots de contact de grille 41, de source 42 et de drain 43. Ces premiers et deuxièmes plots de contacts sont respectivement formés sur la face avant 34 de la première puce 30 et la face avant 44 de la deuxième puce 40 (figure 2c) . Comme bien connu de l'homme du métier, les plots de contact sont composés d'un matériau métallique conducteur électrique, par exemple le cuivre ou autres matériaux adaptés. En particulier, le matériau métallique formant les plots de contacts est apte à être assemblé ou soudé. Les plots de contacts d'une puce selon l'invention pourront se présenter sous différentes formes : soit sous la forme de pavés en relief par rapport à la surface de la face avant de la puce, soit sous la forme de billes (« bumps » selon la terminologie anglo-saxonne) également en relief par rapport à la surface de la face avant de la puce. Les premiers 31,32,33 et deuxièmes plots de contacts 41,42,43 pourront être disposés de différentes manières sur les faces avant 34,44 respectives des première 30 et deuxième 40 puces, selon les différents modes de réalisation et variantes conformes à l'invention. The first chip 30 and the second chip 40 respectively comprise first gate contact pads 31, source 32 and drain 33, and second gate contact pads 41, source 42 and drain 43. These first and second contact pads are respectively formed on the front face 34 of the first chip 30 and the front face 44 of the second chip 40 (Figure 2c). As is well known to those skilled in the art, the contact pads are composed of an electrically conductive metallic material, for example copper or other suitable materials. In particular, the metal material forming the contact pads is able to be assembled or welded. The contact pads of a chip according to the invention may be in various forms: either in the form of raised blocks with respect to the surface of the front face of the chip, or in the form of balls ("bumps" according to the English terminology) also in the form of relief relative to the surface of the front face of the chip. The first 31,32,33 and second contact pads 41,42,43 may be arranged in different ways on the respective front faces 34,44 of the first 30 and second 40 chips, according to the different embodiments and variants according to the invention. 'invention.
La première puce 30 et la deuxième puce 40 sont disposées sur le substrat d'interconnexion 20, en particulier selon l'invention, leurs faces avant 34,44 sont en vis-à-vis avec la face avant 21 du substrat d'interconnexion 20 : les premiers 31,32,33 et deuxièmes plots de contact 41,42,43 sont en contact avec les pistes conductrices 24 du substrat d'interconnexion 20. L'assemblage des premiers 31,32,33 et deuxièmes 41,42,43 plots sur les pistes conductrices 24 pourra être réalisé par un procédé de collage métallique par exemple par thermo-compression ou un procédé de soudage ou brasage entre les matériaux composant les plots de contact et les pistes conductrices. Il est ainsi possible d'obtenir un contact électrique de bonne qualité entre les plots de contact des puces 30, 40 et le substrat d'interconnexion 20, avec un chemin de conduction fortement réduit, par exemple par rapport à des connexions filaires.  The first chip 30 and the second chip 40 are disposed on the interconnection substrate 20, in particular according to the invention, their front faces 34,44 are vis-à-vis with the front face 21 of the interconnection substrate 20 the first 31,32,33 and second contact pads 41,42,43 are in contact with the conductive tracks 24 of the interconnection substrate 20. The assembly of the first 31,32,33 and second 41,42,43 pads on the conductive tracks 24 may be achieved by a metal bonding method for example by thermo-compression or a welding process or soldering between the materials forming the contact pads and the conductive tracks. It is thus possible to obtain a good quality electrical contact between the contact pads of the chips 30, 40 and the interconnection substrate 20, with a greatly reduced conduction path, for example with respect to wire connections.
Au moins une piste conductrice 24b est configurée de manière à connecter le premier plot de contact de source 32 avec le deuxième plot de contact de drain 43 : une telle configuration permet la mise en série du transistor à haute tension en mode déplétion et du dispositif en mode enrichissement, selon un arrangement dit cascade.  At least one conductive track 24b is configured to connect the first source contact pad 32 with the second drain contact pad 43: such a configuration enables the high-voltage transistor to be put in series in depletion mode and the device enrichment mode, according to an arrangement said cascade.
Cette connexion par une piste de conduction 24b permet également de réduire la longueur de connexion entre la source 32 de la première puce 30 et le drain 43 de la deuxième puce 40, ce qui limite les résistance et inductance parasites au niveau de ce nœud de connexion. La figure 3 illustre une vue en coupe d'un circuit intégré 100 conforme à l'invention. Les premiers plots de contact 31,32,33 de la première puce 30 et les deuxièmes plots de contact 41, 42, 43 de la deuxième puce 40 sont en contact avec les pistes conductrices 24 (incluant notamment les pistes référencées 24a, 24b) du substrat d'interconnexion 20. Le via conducteur 25 relie électriquement la piste conductrice 24a et le pavé conducteur 26 en face arrière du substrat d'interconnexion 20. Le pavé conducteur 26 est assemblé par collage métallique, soudure ou brasage sur la plaque structurelle 14, établissant également avec celle-ci un contact électrique. Pour plus de lisibilité, la figure 3 ne montre pas la partie isolante 15 du boitier 10, ni les au moins trois terminaux électriques 11,12,13. Compte tenu de la vue en coupe, la piste conductrice 24b reliant le premier plot de contact de source 32 et le deuxième plot de contact de drain 43 n'est pas visible entièrement : elle se prolonge dans le plan (x,y) perpendiculaire au plan de coupe de la figure 3, pour former la connexion électrique entre les deux plots de contacts 32,43. This connection by a conduction track 24b also reduces the connection length between the source 32 of the first chip 30 and the drain 43 of the second chip 40, which limits the parasitic resistance and inductance at this connection node. Figure 3 illustrates a sectional view of an integrated circuit 100 according to the invention. The first contact pads 31, 32, 33 of the first chip 30 and the second contact pads 41, 42, 43 of the second chip 40 are in contact with the conductive tracks 24 (including in particular the tracks referenced 24a, 24b) of the interconnection substrate 20. The conductive via 25 electrically connects the conductive track 24a and the conductive pad 26 on the rear face of the interconnection substrate 20. The conductive pad 26 is assembled by metal bonding, soldering or brazing on the structural plate 14, also establishing with it an electrical contact. For more clarity, Figure 3 does not show the insulating portion 15 of the housing 10, nor the at least three electrical terminals 11,12,13. Given the sectional view, the conductive track 24b connecting the first source contact pad 32 and the second drain contact pad 43 is not entirely visible: it extends in the plane (x, y) perpendicular to the sectional plane of Figure 3, to form the electrical connection between the two contact pads 32,43.
Selon un premier mode de réalisation du circuit intégré 100 selon l'invention (figure 4a), la piste conductrice déterminée 24a est celle en contact avec le deuxième plot de contact de source 42, le terminal du boitier connecté à la plaque structurelle 14 forme alors le terminal de source 12 du circuit intégré 100. Dans ce cas de figure, une piste conductrice 24c en contact avec le premier plot de contact de drain 33 et une autre piste conductrice 24d en contact avec le deuxième plot de contact de grille 41 sont respectivement connectées au terminal de drain 13 (non représenté sur la figure 4a) et au terminal de grille 11 du boitier 10 du circuit intégré 100. Notons que le terminal de grille 11 est représenté sur la figure 4a dans le même plan de coupe que le terminal de source 12 pour plus de lisibilité ; en réalité, il est situé dans un plan (y, z) voisin, conformément au schéma de la figure 2a. According to a first embodiment of the integrated circuit 100 according to the invention (FIG. 4a), the determined conductive track 24a is the one in contact with the second source contact pad 42, the terminal of the box connected to the structural plate 14 then forms the source terminal 12 of the integrated circuit 100. In this case, a conductive track 24c in contact with the first drain contact pad 33 and another conductive track 24d in contact with the second gate contact pad 41 are respectively connected to the drain terminal 13 (not shown in FIG. 4a) and to the gate terminal 11 of the box 10 of the integrated circuit 100. Note that the gate terminal 11 is represented in FIG. 4a in the same section plane as the source terminal 12 for more readability; in fact, it is situated in a neighboring plane (y, z), in accordance with the diagram of FIG. 2a.
Avantageusement, les connexions entre les pistes conductrices 24 et les terminaux de drain 13 et de grille 11 sont réalisées au moyen de clips de raccordement électrique 16. Les clips de raccordement électrique 16 sont habituellement formés par des bandes métalliques, par exemple en cuivre, en aluminium ou autre matériau approprié, soudées sur l'un et l'autre des éléments à connecter. Ils présentent l'avantage d'une faible inductance et d'une faible résistance d'accès, par rapport à des connexions filaires.  Advantageously, the connections between the conductive tracks 24 and the drain terminals 13 and gate 11 are formed by means of electrical connection clips 16. The electrical connection clips 16 are usually formed by metal strips, for example copper, aluminum or other suitable material, welded to one and the other of the elements to be connected. They have the advantage of a low inductance and a low resistance of access, compared to wired connections.
Selon une première variante s' appliquant au cas d'un arrangement cascade (figure 4b) , une piste conductrice 24e en contact avec le premier plot de contact de grille 31 est connectée à un terminal additionnel 111 du boitier 10. Le boitier 10 comporte dans ce cas quatre terminaux électriques, les trois précédemment cités et un terminal additionnel 111 de grille, pour commander indépendamment la grille du transistor à haute tension en mode déplétion de la première puce 30 (connectée au terminal additionnel 111), et la grille du dispositif en mode enrichissement de la deuxième puce 40 (connectée au terminal de grille 11) . Notons que le terminal additionnel de grille 111 est représenté sur la figure 4b dans le même plan de coupe que le terminal de source 12 pour plus de lisibilité ; en réalité il est situé dans un plan vertical (y, z) voisin . Selon une deuxième variante s' appliquant au cas d'un arrangement cascode (figure 4c) , le boitier 10 ne comporte que trois terminaux 11,12,13 et au moins une piste conductrice 24e est configurée de manière à connecter le premier plot de contact de grille 31 avec le deuxième plot de contact de source 42 : dans l'exemple de la figure 4c, cela signifie que la piste conductrice 24e est connectée à la piste 24a, dans le plan (x,y) en face avant 21 du substrat d'interconnexion 20. Avantageusement, la piste conductrice 24e en contact avec le premier plot de contact de grille 31 est connectée à la face arrière 35 de la première puce 30, au moyen d'un clip de raccordement électrique 17, pour mettre ladite face arrière 35 à la masse. Ce clip 17 présente l'avantage additionnel de favoriser une dissipation thermique au niveau de la face arrière 35 de la première puce 30. According to a first variant applying to the case of a cascade arrangement (FIG. 4b), a conductive track 24e in contact with the first gate contact pad 31 is connected to an additional terminal 111 of the box 10. The box 10 comprises in this case four electrical terminals, the three previously mentioned and an additional gate terminal 111, for independently controlling the gate of the high voltage transistor in depletion mode of the first chip 30 (connected to the additional terminal 111), and the gate of the device in enrichment mode of the second chip 40 (connected to the gate terminal 11). Note that the additional grid terminal 111 is shown in Figure 4b in the same section plane as the source terminal 12 for more readability; in reality it is located in a vertical plane (y, z) neighbor. According to a second variant applicable to the case of a cascode arrangement (FIG. 4c), the box 10 comprises only three terminals 11, 12, 13 and at least one conductive track 24 is configured to connect the first contact pad gate 31 with the second source contact pad 42: in the example of FIG. 4c, this means that the conductive track 24e is connected to the track 24a, in the plane (x, y) on the front face 21 of the substrate 20. Advantageously, the conductive track 24e in contact with the first gate contact pad 31 is connected to the rear face 35 of the first chip 30, by means of an electrical connection clip 17, to put said face back to the ground. This clip 17 has the additional advantage of promoting heat dissipation at the rear face 35 of the first chip 30.
Selon une troisième variante s' appliquant au cas d'un arrangement cascode (figure 4d) , le boitier 10 ne comporte que trois terminaux 11,12,13 et la piste conductrice déterminée 24a est configurée de manière à connecter le premier plot de contact de grille 31 avec le deuxième plot de contact de source 42. Un via conducteur 25 ou une pluralité de vias conducteurs 25 permet de connecter la piste conductrice déterminée 24a et le pavé conducteur 26 en face arrière du substrat d'interconnexion 20. Avantageusement, la piste conductrice 24a en contact avec le premier plot de contact de grille 31 est connectée à la face arrière 35 de la première puce 30, au moyen d'un clip de raccordement électrique 17 (non représenté), pour mettre ladite face arrière 35 à la masse. According to a third variant applying to the case of a cascode arrangement (FIG. 4d), the housing 10 has only three terminals 11, 12, 13 and the determined conductive track 24 a is configured to connect the first contact pad of gate 31 with the second source contact pad 42. A conductive via 25 or a plurality of conductive vias 25 connects the determined conducting track 24a and the conductive pad 26 on the rear face of the interconnection substrate 20. Advantageously, the track conductive 24a in contact with the first gate contact pad 31 is connected to the rear face 35 of the first chip 30, by means of an electrical connection clip 17 (not shown), for putting said rear face 35 to ground .
Selon un deuxième mode de réalisation du circuit intégré 100 selon l'invention (figure 5), la piste conductrice déterminée 24a est celle en contact avec le premier plot de contact de drain 33, le terminal du boitier connecté à la plaque structurelle 14 forme alors le terminal de drain 13 du circuit intégré 100. Dans ce cas de figure, la piste conductrice 24d en contact avec le deuxième plot de contact de grille 41 et une piste conductrice 24f en contact avec le deuxième plot de contact de source 42 sont respectivement connectées au terminal de grille 11 et au terminal de source 12 (non représenté) du boitier 10 du circuit intégré 100. According to a second embodiment of the integrated circuit 100 according to the invention (FIG. 5), the determined conductive track 24a is the one in contact with the first stud of drain contact 33, the terminal of the box connected to the structural plate 14 then forms the drain terminal 13 of the integrated circuit 100. In this case, the conductive track 24d in contact with the second gate contact pad 41 and a 24f conductive track in contact with the second source contact pad 42 are respectively connected to the gate terminal 11 and the source terminal 12 (not shown) of the housing 10 of the integrated circuit 100.
Avantageusement, la connexion entre les pistes conductrices 24d,24f et les terminaux de grille 11 et de source 12 sont réalisées au moyen de clips de raccordement électrique 16 présentant l'avantage d'une faible inductance et d'une faible résistance d'accès, par rapport à des connexions filaires .  Advantageously, the connection between the conductive tracks 24d, 24f and the gate terminals 11 and source 12 are made by means of electrical connection clips 16 having the advantage of a low inductance and a low access resistance, compared to wired connections.
Les première et deuxième variantes décrites dans le cadre du premier mode de réalisation s'appliquent également dans le cadre du deuxième mode de réalisation. The first and second variants described in the context of the first embodiment also apply in the context of the second embodiment.
Selon la première variante s' appliquant au cas d'un arrangement cascade, la piste conductrice 24e en contact avec le premier plot de contact de grille 31 est connectée à un terminal additionnel du boitier 10 (non représenté) . Le boitier 10 comporte dans ce cas quatre terminaux électriques, les trois précédemment cités et un terminal additionnel de grille, pour commander indépendamment la grille du transistor à haute tension en mode déplétion de la première puce 30 (connectée au terminal additionnel) , et la grille du dispositif en mode enrichissement de la deuxième puce 40 (connectée au terminal de grille 11) .  According to the first variant applicable to the case of a cascade arrangement, the conductive track 24e in contact with the first gate contact pad 31 is connected to an additional terminal of the housing 10 (not shown). The box 10 comprises in this case four electrical terminals, the three previously mentioned and an additional gate terminal, for independently controlling the gate of the high voltage transistor in depletion mode of the first chip 30 (connected to the additional terminal), and the gate the device in enrichment mode of the second chip 40 (connected to the gate terminal 11).
Selon la seconde variante s' appliquant au cas d'un arrangement cascode, le boitier 10 ne comporte que trois terminaux 11,12,13 et au moins une piste conductrice 24e est configurée de manière à connecter le premier plot de contact de grille 31 avec le deuxième plot de contact de source 42 : dans l'exemple de la figure 5, cela signifie que la piste conductrice 24e est connectée à la piste 24f, dans le plan (x,y) en face avant 21 du substrat d'interconnexion 20. Avantageusement, la piste conductrice 24e en contact avec le premier plot de grille 31 est connectée à la face arrière 35 de la première puce 30 (non représenté), au moyen d'un clip de raccordement électrique 17, pour mettre ladite face arrière 35 à la masse. According to the second variant applying to the case of a cascode arrangement, the housing 10 comprises only three terminals 11, 12, 13 and at least one conductive track 24 is configured to connect the first gate contact pad 31 with the second source contact pad 42: in the example of FIG. 5, this means that the conductive track 24e is connected to the track 24f, in the plane (x, y) on the front face 21 of the interconnection substrate 20. Advantageously, the conductive track 24e in contact with the first gate stud 31 is connected to the rear face 35 of the first chip 30 (not shown), by means of an electrical connection clip 17, to put said rear face 35 to ground.
Dans le circuit intégré 100 selon les différents modes de réalisation de l'invention, le dispositif en mode enrichissement inclus dans la deuxième puce 40 pourra comprendre un transistor en mode enrichissement dont une électrode de grille est connectée au deuxième plot de contact de grille 41 de la deuxième puce 40. Le terminal de grille 11 du boitier 10, connecté au deuxième plot de contact de grille 41 permet alors d'envoyer un signal électrique pour commander la grille du transistor en mode enrichissement (par exemple, un MOSFET sur silicium) . In the integrated circuit 100 according to the different embodiments of the invention, the enrichment mode device included in the second chip 40 may comprise an enhancement mode transistor including a gate electrode is connected to the second gate contact pad 41 of the second chip 40. The gate terminal 11 of the box 10, connected to the second gate contact pad 41 then makes it possible to send an electrical signal for controlling the gate of the transistor in enrichment mode (for example, a silicon MOSFET).
Alternativement, le dispositif en mode enrichissement inclus dans la deuxième puce 40 pourra comprendre un transistor en mode enrichissement et un composant de commande : dans ce cas, une électrode de grille du transistor en mode enrichissement est connectée à une entrée du composant de commande et une sortie du composant de commande est connectée au deuxième plot de contact de grille 41 de la deuxième puce 40. Le terminal de grille 11 du boitier 10, connecté au deuxième plot de contact de grille 41 permet ici d'envoyer un signal électrique au composant de commande ; ce dernier est ensuite apte à traiter ce signal pour commander la grille du transistor en mode enrichissement. Le circuit intégré 100 selon les différents modes de réalisation de l'invention, peut comprendre, outre la première 30 et la deuxième puce 40, une troisième puce comportant un composant passif ou actif. A titre d'exemple, la troisième puce peut comporter un transistor à haute tension en mode déplétion, et des troisièmes plots de contact de grille, de source et de drain. Les troisièmes plots de contacts formés sur une face avant de la troisième puce sont en contact avec des pistes conductrices 24 formées sur la face avant 21 du substrat d'interconnexion 20 : lesdites pistes conductrices 24 sont configurées de manière à connecter la première 30 et la troisième puce en parallèle. Une telle configuration présente notamment l'avantage de minimiser les interconnexions et ainsi, de réduire les inductances et résistances parasites ainsi que les émissions d'EMI. Alternatively, the enrichment mode device included in the second chip 40 may comprise an enhancement mode transistor and a control component: in this case, a gate electrode of the enhancement mode transistor is connected to an input of the control component and a output of the control component is connected to the second gate contact pad 41 of the second chip 40. The gate terminal 11 of the housing 10, connected to the second gate contact pad 41 here makes it possible to send an electrical signal to the component of ordered ; the latter is then able to process this signal to control the gate of the transistor in enrichment mode. The integrated circuit 100 according to the various embodiments of the invention may comprise, in addition to the first 30 and the second chip 40, a third chip comprising a passive or active component. By way of example, the third chip may comprise a high voltage transistor in depletion mode, and third gate, source and drain contact pads. The third contact pads formed on a front face of the third chip are in contact with conductive tracks 24 formed on the front face 21 of the interconnection substrate 20: said conductive tracks 24 are configured to connect the first 30 and the third chip in parallel. Such a configuration has the particular advantage of minimizing the interconnections and thus reduce parasitic inductances and resistances as well as emissions of EMI.
Bien entendu, l'invention n'est pas limitée aux modes de réalisation décrits et on peut y apporter des variantes de réalisation sans sortir du cadre de l'invention tel que défini par les revendications. Of course, the invention is not limited to the embodiments described and variants can be made without departing from the scope of the invention as defined by the claims.

Claims

REVENDICATIONS
Circuit intégré (100) comprenant : Integrated circuit (100) comprising:
• un boitier (10) comportant au moins trois terminaux électriques, un terminal de grille (11), un terminal de source (12) et un terminal de drain (13), et comportant une plaque structurelle (14) conductrice connectée à l'un des trois terminaux (11,12,13),  A housing (10) comprising at least three electrical terminals, a gate terminal (11), a source terminal (12) and a drain terminal (13), and comprising a conductive structural plate (14) connected to the one of the three terminals (11,12,13),
• un substrat d'interconnexion (20) présentant une face avant (21) et une face arrière (22) disposée sur la plaque structurelle (14),  An interconnection substrate (20) having a front face (21) and a rear face (22) disposed on the structural plate (14),
• et, disposées sur le substrat d'interconnexion (20), au moins une première puce (30) comprenant un transistor à haute tension en mode déplétion, et au moins une deuxième puce (40) comprenant un dispositif en mode enrichissement, la première (30) et la deuxième (40) puces comportant respectivement des premiers et des deuxièmes plots de contact de grille (31,41), de source (32,42) et de drain (33,43);  And, disposed on the interconnect substrate (20), at least one first chip (30) comprising a depletion mode high voltage transistor, and at least one second chip (40) comprising an enrichment mode device, the first (30) and the second (40) chips respectively having first and second gate contact pads (31,41), source (32,42) and drain (33,43);
Le circuit intégré (100) étant caractérisé en ce que :  The integrated circuit (100) being characterized in that:
• Les premiers (31,32,33) et deuxièmes (41,42,43) plots de contacts, respectivement formés sur une face avant de la première puce (30) et sur une face avant de la deuxième puce (40), sont en contact avec des pistes conductrices • The first (31,32,33) and second (41,42,43) contact pads, respectively formed on a front face of the first chip (30) and on a front face of the second chip (40), are in contact with conductive tracks
(24) formées sur la face avant (21) du substrat d'interconnexion (20) ; au moins une piste conductrice(24) formed on the front face (21) of the interconnect substrate (20); at least one conductive track
(24b) étant configurée de manière à connecter le premier plot de contact de source (32) avec le deuxième plot de contact de drain (43) ; (24b) being configured to connect the first source contact pad (32) with the second drain contact pad (43);
• Le substrat d'interconnexion (20) comprend au moins un via conducteur traversant (25) pour connecter au moins une piste conductrice déterminée (24a) avec la plaque structurelle (14).  • The interconnect substrate (20) comprises at least one through conductive via (25) for connecting at least one determined conductive track (24a) with the structural plate (14).
Circuit intégré (100) selon la revendication précédente, dans lequel la piste conductrice déterminée (24a) est celle en contact avec le deuxième plot de contact de source (42), le terminal du boitier connecté à la plaque structurelle (14) formant le terminal de source (12) du circuit intégré (100). Integrated circuit (100) according to the preceding claim, wherein the determined conductive track (24a) is the one in contact with the second source contact pad (42), the terminal of the box connected to the plate structural element (14) forming the source terminal (12) of the integrated circuit (100).
Circuit intégré (100) selon la revendication précédente, dans lequel la piste conductrice (24) en contact avec le premier plot de contact de drain (33) et la piste conductrice (24) en contact avec le deuxième plot de contact de grille (41) sont respectivement connectées au terminal de drain (13) et au terminal de grille (11) du boitier (10). Integrated circuit (100) according to the preceding claim, wherein the conductive track (24) in contact with the first drain contact pad (33) and the conductive track (24) in contact with the second gate contact pad (41). ) are respectively connected to the drain terminal (13) and the gate terminal (11) of the housing (10).
Circuit intégré (100) selon la revendication précédente, dans lequel les connexions entre les pistes conductrices (24) et les terminaux de drain (13) et de grille (11) sont réalisées au moyen de clips de raccordement électrique (16). Integrated circuit (100) according to the preceding claim, wherein the connections between the conductive tracks (24) and the drain terminals (13) and gate (11) are formed by means of electrical connection clips (16).
Circuit intégré (100) selon la revendication 1, dans lequel la piste conductrice déterminée (24a) est celle en contact avec le premier plot de contact de drain (33) , le terminal du boitier connecté à la plaque structurelleIntegrated circuit (100) according to claim 1, wherein the determined conductive track (24a) is the one in contact with the first drain contact pad (33), the terminal of the box connected to the structural plate
(14) formant le terminal de drain (13) du circuit intégré(14) forming the drain terminal (13) of the integrated circuit
(100) . (100).
Circuit intégré (100) selon la revendication précédente, dans lequel la piste conductrice (24) en contact avec le deuxième plot de contact de grille (41) et la piste conductrice (24) en contact avec le deuxième plot de contact de source (42) sont respectivement connectées au terminal de grille (11) et au terminal de source (12) du boitier (10). Integrated circuit (100) according to the preceding claim, wherein the conductive track (24) in contact with the second gate contact pad (41) and the conductive track (24) in contact with the second source contact pad (42). ) are respectively connected to the gate terminal (11) and the source terminal (12) of the housing (10).
Circuit intégré (100) selon la revendication précédente, dans lequel les connexions entre les pistes conductrices (24) et les terminaux de grille (11) et de source (12) sont réalisées au moyen de clips de raccordement électrique (16). 8. Circuit intégré (100) selon l'une des revendications précédentes, dans lequel au moins une piste conductrice (24) est configurée de manière à connecter le premier plot de contact de grille (31) avec le deuxième plot de contact de source (42), pour connecter la première (30) et la deuxième (40) puce en cascode. Integrated circuit (100) according to the preceding claim, wherein the connections between the conductive tracks (24) and the gate (11) and source (12) terminals are realized by means of electrical connection clips (16). An integrated circuit (100) according to one of the preceding claims, wherein at least one conductive track (24) is configured to connect the first gate contact pad (31) with the second source contact pad ( 42), for connecting the first (30) and second (40) chips in cascode.
9. Circuit intégré (100) selon l'une des revendications 1 à 7, dans lequel la piste conductrice (24) en contact avec le premier plot de contact de grille (31) est connectée à un terminal additionnel (111) du boitier (10) . 9. Integrated circuit (100) according to one of claims 1 to 7, wherein the conductive track (24) in contact with the first gate contact pad (31) is connected to an additional terminal (111) of the housing ( 10).
10. Circuit intégré (100) selon l'une des revendications précédentes, dans lequel le dispositif en mode enrichissement inclus dans la deuxième puce (40) comprend un transistor en mode enrichissement dont une électrode de grille est connectée au plot de contact de grille (41) de la deuxième puce (40) . An integrated circuit (100) according to one of the preceding claims, wherein the enrichment mode device included in the second chip (40) comprises an enhancement mode transistor having a gate electrode connected to the gate contact pad ( 41) of the second chip (40).
11. Circuit intégré (100) selon l'une des revendications 1 à 9, dans lequel le dispositif en mode enrichissement inclus dans la deuxième puce (40) comprend un transistor en mode enrichissement et un composant de commande, une électrode de grille du transistor en mode enrichissement étant connectée à une entrée du composant de commande et une sortie du composant de commande étant connectée au plot de contact de grille (41) de la deuxième puce (40) . An integrated circuit (100) according to one of claims 1 to 9, wherein the enrichment mode device included in the second chip (40) comprises an enhancement mode transistor and a control component, a gate electrode of the transistor in enrichment mode being connected to an input of the control component and an output of the control component being connected to the gate contact pad (41) of the second chip (40).
12. Circuit intégré (100) selon l'une des revendications précédentes, comprenant une troisième puce comportant un composant passif ou actif. 12. Integrated circuit (100) according to one of the preceding claims, comprising a third chip having a passive or active component.
13. Circuit intégré (100) selon la revendication précédente, dans lequel la troisième puce comporte un transistor à haute tension en mode déplétion, et des troisièmes plots de contact de grille, de source et de drain ; les troisièmes plots de contacts formés sur une face avant de la troisième puce, étant en contact avec des pistes conductrices (24) formées sur la face avant (21) du substrat d'interconnexion (20) ; les pistes conductrices (24) étant configurées de manière à connecter la première (30) et la troisième puce en parallèle . 13. Integrated circuit (100) according to the preceding claim, wherein the third chip comprises a high-voltage transistor in depletion mode, and third contact pads gate, source and drain; the third contact pads formed on a front face of the third chip being in contact with conductive tracks (24) formed on the front face (21) of the interconnect substrate (20); the conductive tracks (24) being configured to connect the first (30) and third chips in parallel.
PCT/FR2017/053167 2016-11-21 2017-11-20 Integrated circuit formed by two chips that are connected in series WO2018091852A1 (en)

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FR1661315A FR3059154B1 (en) 2016-11-21 2016-11-21 INTEGRATED CIRCUIT FORMED OF TWO CHIPS CONNECTED IN SERIES
FR1661315 2016-11-21

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CN110504242A (en) * 2019-08-26 2019-11-26 黄山学院 High current cascades enhanced GaN full bridge power module encapsulation construction and packaging method
CN113345871A (en) * 2021-04-25 2021-09-03 华中科技大学 Low parasitic inductance series power module
CN113410200A (en) * 2020-03-16 2021-09-17 苏州捷芯威半导体有限公司 Chip packaging frame and chip packaging structure
CN114121840A (en) * 2020-08-31 2022-03-01 苏州兴锝电子有限公司 Semiconductor silicon controlled module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504242A (en) * 2019-08-26 2019-11-26 黄山学院 High current cascades enhanced GaN full bridge power module encapsulation construction and packaging method
CN113410200A (en) * 2020-03-16 2021-09-17 苏州捷芯威半导体有限公司 Chip packaging frame and chip packaging structure
CN113410200B (en) * 2020-03-16 2023-12-05 苏州捷芯威半导体有限公司 Chip packaging frame and chip packaging structure
CN114121840A (en) * 2020-08-31 2022-03-01 苏州兴锝电子有限公司 Semiconductor silicon controlled module
CN113345871A (en) * 2021-04-25 2021-09-03 华中科技大学 Low parasitic inductance series power module
CN113345871B (en) * 2021-04-25 2022-09-13 华中科技大学 Low parasitic inductance series power module

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