JP2015153986A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit warpage of a stress relaxation layer to reduce damages of a solder layer caused by the warpage in a semiconductor device in which a semiconductor chip is bonded to a surface of a lead frame via the stress relaxation layer by a Pb-free solder.SOLUTION: A semiconductor device comprises a semiconductor chip 10 mounted and bonded to a lead frame 20 via a bonding member 30, in which the bonding member 30 is formed by sequentially laminating from the lead frame 20 side, a second solder layer 33, a stress relaxation layer 31 and a first solder layer 32. Each of the first and second solder layers 32, 33 and the stress relaxation layer 31 has the planar size larger than that of the semiconductor chip 10 and has a peripheral part protrudes to the outside of an end 10a of the semiconductor chip 10. A part of the stress relaxation layer 31, which is located directly under the end 10a of the semiconductor chip 10 has a groove 40 for inhibiting warpage of the stress relaxation layer 31 at a part located closer to the peripheral part side than the part directly under the end 10a.

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is solder-bonded to a base material by Pb-free solder via a stress relaxation layer.

  2. Description of the Related Art Conventionally, a semiconductor device is known in which a semiconductor chip is solder-bonded on a base material via a stress relaxation layer. As this type of semiconductor device, for example, a semiconductor device described in Patent Document 1 has been proposed.

  The semiconductor device includes a semiconductor chip, a base material on which the semiconductor chip is mounted, a bonding member that is provided between the semiconductor chip and the base material and has a solder and joins the semiconductor chip and the base material. , And is configured.

  Here, the stress relaxation layer is configured as a part of the joining member, and is configured of a metal such as Al (aluminum). Such a bonding member is provided between the semiconductor chip and the stress relaxation layer, provided between the first solder layer for bonding the semiconductor chip and the stress relaxation layer, and the stress relaxation layer and the base material, The stress relaxation layer and the second solder layer that joins the base material are provided.

  This stress relaxation layer is a portion that relaxes thermal stress generated in the bonding member due to the difference in linear expansion coefficient between the semiconductor chip and the base material. Here, in the said patent document 1, the 1st solder layer and the 2nd solder layer are comprised with the solder containing Pb (lead).

JP-A-4-192341

  In the semiconductor device described in Patent Document 1, the stress relaxation layer is provided as described above, and when the temperature becomes high, the stress relaxation layer is plastically deformed to exhibit the stress relaxation effect. It is configured. In this semiconductor device, the first solder layer and the second solder layer are made of solder containing Pb.

  However, in recent years, there is a trend to reduce the use of harmful chemical substances such as Pb, as seen in the RoHS (Restriction of Hazardous Substances) directive. For this reason, in the semiconductor device as described above, it has been studied to use solder not containing Pb (hereinafter referred to as Pb-free solder) instead of solder containing Pb.

  Therefore, it is necessary that at least one of the first and second solder layers is made of Pb-free solder. Specifically, this Pb-free solder contains Zn (zinc), Au (gold), Bi (bismuth) or the like, which is a high melting point material, as a main component. However, such a high-melting point Pb-free solder is harder than plastics containing Pb and is hard to be plastically deformed.

  In the above semiconductor device, even when such Pb-free solder is used for the first and second solder layers, when the temperature becomes high, the stress relaxation layer plastically deforms and exhibits a stress relaxation effect. It is considered that the occurrence of cracks in the first and second solder layers can be prevented.

  Here, when such a semiconductor device is applied to an electronic device mounted on an automobile, for example, in a high-temperature environment (for example, 250 ° C. or higher) due to circumstances such as high-voltage current control and high-speed operation. Will be used. When used in such a high temperature environment, the heat generated in the semiconductor chip is radiated to the base material via the bonding member. Therefore, it is desired to improve the heat dissipation of the semiconductor chip via this joining member.

  In response to this problem of improving heat dissipation, the present inventor has a configuration in which the planar size of the bonding member 30 on the base material 20 is larger than that of the semiconductor chip 10 in the semiconductor device as shown in FIG. Was prototyped and examined. That is, the first solder layer 32, the second solder layer 33, and the stress relaxation layer 31 in the joining member 30 are all larger in plane size than the semiconductor chip 10, and the peripheral portion is an end portion of the semiconductor chip 10. It was decided to adopt a configuration that protruded to the outside of 10a.

  Conventionally, since the planar size of the bonding member 30, particularly the planar size of the stress relaxation layer 31, is equal to or less than that of the semiconductor chip 10, there is a limit to improving heat dissipation. However, according to the above configuration adopted by the present inventor, in the joining member 30, the heat of the semiconductor chip 10 is diffused to the outside of the end portion 10a of the semiconductor chip 10 in the plane direction, so that heat is dissipated. Improvement in heat dissipation can be expected.

  However, in the case of such a configuration, the peripheral portion of the stress relaxation layer 31 protruding outside the end portion 10 a of the semiconductor chip 10 is a portion that is not pressed by the semiconductor chip 10. That is, the peripheral portion of the stress relaxation layer 31 tends to be less constrained than the portion of the stress relaxation layer 31 located immediately below the semiconductor chip 10.

  Therefore, at a high temperature or the like, as shown in FIG. 7, the portion located immediately below the semiconductor chip 10 in the stress relaxation layer 31 is less likely to warp and maintains flatness. In the part located in the peripheral part side rather than the part located directly under the part 10a, the stress relaxation layer 31 is likely to warp.

  This warpage is caused by the difference in the linear expansion coefficient of each part. More specifically, the stress relaxation layer 31 has the largest linear expansion coefficient compared to the semiconductor chip 10, the solder layers 32 and 33, and the lead frame 20. Therefore, for example, as shown in FIG. 7, the peripheral portion of the stress relaxation layer 31 that protrudes outside the end portion 10 a of the semiconductor chip 10 is warped so as to bend upward.

  As shown in FIG. 7, the first and second solder layers 32 and 33 made of relatively hard Pb-free solder are generated by the warping of the stress relaxation layer 31 outside the semiconductor chip 10. Damage such as a crack K1 is likely to occur.

  That is, if the first and second solder layers 32 and 33 are conventional solders containing Pb that is relatively soft and easily plastically deformed, damage due to warping of the stress relaxation layer 31 hardly occurs, but hard Pb This damage is a problem because it is a free solder.

  The present invention has been made in view of the above problems, and a semiconductor device in which the semiconductor chip is solder-bonded to a base material by Pb-free solder through a stress relaxation layer having a larger planar size than the semiconductor chip. The purpose of the invention is to suppress warping of the stress relaxation layer and reduce damage to the solder layer due to the warping.

In order to achieve the above object, the invention according to claim 1 is provided with a semiconductor chip (10), a base material (20) on which the semiconductor chip is mounted, a semiconductor chip and the base material, A joining member (30) for joining the base material,
The joining member is a part that relieves thermal stress generated in the joining member due to a difference in linear expansion coefficient between the semiconductor chip and the base material, and is provided between the semiconductor chip and the base material, and the metal is a main component. A stress relaxation layer (31) configured to be configured, a first solder layer (32) provided between the semiconductor chip and the stress relaxation layer, and joining the semiconductor chip and the stress relaxation layer; And a second solder layer (33) which is provided between the base material and joins the stress relaxation layer and the base material, and further includes the following configuration. Yes.

  That is, in the semiconductor device of claim 1, at least one of the first solder layer and the second solder layer is made of Pb-free solder not containing Pb, and the first solder layer in the joining member, Each of the second solder layer and the stress relaxation layer has a larger planar size than the semiconductor chip, and the peripheral portion protrudes outside the end portion (10a) of the semiconductor chip. The part located immediately below the end part of the substrate is a warp suppressing part (40 to 44) having a shape that suppresses the warp of the stress relaxation layer in a part located on the peripheral side of the part. To do.

  According to this, since the part located directly under the end of the semiconductor chip in the stress relaxation layer is configured as a warp suppressing part, the part of the stress relaxation layer is located directly under the end of the semiconductor chip. The portion located on the peripheral side, that is, the peripheral portion of the stress relaxation layer that protrudes outward from the end portion of the semiconductor chip is less likely to warp and deform. Thus, according to the present invention, warping of the stress relaxation layer is suppressed, and damage to the solder layer due to the warping can be reduced.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(A) is a schematic sectional drawing of the semiconductor device concerning 1st Embodiment of this invention, (b) is a schematic plan view which shows the planar shape of the groove | channel in (a). It is a schematic sectional drawing of the semiconductor device concerning 2nd Embodiment of this invention. It is a schematic sectional drawing of the semiconductor device concerning 3rd Embodiment of this invention. (A) is a schematic sectional drawing of the semiconductor device concerning 4th Embodiment of this invention, (b) is a schematic plan view which shows the planar pattern of the through-hole in (a). It is a schematic sectional drawing of the semiconductor device concerning 5th Embodiment of this invention. It is a schematic sectional drawing of the semiconductor device concerning 6th Embodiment of this invention. It is a schematic sectional drawing of the semiconductor device as a prototype of this inventor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
The semiconductor device S1 according to the first embodiment of the present invention will be described with reference to FIG. This semiconductor device S1 is mounted on a vehicle such as an automobile, for example, and is applied as a device for driving various electronic devices for the vehicle.

  The semiconductor device S1 of the present embodiment is roughly provided with a semiconductor chip 10 and a lead frame 20 as a base material on which the semiconductor chip 10 is mounted, as shown in FIG. Further, the semiconductor device S1 is provided between the semiconductor chip 10 and the lead frame 20, and is configured to have Pb-free solder, and includes a joining member 30 that joins the semiconductor chip 10 and the lead frame 20.

  The bonding member 30 includes a stress relaxation layer 31 that relaxes thermal stress, a first solder layer 32 that bonds the semiconductor chip 10 and the stress relaxation layer 31, and a second that bonds the stress relaxation layer 31 and the lead frame 20. Solder layer 33. Here, the thermal stress refers to a thermal stress generated due to a difference in linear expansion coefficient between the semiconductor chip 10 and the lead frame 20 at a high temperature. Hereinafter, the term “thermal stress” also refers to this thermal stress.

  The semiconductor chip 10 is a chip in which a semiconductor element is mounted on a thin plate-like semiconductor substrate. The semiconductor substrate constituting the semiconductor chip 10 is made of a semiconductor such as Si (silicon) or SiC (silicon carbide), for example. The semiconductor element mounted on the semiconductor substrate is composed of, for example, an integrated circuit, a power element such as a MOS transistor, a passive element such as a capacitor, and the like.

  The lead frame 20 is a member made of a metal having excellent conductivity such as Cu or 42 alloy, and is formed by etching or pressing. As shown in FIG. 1, the lead frame 20 is formed in a plate shape having one surface 21, and the semiconductor chip 10 is mounted on the one surface 21 of the lead frame 20.

  As described above, in the bonding member 30, the stress relaxation layer 31, the first solder layer 32, and the second solder layer 33 are sequentially stacked from the one surface 21 side of the lead frame 20 toward the semiconductor chip 10 side. It has been configured.

  The stress relaxation layer 31 is a plate-like member that relaxes thermal stress generated in the bonding member 30 due to a difference in linear expansion coefficient between the semiconductor chip 10 and the lead frame 20. The stress relaxation layer 31 is configured to have one surface 311 facing the first solder layer 32 and another surface 312 facing the second solder layer 33 on the side opposite to the one surface 311. That is, the stress relaxation layer 31 is a plate-like member having the one surface 311 and the other surface 312 as front and back plate surfaces.

  The stress relaxation layer 31 employs a plate-like member composed of Al (aluminum) as a main material. As Al used for the stress relaxation layer 31, here, as an example, commercially available pure Al is adopted, but in addition to 100% Al, for example, pure Al at the level of a commercial product is used. Can be adopted. Further, for example, it is sufficient that Al has a concentration of about 99% or higher.

  Further, although not shown in the drawings, at least one surface 311 and the other surface 312 of the Al surface of the stress relaxation layer 31 are made of Ni or the like in order to ensure solderability with the first and second solder layers 32 and 33. Has been plated. In addition, it is preferable that the surface of the semiconductor chip 10 on the side of the bonding member 30 is subjected to a plating process such as Ti—Ni—Au for ensuring solderability to the first solder layer 32.

  In the semiconductor device S <b> 1 according to the present embodiment, the first solder layer 32 is provided between the one surface 311 of the stress relaxation layer 31 and the semiconductor chip 10. A second solder layer 33 is provided between the other surface 312 of the stress relaxation layer 31 and one surface 21 of the lead frame 20.

  As a material constituting the first and second solder layers 32 and 33, normal Pb-free solder can be employed. For example, examples of the Pb-free solder include Sn-Ag solder and Sn-Ag-Cu solder. Note that the first solder layer 32 and the second solder layer 33 may be the same Pb-free solder or different Pb-free solders.

  In the semiconductor device S1 of the present embodiment, the planar size of the bonding member 30 is larger than that of the semiconductor chip 10 as shown in FIG. That is, the first solder layer 32, the second solder layer 33, and the stress relaxation layer 31 in the bonding member 30 are all larger in planar size than the planar size of the semiconductor chip 10. Thereby, each peripheral portion of the first solder layer 32, the second solder layer 33, and the stress relaxation layer 31 is configured to protrude outside the end portion 10 a of the semiconductor chip 10.

  Here, as shown in FIG. 1, the semiconductor chip 10 has a planar rectangular plate shape with four sides as end portions 10 a, and the first solder layer 32 and the second solder layer 33 in the joining member 30. The stress relaxation layer 31 has a planar rectangle that is slightly larger than the semiconductor chip 10. The first solder layer 32, the second solder layer 33, and the stress relaxation layer 31 have substantially the same planar size and substantially the same planar shape.

  Thus, by making the planar size of the joining member 30 larger than the planar size of the semiconductor chip 10, the heat of the semiconductor chip 10 is outside the end portion 10 a of the semiconductor chip 10 in the planar direction via the joining member 30. It will be diffused and will be dissipated. From this, improvement in heat dissipation can be expected.

  In the semiconductor device S1 of the present embodiment, the stress relaxation layer 31 is provided with a groove 40 as a warp suppressing portion at a portion located immediately below the end portion 10a of the semiconductor chip 10. The groove 40 is for suppressing the warp of the stress relaxation layer 31 in a portion located on the peripheral side rather than a portion located directly below the end portion 10 a of the semiconductor chip 10.

  The groove 40 is partially provided in a portion of the stress relaxation layer 31 that is located immediately below the end portion 10a of the semiconductor chip 10, and relaxes the warping stress generated in the portion. Here, in the portion of the groove 40 serving as a warp suppressing portion, the stress relaxation layer 31 has a shape that is thinner than a portion other than the groove 40.

  That is, the portion of the groove 40 is the thinnest portion in the stress relaxation layer 31, thereby constituting a warp suppressing portion. Further, in the stress relaxation layer 31 other than the groove 40, specifically, in the portion closer to the center of the stress relaxation layer 31 than the groove 40, heat dissipation is ensured by ensuring the layer thickness.

  Here, the groove 40 is not provided on the one surface 311 side of the stress relaxation layer 31 but is provided only on the other surface 312 side. The planar shape of the groove 40 is a rectangular ring shape corresponding to the entire circumference of the end portion 10 a of the semiconductor chip 10. That is, as shown in FIG. 1, the entire circumference of the end portion 10 a of the semiconductor chip 10 is positioned within the width of the groove 40.

  Here, the groove 40 has a trapezoidal groove shape with a narrow bottom side. Such a groove 40 is formed by pressing, etching, cutting, or the like. Here, also on the inner surface of the groove 40, the above-described plating treatment with Ni or the like for ensuring solderability with the first and second solder layers 32 and 33 is performed.

  By the way, in the semiconductor device S <b> 1 of the present embodiment, the peripheral portion of the stress relaxation layer 31 that protrudes outside the end portion 10 a of the semiconductor chip 10 in the stress relaxation layer 31 is not restricted by the semiconductor chip 10.

  Therefore, at the time of high temperature or the like, the warp as shown in FIG. 7 is likely to occur due to the difference in linear expansion coefficient of each part in the semiconductor device S1. As an example of the linear expansion coefficient of each part, semiconductor chip 10: SiC of 3 ppm / ° C., each solder layer 32, 33: Pb-free solder of 19 ppm / ° C., lead frame 20: Cu of 16.8 ppm / ° C., stress relaxation Layer 31: Al at 23 ppm / ° C.

  On the other hand, in this embodiment, the site | part located just under the edge part 10a of the semiconductor chip 10 among the stress relaxation layers 31 is comprised as a shape which has the groove | channel 40 as a curvature suppression part. That is, the warp suppressing portion of the present embodiment is provided with the groove 40, so that the thickness of the groove 40 is thinner than the portion of the stress relaxation layer 31 other than the groove 40. It is the part made into the shape.

  Therefore, according to the present embodiment, since the warping stress is relieved at the portion of the groove 40 having the thin shape, warping at a portion of the stress relaxation layer 31 located on the peripheral side of the groove 40 is suppressed. Is done.

  That is, according to the present embodiment, the peripheral portion of the stress relaxation layer 31 that protrudes outward from the end portion 10a of the semiconductor chip 10 is less likely to warp and deform. Thereby, according to this embodiment, the curvature of the stress relaxation layer 31 is suppressed and the damage of the 1st and 2nd solder layers 32 and 33 by the said curvature can be reduced.

  In particular, in the present embodiment, as described above, the first and second solder layers 32 and 33 are made of Pb-free solder that is harder than solder containing Pb. However, even such a hard Pb-free solder can prevent damage due to warping of the stress relaxation layer 31 as much as possible.

  The manufacturing method of the semiconductor device S1 of this embodiment is as follows. First, the second solder layer 33, the stress relaxation layer 31 having the groove 40, the first solder layer 32, and the semiconductor chip 10 are sequentially stacked on the one surface 21 of the lead frame 20. Here, the first and second solder layers 32 and 33 are installed in a state of solder paste, solder foil or the like.

  Then, the first and second solder layers 32 and 33 are melted and solidified while applying pressure to the laminated body as necessary. As a result, the lead frame 20, the stress relaxation layer 31, and the semiconductor chip 10 are solder-bonded via the first and second solder layers 32 and 33. Thus, the semiconductor device S1 of this embodiment is completed.

  In FIG. 1, the groove 40 has a ring shape located on the entire circumference immediately below the end portion 10 a of the semiconductor chip 10. However, as the groove 40 in this embodiment, the end portion 10 a of the semiconductor chip 10 is used. It may be a discontinuous shape partially located immediately below.

  Moreover, although the groove | channel 40 shown by the said FIG. 1 was made into the trapezoid groove | channel shape where the bottom side became narrow, as a groove | channel shape of the groove | channel 40 of this embodiment, it is not limited to this, For example, A rectangular groove shape, a V-shaped groove shape, a U-shaped groove shape, or the like may be used.

(Second Embodiment)
The semiconductor device S2 according to the second embodiment of the present invention will be described with reference to FIG. 2, focusing on differences from the first embodiment. In the first embodiment, the groove 40 as the warp suppressing portion is not provided on the one surface 311 side of the stress relaxation layer 31 but provided only on the other surface 312 side.

  On the other hand, in the semiconductor device S2 of the present embodiment, as shown in FIG. 2, the groove 40 as the warp suppressing portion is symmetrical on both the one surface 311 side and the other surface 312 side of the stress relaxation layer 31. Is provided.

  Here, the planar shape of the grooves 40 on both the one surface 311 side and the other surface 312 side is a rectangular ring shape corresponding to the entire circumference of the end portion 10a of the semiconductor chip 10 as in the groove 40 shown in FIG. There is no. Also in the present embodiment, the entire circumference of the end portion 10 a of the semiconductor chip 10 is located within the range of the widths of both the grooves 40.

  In addition, here, both the grooves 40 have a trapezoidal groove shape with a narrow bottom side. Such a groove 40 is formed by pressing, etching, cutting, or the like. Here, also on the inner surfaces of both the grooves 40, the above-described plating treatment with Ni or the like for ensuring solderability with the first and second solder layers 32 and 33 is performed.

  As described above, also in the present embodiment, a portion of the stress relaxation layer 31 located immediately below the end portion 10a of the semiconductor chip 10 has a shape having the groove 40, thereby forming a warpage suppressing portion. .

  That is, the warp suppressing portion in the present embodiment is provided with the grooves 40 on both the one surface 311 side and the other surface 312 side of the stress relaxation layer 31, so that the stress relaxation layer 31 other than both the grooves 40. Compared with the above-mentioned part, it is the part made into the thin shape by which the layer thickness became thin by the part of the said both groove | channel 40.

  Therefore, also in the present embodiment, since the warping stress is relieved at the portions of the both grooves 40 having the thin shape, the stress relaxation layer 31 is positioned closer to the peripheral portion than both the grooves 40. Warpage at the site is suppressed. Therefore, also in this embodiment, the warp of the stress relaxation layer 31 is suppressed, and damage to the first and second solder layers 32 and 33 due to the warp can be reduced.

  In the present embodiment, the grooves 40 on both the one surface 311 side and the other surface 312 side of the stress relaxation layer 31 only need to be positioned directly below the end portion 10a of the semiconductor chip 10, and the positions of both the grooves 40 are the same. The groove width may be somewhat different.

  Further, both the grooves 40 may have different groove shapes. For example, the groove shape of one groove 40 may be V-shaped, and the groove shape of the other groove 40 may be U-shaped.

  Also in the present embodiment, both the grooves 40 may have a discontinuous shape that is partially located immediately below the end 10 a of the semiconductor chip 10. Furthermore, one of the both grooves 40 may have the discontinuous shape, and the other may have a continuous ring shape located on the entire circumference immediately below the end portion 10a of the semiconductor chip 10.

  Further, with respect to the first embodiment and the second embodiment, the groove 40 as the warp suppressing portion may be provided only on the one surface 311 side of the stress relaxation layer 31. That is, the groove 40 as the warp suppressing portion is a front and back both surfaces of the stress relaxation layer 31 and at least one of the one surface 311 and the other surface 312 in a portion of the stress relaxation layer 31 located immediately below the end portion 10 a of the semiconductor chip 10. What is provided in one side should just be.

(Third embodiment)
The semiconductor device S3 according to the third embodiment of the present invention will be described with reference to FIG. 3, focusing on differences from the first embodiment. In the first embodiment, the warpage suppressing portion has the groove 40.

  On the other hand, in the semiconductor device S3 of the present embodiment, the warp suppressing portion is provided inside the stress relaxation layer 31 in a portion of the stress relaxation layer 31 that is located immediately below the end portion 10a of the semiconductor chip 10. An inner hole 41 is provided. The inner hole 41 is formed by making the stress relaxation layer 31 porous by etching or the like, for example.

  The inner hole 41 is partially provided in a portion of the stress relaxation layer 31 that is located immediately below the end 10 a of the semiconductor chip 10. And in the part of this inner hole 41, the stress relaxation layer 31 is made into the shape whose layer thickness is relatively thinner than the site | parts other than the inner hole 41, and the curvature suppression part is comprised. Specifically, a large number of inner holes 41 are formed so as to be distributed in a region corresponding to the entire circumference of the end portion 10a of the semiconductor chip 10 in the same manner as the groove 40 shown in FIG.

  That is, in the stress relaxation layer 31, the portion of the inner hole 41, which is a warp suppressing portion, is a portion having the thinnest effective layer thickness in the stress relaxation layer 31. Therefore, the warping stress is relieved in the warp suppressing portion which is a thin portion formed by the inner hole 41 in the stress relieving layer 31.

  Also in the present embodiment, by securing the layer thickness at a portion other than the inner hole 41 in the stress relaxation layer 31, specifically, at a portion closer to the center of the stress relaxation layer 31 than the inner hole 41, Heat dissipation is ensured.

  As described above, according to the present embodiment, since the warping stress is relieved at the portion of the inner hole 41 having a thin shape, in the portion located on the peripheral side of the stress relieving layer 31 from the inner hole 41. Warpage is suppressed. Therefore, also in this embodiment, damage to the first and second solder layers 32 and 33 due to warping of the stress relaxation layer 31 can be reduced.

  The inner holes 41 do not have to be distributed in a region corresponding to the entire circumference of the end portion 10a of the semiconductor chip 10, and in the region corresponding to the entire circumference of the end portion 10a of the semiconductor chip 10. It may be partially distributed.

(Fourth embodiment)
The semiconductor device S4 according to the fourth embodiment of the present invention will be described with reference to FIG. 4, focusing on the differences from the first embodiment. In the first embodiment, the warpage suppressing portion has the groove 40.

  On the other hand, in the semiconductor device S4 of the present embodiment, the warp suppressing portion has the stress relaxing layer 31 in the layer thickness direction at a portion of the stress relaxing layer 31 located immediately below the end portion 10a of the semiconductor chip 10. It has a through hole 42 penetrating therethrough.

  In this case, it is necessary to ensure the mechanical strength without separating the stress relaxation layer 31 from the through hole 42 as a boundary. Therefore, as shown in FIG. 4, the plurality of through holes 42 are intermittently arranged in a portion of the stress relaxation layer 31 located immediately below the end portion 10 a of the semiconductor chip 10.

  Such a through hole 42 is formed by pressing, etching, cutting, or the like. In FIG. 4, the through hole 42 is a hole having a circular opening shape, but may be a square hole or the like. The plurality of through holes 42 may have the same shape or different shapes. Also, the opening size of the through holes 42 may be the same or different in the plurality of through holes 42.

  According to the present embodiment, in the stress relaxation layer 31, by providing the through hole 42 as the warp suppressing portion, the through hole 42 is provided in the part of the through hole 42 compared to the part other than the through hole 42. Therefore, the mechanical strength is reduced. Therefore, the warp stress can be relaxed at the portion of the through hole 42.

  Also in the present embodiment, it is effective because the through hole 42 does not exist in a portion other than the through hole 42 in the stress relaxation layer 31, specifically, a portion closer to the center of the stress relaxation layer 31 than the through hole 42. Layer thickness is ensured and heat dissipation is ensured.

  As described above, according to the present embodiment, since the warping stress is relieved at the portion of the through hole 42 as the warp suppressing portion, the stress relieving layer 31 in the portion located on the peripheral side of the through hole 42. Warpage is suppressed. Therefore, also in this embodiment, damage to the first and second solder layers 32 and 33 due to warping of the stress relaxation layer 31 can be reduced.

(Fifth embodiment)
The semiconductor device S5 according to the fifth embodiment of the present invention will be described with reference to FIG. 5, focusing on differences from the first embodiment. In the first embodiment, the warpage suppressing portion has the groove 40.

  On the other hand, in the semiconductor device S5 of the present embodiment, the warp suppressing portion is provided inside the stress relaxation layer 31 in a portion of the stress relaxation layer 31 that is located immediately below the end portion 10a of the semiconductor chip 10. It is assumed that the gap portion 43 is provided.

  The planar pattern of the gap 43 has a rectangular ring shape corresponding to the entire circumference of the end 10 a of the semiconductor chip 10, similar to the groove 40 shown in FIG. Also in this embodiment, the entire circumference of the end portion 10 a of the semiconductor chip 10 is located within the range of the width in the plane direction of the gap portion 43.

  The gap portion 43 is a closed space formed inside the stress relaxation layer 31. For example, the gap portion 43 is formed by laminating the stress relaxation layer 31 by laminating a plurality of plate materials or the like. It is formed by making it. Specifically, a plate material having a larger planar size than that on the front and back sides of a plate material having a smaller planar size may be laminated and then integrated by rolling or the like.

  According to the present embodiment, the portion of the void portion 43 as the warp suppressing portion of the stress relaxation layer 31 is a portion having the thinnest effective layer thickness in the stress relaxation layer 31. Therefore, the warping stress is relieved at a portion of the stress relaxation layer 31 that has a thin shape due to the gap 43.

  Also in the present embodiment, by securing the layer thickness at a portion other than the gap portion 43 in the stress relaxation layer 31, specifically, at a portion closer to the center of the stress relaxation layer 31 than the gap portion 43, Heat dissipation is ensured.

  As described above, according to the present embodiment, the warp stress is relieved at the portion of the gap 43 formed into a thin shape, that is, the warp suppressing part. The curvature in the part located in the side is suppressed. Therefore, also in this embodiment, damage to the first and second solder layers 32 and 33 due to warping of the stress relaxation layer 31 can be reduced.

  In the present embodiment, in the above-described example, the planar pattern of the gap portion 43 is a ring shape located on the entire circumference immediately below the end portion 10a of the semiconductor chip 10, but the gap portion 43 of the present embodiment. Alternatively, it may be a discontinuous plane pattern that is partially located immediately below the end 10a of the semiconductor chip 10.

(Sixth embodiment)
The semiconductor device S6 according to the sixth embodiment of the present invention will be described with reference to FIG. 6, focusing on differences from the first embodiment. In the first embodiment, the warpage suppressing portion has the groove 40 formed in the other surface 312 which is the plate surface of the stress relaxation layer 31.

  On the other hand, in the semiconductor device S6 of the present embodiment, the warp suppressing portion of the end surface 31a located on the outer periphery of the stress relaxation layer 31 extends from the end surface 31a to the end 10a of the semiconductor chip 10 in the stress relaxation layer 31. It has a groove 44 that reaches a portion located immediately below.

  Here, the groove 44 is provided on the entire circumference of the end portion 10 a of the semiconductor chip 10. Here, a part of the solder of the first and second solder layers 32 and 33 wraps around and enters the groove 44.

  According to the present embodiment, the portion where the groove 44 is present in the stress relaxation layer 31 is a portion where the layer thickness is thinner than the portion where the groove 44 is present, so that the warp is warped. The suppression part is comprised. Therefore, the warping stress is relieved at a portion of the stress relieving layer 31 that has a thin shape due to the groove 44.

  Also in the present embodiment, heat dissipation is achieved by securing a layer thickness at a portion other than the groove 44 in the stress relaxation layer 31, specifically, at a portion closer to the center of the stress relaxation layer 31 than the groove 44. Is secured.

  As described above, according to the present embodiment, since the warp stress is relieved at the portion of the groove 44 having a thin shape as the warp suppressing portion, the stress relieving layer 31 is positioned closer to the peripheral side than the groove 44. Warpage at the site to be suppressed is suppressed. Therefore, also in this embodiment, damage to the first and second solder layers 32 and 33 due to warping of the stress relaxation layer 31 can be reduced.

  Also in the present embodiment, the groove 44 may be provided not in the entire periphery of the end portion 10a of the semiconductor chip 10 but in a part thereof. Further, the groove shape of the groove 44 of the present embodiment is also V-shaped in FIG. 6 described above, but is not limited thereto, and may be, for example, U-shaped or rectangular.

(Other embodiments)
In each of the embodiments described above, the stress relaxation layer 31 was obtained by plating Ni or the like on the surface of Al that is the main material. For example, the material may be composed of at least one element of Cu, Ag, Au, Pt (platinum), Pd (palladium), Ni, and BN (boron nitride).

  Further, the plating treatment of the surface of the stress relaxation layer 31 may be omitted if the solderability of the solder layers 32 and 33 is sufficiently ensured without the plating treatment.

  Further, in each of the above embodiments, the example in which the lead frame 20 made of a metal such as Cu is adopted as the base material is shown, but the base material is not limited to the lead frame 20. That is, for example, a wiring board made of ceramic or the like may be used as the base material.

  In addition, in the semiconductor devices S1 to S6 according to the above embodiments, another lead frame 20 is provided in addition to the above-described lead frame 20, and the semiconductor chip 10 and the joining member 30 are sandwiched between the two lead frames 20. It is good also as a structure.

  Further, only one of the first solder layer 32 and the second solder layer 33 may be Pb-free solder, and the other may be solder containing Pb.

  Moreover, you may combine each above-mentioned embodiment in the possible range. Specifically, a combination of the above-described groove 40 and the inner hole 41 or a combination of the above-described groove 40 and the gap portion 43 is employed as long as the mechanical strength of the stress relaxation layer 31 is ensured. Also good.

  Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible, and the above embodiments are not limited to the illustrated examples. Absent. In each of the above-described embodiments, it is needless to say that elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Yes. Further, in each of the above embodiments, when numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, it is clearly limited to a specific number when clearly indicated as essential and in principle. The number is not limited to the specific number except for the case. Further, in each of the above embodiments, when referring to the shape, positional relationship, etc. of the component, etc., the shape, unless otherwise specified and in principle limited to a specific shape, positional relationship, etc. It is not limited to the positional relationship or the like.

DESCRIPTION OF SYMBOLS 10 Semiconductor chip 10a End part of semiconductor chip 20 Lead frame as base material 30 Joining member 31 Stress relaxation layer 32 First solder layer 33 Second solder layer 40, 44 Groove 41 as a warp suppressing part 41 As a warp suppressing part Inner hole 42 Through hole as a warpage suppressing portion 43 Gaps as a warpage suppressing portion

Claims (6)

A semiconductor chip (10);
A substrate (20) on which the semiconductor chip is mounted;
A bonding member (30) provided between the semiconductor chip and the base material for bonding the semiconductor chip and the base material;
The joining member is
A portion that relieves thermal stress generated in the joining member due to a difference in linear expansion coefficient between the semiconductor chip and the base material, and is provided between the semiconductor chip and the base material, and is mainly composed of metal. A stress relaxation layer (31) configured as follows:
A first solder layer (32) provided between the semiconductor chip and the stress relaxation layer and joining the semiconductor chip and the stress relaxation layer;
A semiconductor device provided between the stress relaxation layer and the base material and having a second solder layer (33) for joining the stress relaxation layer and the base material;
At least one of the first solder layer and the second solder layer is made of Pb-free solder not containing Pb,
The first solder layer, the second solder layer, and the stress relieving layer in the joining member are all larger in plane size than the semiconductor chip, and the peripheral portion is an end (10a) of the semiconductor chip. ) Protruding outside the
The portion of the stress relaxation layer located immediately below the end of the semiconductor chip suppresses the warp of the stress relaxation layer at the portion located on the peripheral side of the portion located directly below the end of the semiconductor chip. A semiconductor device characterized in that the warp suppressing portion (40 to 44) has a shape to be formed.   The warpage suppressing portion has a groove (40) provided on at least one of the front and back surfaces of the stress relaxation layer in a portion of the stress relaxation layer located immediately below the end of the semiconductor chip. The semiconductor device according to claim 1.   The warpage suppressing portion has an inner hole (41) provided in the stress relaxation layer in a portion of the stress relaxation layer located immediately below the end portion of the semiconductor chip. The semiconductor device according to claim 1.   The warpage suppressing portion has a through hole (42) penetrating the stress relaxation layer in the layer thickness direction at a portion of the stress relaxation layer located immediately below the end of the semiconductor chip. The semiconductor device according to claim 1.   The warpage suppressing portion has a void portion (43) provided inside the stress relaxation layer in a portion of the stress relaxation layer located immediately below the end portion of the semiconductor chip. The semiconductor device according to claim 1.   The warpage suppressing portion has a groove (44) that reaches from the end surface to a portion of the stress relaxation layer located immediately below the end portion of the semiconductor chip on the end surface (31a) positioned on the outer periphery of the stress relaxation layer. The semiconductor device according to claim 1, wherein the semiconductor device is a device.

Images