JP2016134547A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2016134547A
JP2016134547A JP2015009293A JP2015009293A JP2016134547A JP 2016134547 A JP2016134547 A JP 2016134547A JP 2015009293 A JP2015009293 A JP 2015009293A JP 2015009293 A JP2015009293 A JP 2015009293A JP 2016134547 A JP2016134547 A JP 2016134547A
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circuit pattern
layer
semiconductor device
bonding
electrode terminal
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順昭 安藤
Nobuaki Ando
順昭 安藤
洋平 大本
Yohei Omoto
洋平 大本
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device which can decrease a difference in linear expansion coefficient between a composite of a circuit pattern and an insulating substrate, and a bonding part of an electrode terminal to inhibit the occurrence of breaking around ultrasonic bonding, which is caused by a difference in linear expansion coefficient.SOLUTION: A semiconductor device according to the present embodiment comprises: an insulating substrate where a circuit pattern is formed on a surface; and an electrode terminal which is ultrasonic bonded to the circuit pattern and has a bonding part. The circuit pattern is made of Cu or Cu alloy, and the bonding part includes: a bonding layer which is made of the same material with the circuit pattern and ultrasonic bonded to the circuit pattern; and a surface layer which is laminated on the bonding layer on the side opposite to the circuit pattern and made of a material having a linear expansion coefficient smaller than that of the material of the circuit pattern.SELECTED DRAWING: Figure 2

Description

この発明は、絶縁基板の表面に形成された回路パターンと電極端子とが超音波接合される半導体装置に関するものである。   The present invention relates to a semiconductor device in which a circuit pattern formed on a surface of an insulating substrate and an electrode terminal are ultrasonically bonded.

従来の半導体装置は、表面に複数の配線パターンが形成された基板と、基板に搭載されて複数の配線パターンのうちの一部の配線パターンに電気的に接続された半導体素子と、複数の配線パターンのうちの他の配線パターンに電気的に接続されたリードを有する端子部と、を備え、端子部のリードは、銅を主成分とする部材とアルミニウムを主成分とする部材とを積層して構成され、他の配線パターンは、銅で形成され、リードを構成するアルミニウムを主成分とする部材が、他の配線パターンに超音波接合により電気的に接続されていた（例えば、特許文献１参照）。   A conventional semiconductor device includes a substrate having a plurality of wiring patterns formed on a surface thereof, a semiconductor element mounted on the substrate and electrically connected to a part of the plurality of wiring patterns, and a plurality of wirings A terminal portion having a lead electrically connected to another wiring pattern of the pattern, and the lead of the terminal portion is formed by laminating a member mainly composed of copper and a member mainly composed of aluminum. The other wiring pattern is made of copper, and a member mainly composed of aluminum constituting the lead is electrically connected to the other wiring pattern by ultrasonic bonding (for example, Patent Document 1). reference).

特開２０１３−５１３６６号公報JP 2013-51366 A

従来の半導体装置では、異種金属同士を超音波接合しているので、同じ金属同士を超音波接合する場合に比べて、接合強度が低下する。さらに、アルミニウムを主成分とする部材は銅を主成分とする部材より線膨張係数が大きいので、銅を主成分とする部材とアルミニウムを主成分とする部材とを積層して構成されたリードの線膨張係数は、銅で形成された他の配線パターンより大きくなる。そこで、使用環境などによって半導体装置自体が繰り返し温度変化すると、線膨張係数差に起因する熱応力が超音波接合部に繰り返し作用する。そのため、超音波接合部の端部を起点に亀裂が発生し、その亀裂が進展して、超音波接合部付近が破壊するという恐れがあった。   In the conventional semiconductor device, since different metals are ultrasonically bonded to each other, the bonding strength is reduced as compared with the case where the same metals are ultrasonically bonded. Furthermore, since a member whose main component is aluminum has a larger linear expansion coefficient than a member whose main component is copper, a lead formed by laminating a member whose main component is copper and a member whose main component is aluminum is laminated. The linear expansion coefficient is larger than that of other wiring patterns formed of copper. Therefore, when the temperature of the semiconductor device itself is repeatedly changed depending on the use environment or the like, the thermal stress caused by the difference in linear expansion coefficient repeatedly acts on the ultrasonic bonding portion. For this reason, there is a risk that a crack is generated starting from the end of the ultrasonic bonding portion, the crack develops, and the vicinity of the ultrasonic bonding portion is broken.

この発明は、上記課題を解決するためになされたもので、回路パターンと絶縁基板の複合体と、電極端子の接合部と、の線膨張係数差を小さくして、線膨張係数差に起因する超音波接合部付近での破壊の発生を抑制できる半導体装置を得ることを目的とする。   The present invention has been made to solve the above-described problems, and is caused by the difference in the linear expansion coefficient between the circuit pattern / insulating substrate composite and the electrode terminal joint, which is reduced. An object of the present invention is to obtain a semiconductor device capable of suppressing the occurrence of breakage in the vicinity of an ultrasonic bonded portion.

この発明に係る半導体装置は、表面に回路パターンが形成された絶縁基板と、上記回路パターンに超音波接合された接合部を有する電極端子と、を備え、上記回路パターンは、ＣｕまたはＣｕ合金で作製され、上記接合部が、上記回路パターンと同じ材料で作製され、上記回路パターンと超音波接合される接合層と、上記接合層の上記回路パターンと反対側に積層され、上記回路パターンの材料より線膨張係数が小さい表層と、から構成されている。   A semiconductor device according to the present invention includes an insulating substrate having a circuit pattern formed on a surface thereof, and an electrode terminal having a bonding portion ultrasonically bonded to the circuit pattern. The circuit pattern is made of Cu or Cu alloy. The joint portion is made of the same material as the circuit pattern, and is laminated on the side opposite to the circuit pattern of the joining layer, the joining layer to be ultrasonically joined to the circuit pattern, and the material of the circuit pattern. And a surface layer having a smaller linear expansion coefficient.

この発明によれば、接合層と回路パターンとが同じ材料で作製されているので、接合強度が大きくなる。また、表層の線膨張係数が回路パターンの材料の線膨張係数より小さいので、接合部の線膨張係数が、接合部が回路パターンと同じ材料のみで作製されている場合にくべて小さくなる。そこで、回路パターンと絶縁基板の複合体と、接合部と、の線膨張係数差が小さくなり、半導体装置の温度変化に起因して超音波接合部に作用する熱応力が小さくなる。これにより、線膨張係数差に起因する超音波接合部付近での破壊の発生が抑制される。   According to this invention, since the bonding layer and the circuit pattern are made of the same material, the bonding strength is increased. In addition, since the linear expansion coefficient of the surface layer is smaller than the linear expansion coefficient of the material of the circuit pattern, the linear expansion coefficient of the joint portion becomes smaller when the joint portion is made of only the same material as the circuit pattern. Therefore, the difference in linear expansion coefficient between the composite of the circuit pattern and the insulating substrate and the bonding portion is reduced, and the thermal stress acting on the ultrasonic bonding portion due to the temperature change of the semiconductor device is reduced. As a result, the occurrence of breakage near the ultrasonic bonded portion due to the difference in linear expansion coefficient is suppressed.

この発明の実施の形態１に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to Embodiment 1 of the present invention. この発明の実施の形態１に係る半導体装置における電極端子の接合部の構成を説明する図である。It is a figure explaining the structure of the junction part of the electrode terminal in the semiconductor device which concerns on Embodiment 1 of this invention. この発明の実施の形態１に係る半導体装置における超音波接合方法を説明する図である。It is a figure explaining the ultrasonic bonding method in the semiconductor device concerning Embodiment 1 of this invention. この発明の実施の形態１に係る半導体装置における回路パターンと電極端子との超音波接合部を示す要部断面図である。It is principal part sectional drawing which shows the ultrasonic junction part of the circuit pattern and electrode terminal in the semiconductor device which concerns on Embodiment 1 of this invention. この発明の実施の形態２に係る半導体装置における電極端子の接合部の構成を説明する図である。It is a figure explaining the structure of the junction part of the electrode terminal in the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置における超音波接合方法を説明する要部断面図である。It is principal part sectional drawing explaining the ultrasonic bonding method in the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態２に係る半導体装置における回路パターンと電極端子との超音波接合部を示す要部断面図である。It is principal part sectional drawing which shows the ultrasonic junction part of the circuit pattern and electrode terminal in the semiconductor device which concerns on Embodiment 2 of this invention. この発明の実施の形態３に係る半導体装置における電極端子の接合部の構成を説明する図である。It is a figure explaining the structure of the junction part of the electrode terminal in the semiconductor device which concerns on Embodiment 3 of this invention.

以下、本発明の半導体装置の好適な実施の形態につき図面を用いて説明する。   Hereinafter, preferred embodiments of a semiconductor device of the present invention will be described with reference to the drawings.

実施の形態１．
図１はこの発明の実施の形態１に係る半導体装置を示す断面図、図２はこの発明の実施の形態１に係る半導体装置における電極端子の接合部の構成を説明する図であり、図２の（ａ）は接合部周りを示す斜視図、図２の（ｂ）は接合部周りを示す断面図である。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a diagram for explaining the configuration of electrode terminal joints in the semiconductor device according to the first embodiment of the present invention. (A) of FIG. 2 is a perspective view showing the periphery of the joint, and FIG.

図１において、半導体装置１は、ケース型と呼ばれるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）パワーモジュールであり、ベース板２と、ベース板２上に固定された絶縁基板３と、絶縁基板３の裏面に形成された金属パターン４と、絶縁基板３の表面に形成された回路パターン５と、回路パターン５上に固定された半導体チップ６と、回路パターン５と外部電源（図示せず）とを電気的、かつ機械的に接続する電極端子８と、半導体チップ６の電極７と回路パターン５とを電気的、かつ機械的に接続する金属ワイヤ９と、樹脂製のケース１０と、を備えている。   In FIG. 1, a semiconductor device 1 is an IGBT (Insulated Gate Bipolar Transistor) power module called a case type, and is formed on a back surface of a base plate 2, an insulating substrate 3 fixed on the base plate 2, and the insulating substrate 3. Electrically connecting the formed metal pattern 4, the circuit pattern 5 formed on the surface of the insulating substrate 3, the semiconductor chip 6 fixed on the circuit pattern 5, the circuit pattern 5 and an external power source (not shown), In addition, an electrode terminal 8 that is mechanically connected, a metal wire 9 that electrically and mechanically connects the electrode 7 of the semiconductor chip 6 and the circuit pattern 5, and a resin case 10 are provided.

ベース板２には、例えば、純Ａｌ、Ａｌ合金、純Ｃｕ、Ｃｕ合金、Ａｌ−ＳｉＣ、ＡｌＣ、Ｃｕ−Ｍｏなどの金属板が用いられる。絶縁基板３には、例えば、ＡｌＮ、Ａｌ２Ｏ３、Ｓｉ３Ｎ４などのセラミック基板や、ガラスエポキシ樹脂基板などが用いられる。金属パターン４には、純ＣｕまたはＣｕを主成分とするＣｕ合金が用いられ、ベース板２とはんだ１１で接合するために、絶縁基板３の裏面の比較的広い面積、または全面に形成されている。回路パターン５には、導電性の高い純ＣｕまたはＣｕを主成分とするＣｕ合金が用いられ、絶縁基板３の表面に形成されている。 For the base plate 2, for example, a metal plate such as pure Al, Al alloy, pure Cu, Cu alloy, Al—SiC, AlC, or Cu—Mo is used. As the insulating substrate 3, for example, a ceramic substrate such as AlN, Al 2 O 3 , Si 3 N 4 or a glass epoxy resin substrate is used. For the metal pattern 4, pure Cu or a Cu alloy containing Cu as a main component is used, and the metal pattern 4 is formed on a relatively wide area or the entire back surface of the insulating substrate 3 in order to join the base plate 2 with the solder 11. Yes. The circuit pattern 5 is made of pure Cu having high conductivity or a Cu alloy containing Cu as a main component, and is formed on the surface of the insulating substrate 3.

電極端子８は、図２に示されるように、厚さが１〜２ｍｍ、幅が数ｍｍの帯状体に構成され、回路パターン５と接合するために折り曲げられたネック部１２を有する。そして、ネック部１２の先端側が平坦な接合部１３となる。接合部１３は、接合層１４と表層１５とを厚さ方向に積層した２層構造となっている。そして、電極端子８の表層１５を除く部分は、回路パターン５と同じ材料、すなわちＣｕまたはＣｕ合金で作製されている。また、表層１５は、接合層１４の材料であるＣｕまたはＣｕ合金より線膨張係数の小さい材料である、Ｆｅ、Ｔｉ、Ｎｉ、Ｍｏ、Ｃｒ、Ａｕ、又はそれらの合金などで作製されている。   As shown in FIG. 2, the electrode terminal 8 is formed in a belt-like body having a thickness of 1 to 2 mm and a width of several mm, and has a neck portion 12 that is bent to be joined to the circuit pattern 5. And the front end side of the neck part 12 becomes the flat junction part 13. FIG. The joining portion 13 has a two-layer structure in which the joining layer 14 and the surface layer 15 are laminated in the thickness direction. And the part except the surface layer 15 of the electrode terminal 8 is produced with the same material as the circuit pattern 5, ie, Cu or Cu alloy. The surface layer 15 is made of Fe, Ti, Ni, Mo, Cr, Au, or an alloy thereof, which is a material having a smaller linear expansion coefficient than Cu or a Cu alloy that is a material of the bonding layer 14.

つぎに、回路パターン５と電極端子８との超音波接合方法について図３および図４を参照しつつ説明する。図３はこの発明の実施の形態１に係る半導体装置における超音波接合方法を説明する図であり、図３の（ａ）はその斜視図であり、図３の（ｂ）は図３の（ａ）のＡ−Ａ’矢斜断面図である。図４はこの発明の実施の形態１に係る半導体装置における回路パターンと電極端子との超音波接合部を示す要部断面図である。   Next, an ultrasonic bonding method between the circuit pattern 5 and the electrode terminal 8 will be described with reference to FIGS. 3 is a view for explaining an ultrasonic bonding method in the semiconductor device according to the first embodiment of the present invention, FIG. 3 (a) is a perspective view thereof, and FIG. 3 (b) is a view of FIG. It is AA 'arrow cross-sectional view of a). FIG. 4 is a cross-sectional view of a main part showing an ultrasonic bonding portion between the circuit pattern and the electrode terminal in the semiconductor device according to the first embodiment of the present invention.

電極端子８を回路パターン５に接合するには、図３の（ａ）に示されるように、接合層１４が回路パターン５に接するように接合部１３を回路パターン５に重ね合わせる。ついで、超音波接合ツール１６を接合部１３の表層１５上に載置し、荷重負荷方向１７に押圧しながら振動方向１８に超音波振動を印加する。これにより、図３の（ｂ）に示されるように、超音波接合ツール１６の押圧面１６ａに形成された突起１９が表層１５に食い込み、超音波振動が接合部１３に伝達され、金属表面にあった汚れや酸化膜が除去され、回路パターン５と接合層１４とが接合される。   In order to bond the electrode terminal 8 to the circuit pattern 5, the bonding portion 13 is overlapped with the circuit pattern 5 so that the bonding layer 14 is in contact with the circuit pattern 5, as shown in FIG. Next, the ultrasonic bonding tool 16 is placed on the surface layer 15 of the bonding portion 13, and ultrasonic vibration is applied in the vibration direction 18 while pressing in the load loading direction 17. Thereby, as shown in FIG. 3 (b), the protrusion 19 formed on the pressing surface 16a of the ultrasonic bonding tool 16 bites into the surface layer 15, and the ultrasonic vibration is transmitted to the bonding portion 13 to be applied to the metal surface. The dirt and oxide film that have been removed are removed, and the circuit pattern 5 and the bonding layer 14 are bonded.

超音波接合後、表層１５の表面には、図４に示されるように、突起１９の食い込みよる圧痕２０が残っている。また、超音波接合ツール１６による押圧部の真下位置、すなわち圧痕２０の真下位置に、回路パターン５と接合層１４との超音波接合部２１が形成されている。   After ultrasonic bonding, as shown in FIG. 4, an indentation 20 due to the biting of the protrusion 19 remains on the surface of the surface layer 15. In addition, an ultrasonic bonding portion 21 between the circuit pattern 5 and the bonding layer 14 is formed at a position directly below the pressing portion by the ultrasonic bonding tool 16, that is, a position directly below the indentation 20.

この実施の形態１によれば、電極端子８の接合部１３が、ＣｕまたはＣｕ合金で作製された接合層１４と、ＣｕまたはＣｕ合金より線膨張係数の小さい材料で作製された表層１５と、からなる２層構造となっているので、接合部１３の線膨張係数は、接合部がＣｕまたはＣｕ合金のみで作製されている場合よりも小さくなる。そこで、回路パターン５と絶縁基板３の複合体と、接合部１３と、の間の線膨張係数差は、回路パターン５と絶縁基板３の複合体と、ＣｕまたはＣｕ合金のみで作製された接合部と、の間の線膨張係数差より小さくなる。そこで、半導体装置１が温度変化した際に、線膨張係数差に起因して超音波接合部２１に作用する熱応力が小さくなる。また、接合部１３の接合層１４が回路パターン５と同じ材料で作製されているので、接合強度が大きくなる。これにより、半導体装置１の温度変化に起因する、超音波接合部２１の端部を起点とした亀裂の発生や亀裂の進展を抑制でき、超音波接合部２１付近での破壊の発生を防ぐことができる。   According to the first embodiment, the bonding portion 13 of the electrode terminal 8 includes a bonding layer 14 made of Cu or Cu alloy, and a surface layer 15 made of a material having a smaller linear expansion coefficient than Cu or Cu alloy, Therefore, the linear expansion coefficient of the joint portion 13 is smaller than when the joint portion is made of only Cu or Cu alloy. Therefore, the difference in linear expansion coefficient between the composite of the circuit pattern 5 and the insulating substrate 3 and the joint 13 is a joint made of only the composite of the circuit pattern 5 and the insulating substrate 3 and Cu or Cu alloy. And the linear expansion coefficient difference between the two parts becomes smaller. Therefore, when the temperature of the semiconductor device 1 changes, the thermal stress acting on the ultrasonic bonding portion 21 due to the difference in linear expansion coefficient is reduced. In addition, since the bonding layer 14 of the bonding portion 13 is made of the same material as the circuit pattern 5, the bonding strength is increased. As a result, it is possible to suppress the occurrence of cracks starting from the end of the ultrasonic bonding portion 21 and the progress of the crack caused by the temperature change of the semiconductor device 1, and prevent the occurrence of breakage near the ultrasonic bonding portion 21. Can do.

電極端子の全体が異種金属からなる２層構造となっている場合には、半導体装置１の温度変化により電極端子がバイメタル効果により反り、超音波接合部２１に引っ張り荷重が作用する。この実施の形態１では、電極端子８の接合部１３の表層１５を除く部分がＣｕまたはＣｕ合金で作製されているので、バイメタル効果に起因する引っ張り荷重が超音波接合部２１に作用することがなく、超音波接合部２１の接合信頼性が高められる。   When the entire electrode terminal has a two-layer structure made of different metals, the electrode terminal warps due to the temperature change of the semiconductor device 1 due to the bimetal effect, and a tensile load acts on the ultrasonic bonding portion 21. In this Embodiment 1, since the part except the surface layer 15 of the junction part 13 of the electrode terminal 8 is produced with Cu or Cu alloy, the tensile load resulting from a bimetal effect may act on the ultrasonic junction part 21. FIG. In addition, the bonding reliability of the ultrasonic bonding portion 21 is improved.

ここで、表層１５は、接合部１３の超音波接合ツール１６により押圧される側に形成されていればよく、超音波接合ツール１６の押圧面１６ａよりもコンマ数ｍｍ〜数ｍｍ程度大きい範囲に形成されるのが好ましい。表層１５の形成範囲が超音波接合ツール１６の押圧面１６ａよりも小さい範囲であれば、超音波接合時に超音波接合ツール１６が表層１５と電極端子８を跨がって押圧することになる。表層１６と電極端子８は剛性が異なり、超音波接合ツール１６の押圧による変形量が異なるため、超音波接合部２１に生じる圧力に偏りができ、超音波接合部２１の強度が低下する可能性がある。
また、上記実施の形態１では、表層１５は電極端子８の接合部１３近傍と面一に形成されているが、表層１５は必ずしも電極端子８の接合部１３近傍と面一に形成される必要はない。 Here, the surface layer 15 should just be formed in the side pressed by the ultrasonic bonding tool 16 of the junction part 13, and is in the range larger than the comma several mm-several mm than the pressing surface 16a of the ultrasonic bonding tool 16. Preferably it is formed. If the formation range of the surface layer 15 is a range smaller than the pressing surface 16 a of the ultrasonic bonding tool 16, the ultrasonic bonding tool 16 presses across the surface layer 15 and the electrode terminal 8 during ultrasonic bonding. Since the surface layer 16 and the electrode terminal 8 have different rigidity and different deformation amounts due to the pressure of the ultrasonic bonding tool 16, the pressure generated in the ultrasonic bonding portion 21 can be biased, and the strength of the ultrasonic bonding portion 21 may be reduced. There is.
In the first embodiment, the surface layer 15 is formed flush with the vicinity of the joint portion 13 of the electrode terminal 8, but the surface layer 15 is not necessarily formed flush with the vicinity of the joint portion 13 of the electrode terminal 8. There is no.

実施の形態２．
図５はこの発明の実施の形態２に係る半導体装置における電極端子の接合部の構成を説明する図であり、図５の（ａ）は接合部周りを示す斜視図、図５の（ｂ）は接合部周りを示す断面図である。図６はこの発明の実施の形態２に係る半導体装置における超音波接合方法を説明する要部断面図、図７はこの発明の実施の形態２に係る半導体装置における回路パターンと電極端子との超音波接合部を示す要部断面図である。 Embodiment 2. FIG.
FIG. 5 is a view for explaining the structure of the joint portion of the electrode terminal in the semiconductor device according to the second embodiment of the present invention. FIG. 5 (a) is a perspective view showing the periphery of the joint portion, and FIG. 5 (b). FIG. 3 is a cross-sectional view showing the periphery of a joint. FIG. 6 is a cross-sectional view of an essential part for explaining the ultrasonic bonding method in the semiconductor device according to the second embodiment of the present invention, and FIG. It is principal part sectional drawing which shows a sound wave junction part.

図５において、電極端子８Ａの接合部１３Ａは、接合層１４と、超音波接合ツール１６が挿入される穴部２２を有するように接合層１４上に枠状に形成された表層１５Ａと、から構成されている。穴部２２は、超音波接合時に、表層１５Ａが超音波接合ツール１６と干渉しないように、超音波接合ツール１６の押圧面１６ａより大きくなっている。
なお、他の構成は、上記実施の形態１と同様に構成されている。 In FIG. 5, the joining portion 13A of the electrode terminal 8A includes a joining layer 14 and a surface layer 15A formed in a frame shape on the joining layer 14 so as to have a hole portion 22 into which the ultrasonic joining tool 16 is inserted. It is configured. The hole 22 is larger than the pressing surface 16a of the ultrasonic bonding tool 16 so that the surface layer 15A does not interfere with the ultrasonic bonding tool 16 during ultrasonic bonding.
Other configurations are the same as those in the first embodiment.

実施の形態２では、電極端子８Ａを回路パターン５に接合するには、図６に示されるように、接合層１４が回路パターン５に接するように接合部１３Ａを回路パターン５に重ね合わせる。ついで、超音波接合ツール１６を接合部１３Ａの穴部２２内に差し入れ、荷重負荷方向１７に押圧しながら振動方向１８に超音波振動を印加する。これにより、超音波接合ツール１６の突起１９が穴部２２内に露出する接合層１４に食い込み、超音波振動が接合層１４に伝達され、金属表面にあった汚れや酸化膜が除去され、回路パターン５と接合層１４とが接合される。   In the second embodiment, in order to join the electrode terminal 8A to the circuit pattern 5, the joining portion 13A is superimposed on the circuit pattern 5 so that the joining layer 14 is in contact with the circuit pattern 5, as shown in FIG. Next, the ultrasonic bonding tool 16 is inserted into the hole 22 of the bonding portion 13 </ b> A, and ultrasonic vibration is applied in the vibration direction 18 while pressing in the load loading direction 17. As a result, the protrusion 19 of the ultrasonic bonding tool 16 bites into the bonding layer 14 exposed in the hole 22, and ultrasonic vibration is transmitted to the bonding layer 14 to remove dirt and oxide film on the metal surface, thereby The pattern 5 and the bonding layer 14 are bonded.

超音波接合後、穴部２２内に露出する接合層１４の表面には、図７に示されるように、突起１９の食い込みよる圧痕２０が残っている。また、超音波接合ツール１６による押圧部の真下位置、すなわち圧痕２０の真下位置に、回路パターン５と接合層１４との超音波接合部２１が形成されている。   After the ultrasonic bonding, as shown in FIG. 7, an indentation 20 due to the biting of the protrusion 19 remains on the surface of the bonding layer 14 exposed in the hole 22. In addition, an ultrasonic bonding portion 21 between the circuit pattern 5 and the bonding layer 14 is formed at a position directly below the pressing portion by the ultrasonic bonding tool 16, that is, a position directly below the indentation 20.

半導体装置が温度変化した際に超音波接合部２１に発生する熱応力は、超音波接合部２１の外周部が最も大きくなる。実施の形態２では、ｚ軸方向から見て、表層１５Ａが、超音波接合部２１の外周部に近接して超音波接合部２１を取り囲むように配置されている。そこで、超音波接合部２１の周りの接合部１３Ａの線膨張係数が小さくなり、半導体装置の温度変化に起因して超音波接合部２１の外周部に発生する熱応力が小さくなる。また、接合層１４が回路パターン５と同じ材料で作製されているので、接合強度が大きくなる。したがって、実施の形態２においても、半導体装置の温度変化に起因する超音波接合部２１付近での破壊の発生が抑制される。   The thermal stress generated in the ultrasonic bonding portion 21 when the temperature of the semiconductor device changes is greatest at the outer peripheral portion of the ultrasonic bonding portion 21. In the second embodiment, the surface layer 15 </ b> A is disposed so as to surround the ultrasonic bonding portion 21 in the vicinity of the outer peripheral portion of the ultrasonic bonding portion 21 when viewed from the z-axis direction. Therefore, the linear expansion coefficient of the bonding portion 13A around the ultrasonic bonding portion 21 is reduced, and the thermal stress generated in the outer peripheral portion of the ultrasonic bonding portion 21 due to the temperature change of the semiconductor device is reduced. In addition, since the bonding layer 14 is made of the same material as the circuit pattern 5, the bonding strength is increased. Therefore, also in the second embodiment, the occurrence of destruction near the ultrasonic bonding portion 21 due to the temperature change of the semiconductor device is suppressed.

接合層１４の剛性は表層１５Ａの剛性より小さい。実施の形態２では、超音波接合ツール１６が剛性の小さい接合層１４を直接押圧しているので、超音波接合ツール１６に押圧される部位の塑性変形量が大きくなり、超音波接合部２１の接合強度が大きくなる。したがって、実施の形態２によれば、半導体装置の温度変化に起因する超音波接合部２１付近での破壊の発生をより抑制できる。   The rigidity of the bonding layer 14 is smaller than the rigidity of the surface layer 15A. In the second embodiment, since the ultrasonic bonding tool 16 directly presses the bonding layer 14 having low rigidity, the amount of plastic deformation of the portion pressed by the ultrasonic bonding tool 16 increases, and the ultrasonic bonding portion 21 Bonding strength is increased. Therefore, according to the second embodiment, it is possible to further suppress the occurrence of destruction near the ultrasonic bonding portion 21 due to the temperature change of the semiconductor device.

なお、上記実施の形態２では、穴部２２はｚ方向から見て四角形の穴形状に形成されているが、穴部２２は、超音波接合時に、表層１５Ａが超音波接合ツール１６と干渉しない穴形状であればよく、例えば円形、楕円形でもよい。
また、上記実施の形態２では、穴部２２が表層１５Ａを貫通するように形成されているが、穴部は表層を貫通しないように形成され、超音波接合ツール１６が接触する領域を薄肉としてもよい。 In the second embodiment, the hole 22 is formed in a square hole shape when viewed from the z direction. However, the hole 22 does not interfere with the ultrasonic bonding tool 16 in the surface layer 15A during ultrasonic bonding. Any hole shape may be used, for example, a circle or an ellipse.
In the second embodiment, the hole 22 is formed so as to penetrate the surface layer 15A. However, the hole is formed so as not to penetrate the surface layer, and the region where the ultrasonic bonding tool 16 contacts is made thin. Also good.

実施の形態３．
図８はこの発明の実施の形態３に係る半導体装置における電極端子の接合部の構成を説明する図であり、図８の（ａ）は接合部周りを示す斜視図、図８の（ｂ）は接合部周りを示す断面図である。 Embodiment 3 FIG.
8A and 8B are views for explaining the configuration of the electrode terminal bonding portion in the semiconductor device according to the third embodiment of the present invention. FIG. 8A is a perspective view showing the periphery of the bonding portion, and FIG. FIG. 3 is a cross-sectional view showing the periphery of a joint.

図８において、電極端子８Ｂの接合部１３Ｂは、接合層１４と、表層１５Ｂと、から構成されている。表層１５Ｂは、接合層１４側の下層２３ａと、接合層１４と逆側の上層２３ｂと、の２層構造となっている。下層２３ａは、ＣｕまたはＣｕ合金より線膨張係数の小さい材料、すなわち実施の形態１における表層１５と同じ材料で作製されている。上層２３ｂは、ＣｕまたはＣｕ合金、すなわち接合層１４と同じ材料で作製されている。さらに、上層２３ｂの厚さｔ１は、接合層１４の厚さｔ２と同じである。
なお、他の構成は上記実施の形態１と同様に構成されている。 In FIG. 8, the joining part 13B of the electrode terminal 8B is comprised from the joining layer 14 and the surface layer 15B. The surface layer 15B has a two-layer structure of a lower layer 23a on the bonding layer 14 side and an upper layer 23b on the opposite side to the bonding layer 14. Lower layer 23a is made of a material having a smaller linear expansion coefficient than Cu or Cu alloy, that is, the same material as surface layer 15 in the first embodiment. The upper layer 23b is made of the same material as that of Cu or a Cu alloy, that is, the bonding layer 14. Furthermore, the thickness t1 of the upper layer 23b is the same as the thickness t2 of the bonding layer 14.
Other configurations are the same as those in the first embodiment.

実施の形態３では、表層１５Ｂが、ＣｕまたはＣｕ合金より線膨張係数の小さい材料で作製された下層２３ａと、ＣｕまたはＣｕ合金で作製された上層２３ｂと、の２層構造に構成されているので、接合部１３Ｂの線膨張係数は、接合部がＣｕまたはＣｕ合金のみで作製されている場合よりも小さくなる。また、接合層１４が回路パターン５と同じ材料で作製されているので、接合強度が大きくなる。したがって、実施の形態３においても、半導体装置の温度変化に起因する超音波接合部２１付近での破壊の発生が抑制される。   In the third embodiment, the surface layer 15B has a two-layer structure of a lower layer 23a made of a material having a smaller linear expansion coefficient than Cu or Cu alloy and an upper layer 23b made of Cu or Cu alloy. Therefore, the linear expansion coefficient of the joint portion 13B is smaller than when the joint portion is made of only Cu or Cu alloy. In addition, since the bonding layer 14 is made of the same material as the circuit pattern 5, the bonding strength is increased. Therefore, also in the third embodiment, the occurrence of destruction near the ultrasonic bonding portion 21 due to the temperature change of the semiconductor device is suppressed.

実施の形態３では、表層１５Ｂが、接合層１４より線膨張係数の小さい材料で作製された下層２３ａと、接合層１４と同じ材料で、接合層１４と同じ厚さに形成された上層２３ｂと、の２層構造に構成されている。そこで、接合部１３Ｂは、その厚さ方向の中心を通る面に対して対称な構造となっており、温度が高くなった際の伸び量が、接合部１３Ｂの厚さ方向の中心を通る面の接合層１４側と上層２３ｂ側とで等しくなる。これにより、半導体装置の温度変化に起因する接合部１３Ｂの反りの発生が抑制されるので、超音波接合部２１付近での破壊の発生をより抑制できる。   In the third embodiment, the surface layer 15B includes a lower layer 23a made of a material having a smaller linear expansion coefficient than the bonding layer 14, and an upper layer 23b formed of the same material as the bonding layer 14 and the same thickness as the bonding layer 14. , And a two-layer structure. Therefore, the joint portion 13B has a symmetric structure with respect to the plane passing through the center in the thickness direction, and the amount of elongation when the temperature is increased passes through the center in the thickness direction of the joint portion 13B. The bonding layer 14 side and the upper layer 23b side are equal. As a result, the occurrence of warpage of the bonding portion 13B due to the temperature change of the semiconductor device is suppressed, so that the occurrence of destruction near the ultrasonic bonding portion 21 can be further suppressed.

ここで、実施の形態３では、穴部が表層１５Ｂに形成されていないが、上記実施の形態２と同様に、表層１５Ｂを貫通するように穴部を形成すれば、上記実施の形態２と同様の効果が得られる。   Here, in Embodiment 3, the hole is not formed in the surface layer 15B. However, as in Embodiment 2, if the hole is formed so as to penetrate the surface layer 15B, Similar effects can be obtained.

なお、本発明は、発明の範囲内において、各実施の形態を自由に組み合わせることや、各実施の形態の一部を変形や省略することができる。
また、上記各実施の形態において、電極端子および回路パターンの酸化防止を目的として、電極端子および回路パターンの表面にＮｉなどのメッキ処理を施してもよい。 In the present invention, the embodiments can be freely combined within the scope of the invention, and a part of the embodiments can be modified or omitted.
In each of the above embodiments, the surface of the electrode terminal and the circuit pattern may be plated with Ni or the like for the purpose of preventing oxidation of the electrode terminal and the circuit pattern.

１ 半導体装置、３ 絶縁基板、５ 回路パターン、８，８Ａ，８Ｂ 電極端子、１３，１３Ａ，１３Ｂ 接合部、１４ 接合層、１５，１５Ａ，１５Ｂ 表層、１６ 超音波接合ツール、２２ 穴部、２３ａ 下層、２３ｂ 上層。   DESCRIPTION OF SYMBOLS 1 Semiconductor device, 3 Insulation board | substrate, 5 Circuit pattern, 8, 8A, 8B Electrode terminal, 13, 13A, 13B Bonding part, 14 Bonding layer, 15, 15A, 15B Surface layer, 16 Ultrasonic bonding tool, 22 Hole part, 23a Lower layer, 23b Upper layer.

Claims (5)

表面に回路パターンが形成された絶縁基板と、上記回路パターンに超音波接合された接合部を有する電極端子と、を備えた半導体装置において、
上記回路パターンは、ＣｕまたはＣｕ合金で作製され、
上記接合部が、上記回路パターンと同じ材料で作製され、上記回路パターンと超音波接合される接合層と、上記接合層の上記回路パターンと反対側に積層され、上記回路パターンの材料より線膨張係数が小さい表層と、から構成されている半導体装置。 In a semiconductor device comprising: an insulating substrate having a circuit pattern formed on a surface; and an electrode terminal having a bonding portion ultrasonically bonded to the circuit pattern.
The circuit pattern is made of Cu or Cu alloy,
The joint is made of the same material as the circuit pattern, and is laminated on the side opposite to the circuit pattern of the joining layer, the joining layer to be ultrasonically joined to the circuit pattern, and linearly expanded from the material of the circuit pattern. A semiconductor device comprising a surface layer having a small coefficient. 上記表層は、上記回路パターンの材料より線膨張係数の小さい材料で作製された単一層に構成されている請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the surface layer is configured as a single layer made of a material having a smaller linear expansion coefficient than the material of the circuit pattern. 上記表層は、上記接合層の上記回路パターンと反対側に積層され、上記回路パターンの材料より線膨張係数の小さい材料で作製された下層と、上記下層の上記接合層と反対側に積層され、上記接合層と同じ材料で、上記接合層と同じ厚さに作製された上層と、からなる２層構造に構成されている請求項１記載の半導体装置。   The surface layer is laminated on the side opposite to the circuit pattern of the bonding layer, a lower layer made of a material having a smaller linear expansion coefficient than the material of the circuit pattern, and laminated on the side opposite to the bonding layer of the lower layer, The semiconductor device according to claim 1, wherein the semiconductor device is configured in a two-layer structure including an upper layer made of the same material as the bonding layer and having the same thickness as the bonding layer. 上記電極端子の上記接合部を除く部分が、上記接合層と同じ材料で作製されている請求項１から請求項３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a portion of the electrode terminal excluding the bonding portion is made of the same material as the bonding layer. 5. 超音波接合ツールが差し込まれる穴部が、上記表層の上記接合層と反対側に凹設されている請求項１から請求項４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein a hole portion into which the ultrasonic bonding tool is inserted is recessed on the surface layer opposite to the bonding layer. 6.
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Cited By (2)

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DE102020200099A1 (en) 2019-01-15 2020-07-16 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device
JP2020526927A (en) * 2017-07-10 2020-08-31 アー・ベー・ベー・パワー・グリッズ・スウィツァーランド・アクチェンゲゼルシャフトＡｂｂ Ｐｏｗｅｒ Ｇｒｉｄｓ Ｓｗｉｔｚｅｒｌａｎｄ Ａｇ Power semiconductor module containing metallized dimples below the terminal legs

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020526927A (en) * 2017-07-10 2020-08-31 アー・ベー・ベー・パワー・グリッズ・スウィツァーランド・アクチェンゲゼルシャフトＡｂｂ Ｐｏｗｅｒ Ｇｒｉｄｓ Ｓｗｉｔｚｅｒｌａｎｄ Ａｇ Power semiconductor module containing metallized dimples below the terminal legs
JP7233407B2 (en) 2017-07-10 2023-03-06 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト Power semiconductor module containing dimples in the metallization layer below the legs of the terminals
DE102020200099A1 (en) 2019-01-15 2020-07-16 Mitsubishi Electric Corporation Method of manufacturing a semiconductor device
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