JPS63308944A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63308944A JPS63308944A JP62144011A JP14401187A JPS63308944A JP S63308944 A JPS63308944 A JP S63308944A JP 62144011 A JP62144011 A JP 62144011A JP 14401187 A JP14401187 A JP 14401187A JP S63308944 A JPS63308944 A JP S63308944A
- Authority
- JP
- Japan
- Prior art keywords
- bottom plate
- heat dissipating
- ceramic substrate
- heat dissipation
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000919 ceramic Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000005219 brazing Methods 0.000 claims description 6
- 230000005496 eutectics Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔4既 要〕
セラミック基板にロー付けした放熱用底板にチップを搭
載した半導体装置であって、該放熱用底板のチップ搭載
位置の周囲に溝を設けたことにより、セラミック基板と
放熱用底板との熱的特性の違いによる応力によりセラミ
ック基板に生ずるクランクの発生を防止可能とする。[Detailed Description of the Invention] [4 Already Required] A semiconductor device in which a chip is mounted on a heat dissipation bottom plate brazed to a ceramic substrate, in which a groove is provided around the chip mounting position of the heat dissipation bottom plate. It is possible to prevent the occurrence of cranks in the ceramic substrate due to stress due to the difference in thermal characteristics between the ceramic substrate and the heat dissipation bottom plate.
〔産業上の利用分野]
本発明は半導体装置に関するもので、さらに詳しく言へ
ば、放熱用底板との熱膨張率の差によりセラミック基板
に生ずるクランクを防止した半導体装置に関するもので
ある。[Industrial Field of Application] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that prevents cranking from occurring in a ceramic substrate due to a difference in coefficient of thermal expansion with a heat dissipating bottom plate.
第3図は従来の半導体装置の1例を示す図である。これ
は中央に貫通穴を有するセラミック基板lの一方の面に
施されたメタライズ2の上にロー材3を用いてロー付け
された放熱用底板4の前記基板貫通穴部分に半導体チッ
プ5をAu/Si共晶によりチップ付けし、その電極と
基板1の端子6からのリード線間を細線7でワイヤポン
ディングし、さらに放熱川底板4に放り゛ハ用フィン8
を樹脂9で接着したものである。この半導体装置の各構
成部材には第1表に示す材料が用いられ、その熱的特性
は同表に示す通りである。FIG. 3 is a diagram showing an example of a conventional semiconductor device. This is a heat dissipation bottom plate 4 which is soldered using a brazing material 3 onto the metallization 2 applied to one side of a ceramic substrate l having a through hole in the center. A chip is attached using /Si eutectic, wire bonding is performed between the electrode and the lead wire from the terminal 6 of the substrate 1 using a thin wire 7, and the fin 8 for heat dissipation is placed on the bottom plate 4.
are glued together with resin 9. The materials shown in Table 1 are used for each component of this semiconductor device, and the thermal characteristics thereof are shown in the same table.
第1表
〔発明が解決しようとする問題点〕
上記従来の半導体装置では、セラミック基板1、ロー材
3、放熱用底板4間の熱的特性の差により組立時(チッ
プ搭載時)にセラミック基板1に第4図の如く放熱用底
板4の外周に沿ってクラック10が発生し、またサーマ
ルショック試験時にも同様のクラックが発生するという
問題があった。Table 1 [Problems to be Solved by the Invention] In the conventional semiconductor device described above, due to the difference in thermal characteristics between the ceramic substrate 1, brazing material 3, and heat dissipation bottom plate 4, the ceramic substrate 1, there was a problem in that cracks 10 occurred along the outer periphery of the heat dissipation bottom plate 4 as shown in FIG. 4, and similar cracks also occurred during the thermal shock test.
本発明はこのような点にかんがみて創作されたもので、
セラミック基板に発生するクランクを防止した半導体装
置を提供することを目的としている。The present invention was created in view of these points.
The object of the present invention is to provide a semiconductor device that prevents cranks from occurring on a ceramic substrate.
〔問題点を解決するための手段]
このため本発明においては、第1図に例示するように、
中央部に貫通した穴が設けられ且つ該穴の周囲にメタラ
イズ2が施されたセラミック基板1と、該基板1のメタ
ライズ面にロー材3を用いてロー付けされた放熱川底板
4と、該放熱用底板4に固着された半導体チップ5とよ
りなる半導体装置において、−上記放熱用底板4のチッ
プ搭載位置の周囲に溝11を設けたことを特徴としてい
る。[Means for solving the problem] Therefore, in the present invention, as illustrated in FIG.
A ceramic substrate 1 having a hole passing through the center and having metallization 2 applied around the hole; a heat dissipation bottom plate 4 soldered to the metallized surface of the substrate 1 using a brazing material 3; A semiconductor device comprising a semiconductor chip 5 fixed to a heat dissipating base plate 4 is characterized in that a groove 11 is provided around the chip mounting position of the heat dissipating base plate 4.
〔作 用]
放熱用底板4のチップ搭載位置の周囲に溝11を設けた
ことにより、セラミック基板1と放熱用底板4との熱的
特性の差による応力を緩和することができ、セラミック
基板に生ずるクラックを防止することが可能となる。[Function] By providing the groove 11 around the chip mounting position of the heat dissipation bottom plate 4, stress due to the difference in thermal characteristics between the ceramic substrate 1 and the heat dissipation bottom plate 4 can be alleviated, and the ceramic substrate It becomes possible to prevent cracks from occurring.
第1図は本発明の実施例を示す図であり、aは断面図、
bはa図のZ天方向から見た放熱用底板を示す図である
。FIG. 1 is a diagram showing an embodiment of the present invention, in which a is a cross-sectional view;
b is a diagram showing the heat dissipation bottom plate viewed from the Z-top direction in diagram a;
本実施例は同図に示すように、中央に貫通穴を有するセ
ラミック基板1の一方の面に施されたメタライズ2の上
にロー材3によりロー付けされた放熱用底板4の前記基
板貫通穴部分に半導体チップ5をAu/Si共晶により
チップ付けし、その電極と基板1の端子6からのリード
線間を細線7でワイヤボンディングし、さらに放熱用底
板4に放熱用フィン8を樹脂9で接着していることは第
3図で説明した従来例と同様であり、本実施例の要点は
、放熱用底板4のチップ搭載位置の周囲に溝11を設け
たことである。As shown in the figure, in this embodiment, a heat dissipating bottom plate 4 is brazed with a brazing material 3 onto a metallization 2 formed on one side of a ceramic substrate 1 having a through hole in the center. A semiconductor chip 5 is attached to the part using Au/Si eutectic, wire bonding is performed between the electrode and the lead wire from the terminal 6 of the substrate 1 using a thin wire 7, and a heat dissipating fin 8 is attached to the heat dissipating bottom plate 4 using resin 9. This is the same as the conventional example explained in FIG. 3, and the key point of this embodiment is that a groove 11 is provided around the chip mounting position of the heat dissipation bottom plate 4.
このように構成された本実施例は、セラミック基板1と
放熱用底板4との熱的特性の違いにより生ずる応力を前
記溝10に集中させることによりセラミック基板1に生
ずる応力を緩和させることができ、それにより放熱用底
板の外周に沿って生ずるクラックの発生を防止すること
ができる。In this embodiment configured as described above, the stress generated in the ceramic substrate 1 can be alleviated by concentrating the stress generated due to the difference in thermal characteristics between the ceramic substrate 1 and the heat dissipation bottom plate 4 in the groove 10. This makes it possible to prevent cracks from occurring along the outer periphery of the heat dissipation bottom plate.
第2図は本発明の他の実施例を示す図であり、第1図と
同一部分は同一符号を付して示した。FIG. 2 is a diagram showing another embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.
本実施例が前実施例と異なるところは、411を放熱用
底板4の両面に設けたことであり、その効果は前実施例
と同様である。This embodiment differs from the previous embodiment in that 411 is provided on both sides of the heat dissipation bottom plate 4, and the effect is the same as that of the previous embodiment.
〔発明の効果]
以上述べてきたように、本発明によれば、極めて簡単な
構成で、放熱用底板との熱的特性の違いによりセラミッ
ク基板に生ずるクラックの発生を防出でき、実用的には
極めて有用である。[Effects of the Invention] As described above, according to the present invention, with an extremely simple configuration, it is possible to prevent the occurrence of cracks in the ceramic substrate due to the difference in thermal characteristics with the heat dissipation bottom plate, and it is practical. is extremely useful.
第1図は本発明の実施例を示す図、
第2図は本発明の他の実施例を示す図、第3図は従来の
放熱用底板付半導体装置を示す断面図、
第4図は従来の半導体装置の問題点を説明するための図
である。
第1図、第2図において、
1はセラミック基板、
2はメタライズ、
3はロー材、
4は放熱用底板、
5は半導体チップ、
8は放熱フィン、
11は溝である。
特許出願代理人Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing another embodiment of the invention, Fig. 3 is a sectional view showing a conventional semiconductor device with a bottom plate for heat dissipation, and Fig. 4 is a conventional diagram. FIG. 3 is a diagram for explaining problems of the semiconductor device of FIG. In FIGS. 1 and 2, 1 is a ceramic substrate, 2 is metallized, 3 is a brazing material, 4 is a heat dissipation bottom plate, 5 is a semiconductor chip, 8 is a heat dissipation fin, and 11 is a groove. patent application agent
Claims (1)
タライズ(2)が施されたセラミック基板(1)と、該
基板(1)のメタライズ面にロー材(3)を用いてロー
付けされた放熱用底板(4)と、該放熱用底板(4)に
固着された半導体チップ(5)とよりなる半導体装置に
おいて、 上記放熱用底板(4)のチップ搭載位置の周囲に溝(1
1)を設けたことを特徴とした半導体装置。[Claims] 1. A ceramic substrate (1) with a hole passing through the center and metallized (2) around the hole, and a brazing material (2) on the metallized surface of the substrate (1). 3) A semiconductor device comprising a heat dissipating base plate (4) soldered using a heat dissipating base plate (4) and a semiconductor chip (5) fixed to the heat dissipating base plate (4), wherein the chip is mounted on the heat dissipating base plate (4). A groove (1
A semiconductor device characterized by having 1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62144011A JPS63308944A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62144011A JPS63308944A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63308944A true JPS63308944A (en) | 1988-12-16 |
Family
ID=15352245
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62144011A Pending JPS63308944A (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63308944A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021237856A1 (en) * | 2020-05-27 | 2021-12-02 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method therefor, and display panel |
US11695015B2 (en) | 2020-05-27 | 2023-07-04 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate, method of manufacturing the same, and display panel |
-
1987
- 1987-06-11 JP JP62144011A patent/JPS63308944A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2021237856A1 (en) * | 2020-05-27 | 2021-12-02 | 武汉华星光电半导体显示技术有限公司 | Array substrate, preparation method therefor, and display panel |
US11695015B2 (en) | 2020-05-27 | 2023-07-04 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate, method of manufacturing the same, and display panel |
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