JPH0621237Y2 - Ceramic package - Google Patents
Ceramic packageInfo
- Publication number
- JPH0621237Y2 JPH0621237Y2 JP1987114866U JP11486687U JPH0621237Y2 JP H0621237 Y2 JPH0621237 Y2 JP H0621237Y2 JP 1987114866 U JP1987114866 U JP 1987114866U JP 11486687 U JP11486687 U JP 11486687U JP H0621237 Y2 JPH0621237 Y2 JP H0621237Y2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- ceramic package
- present
- metal pedestal
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】 〔概要〕 本考案は、セラミックパッケージの構造に関し、 半導体チップをセラミックパッケージに固着するとき、
熱膨脹の差によって該チップにクラックが発生するのを
防止することを目的とし、 セラミックパッケージの基体の上に、空洞部が形成され
た半導体チップ固着用メタル台座を設けていることを特
徴としている。[Detailed Description of the Invention] [Outline] The present invention relates to a structure of a ceramic package, wherein when a semiconductor chip is fixed to the ceramic package,
For the purpose of preventing cracks from being generated in the chip due to the difference in thermal expansion, a semiconductor pedestal fixing metal pedestal in which a cavity is formed is provided on the base of the ceramic package.
本考案はセラミックパッケージの構造に関するものであ
る。The present invention relates to a ceramic package structure.
第４図は従来例に係るセラミックパッケージの構造断面
図である。FIG. 4 is a structural sectional view of a ceramic package according to a conventional example.
１はセラミック基体，２は半導体チップ，３はボンディ
ングワイヤである。４はセラミック基体の表面に作成さ
れたAuペースト又はAuメッキであり、５は半導体チップ
２をセラミック基体１に固着するためのAu又はAuSiであ
る。1 is a ceramic substrate, 2 is a semiconductor chip, and 3 is a bonding wire. Reference numeral 4 is an Au paste or Au plating formed on the surface of the ceramic substrate, and 5 is Au or AuSi for fixing the semiconductor chip 2 to the ceramic substrate 1.
ところで、従来例によれば、熱を加えてAu又はAuSi５を
溶融し、半導体チップ２をセラミック基体１の表面に直
接固着している。By the way, according to the conventional example, heat is applied to melt Au or AuSi 5, and the semiconductor chip 2 is directly fixed to the surface of the ceramic substrate 1.
このため、半導体チップ２とセラミック基体１との熱膨
脹係数の差により半導体チップにストレスが加わり、半
導体チップにクラックが生じる等の問題がある。Therefore, there is a problem that stress is applied to the semiconductor chip due to the difference in coefficient of thermal expansion between the semiconductor chip 2 and the ceramic substrate 1, and the semiconductor chip is cracked.
本考案はかかる従来の問題に鑑みて創作されたものであ
り、半導体チップにクラックが発生するのを防止するこ
とのできるセラミックパッケージの提供を目的とする。The present invention was created in view of the above conventional problems, and an object of the present invention is to provide a ceramic package capable of preventing a semiconductor chip from cracking.
本考案は、第１図に示すように、セラミック基体１の上
に空洞部７を有するメタル台座６を設けており、半導体
チップ２はAuペースト又はAuメッキ４およびAu又はAuSi
５を介して該メタル部６の上に固着する構成となってい
る。According to the present invention, as shown in FIG. 1, a metal pedestal 6 having a cavity 7 is provided on a ceramic substrate 1, and a semiconductor chip 2 is Au paste or Au plating 4 and Au or AuSi.
It is configured to be fixed on the metal portion 6 via 5.
半導体チップ２をメタル台座６の上に固着する際に熱を
加えてAuペースト又はAuメッキ４およびAu又はAuSi５を
溶融するが、このとき熱膨脹係数の差によってストレス
が生じる。しかし、このストレスは空洞部７を有するメ
タル台座６により効率良く吸収することができるので、
半導体チップに加わるストレスを軽減することができ
る。When the semiconductor chip 2 is fixed on the metal pedestal 6, heat is applied to melt the Au paste or Au plating 4 and Au or AuSi5. At this time, stress is generated due to the difference in thermal expansion coefficient. However, since this stress can be efficiently absorbed by the metal pedestal 6 having the cavity 7,
It is possible to reduce the stress applied to the semiconductor chip.
次に図を参照しながら本考案の実施例について説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第２図は本考案の実施例に係るセラミックパッケージを
説明する断面図である。図において、８はセラミック基
体，９は該セラミック基体の上に形成されたタングステ
ン（Ｗ）からなるメタライズ層，１０はその上に形成さ
れたNiメッキである。FIG. 2 is a sectional view illustrating a ceramic package according to an embodiment of the present invention. In the figure, 8 is a ceramic substrate, 9 is a metallization layer made of tungsten (W) formed on the ceramic substrate, and 10 is Ni plating formed thereon.
１１は本考案のメタル台座であって、Niメッキ１２され
たコバール材によって形成されており、空洞部１５を有
している。このメタル台座はロー材（Ag又はCu）１３に
よりセラミック基体８に固着されている。また、１４は
全体に形成されたAuメッキである。Reference numeral 11 denotes a metal pedestal of the present invention, which is made of Ni-plated Kovar material 12 and has a cavity 15. This metal pedestal is fixed to the ceramic base 8 with a brazing material (Ag or Cu) 13. Further, 14 is Au plating formed on the entire surface.
本考案の実施例によれば、半導体チップをメタル台座に
固着する際に熱を加えてAuペースト又はAuメッキ４およ
びAu又はAuSi５を溶融するが、このときの熱膨脹差によ
る該半導体チップに加わるストレスをメタル台座によっ
て効率良く吸収することができるので、半導体チップに
クラックが発生するのを防止することができる。According to the embodiment of the present invention, when the semiconductor chip is fixed to the metal pedestal, heat is applied to melt the Au paste or Au plating 4 and Au or AuSi5, but stress applied to the semiconductor chip due to the difference in thermal expansion at this time. Since the metal pedestal can be efficiently absorbed, it is possible to prevent the semiconductor chip from being cracked.
第３図（ａ），（ｂ）は本考案の別の実施例に係るメタ
ル台座の形状を示す図である。このような形態のメタル
台座も空洞部を備えているので、熱によるストレスを効
率良く吸収することが可能となる。3 (a) and 3 (b) are views showing the shape of a metal pedestal according to another embodiment of the present invention. Since the metal pedestal of such a form also has the hollow portion, it becomes possible to efficiently absorb the stress due to heat.
以上説明したように、本考案によればセラミックパッケ
ージ内に設けたメタル台座の上に半導体チップを固着す
る構成であるから、固着する際の熱によるストレスを該
メタルに台座により吸収することが可能となる。このた
め、半導体チップに加わるストレスを軽減することがで
きるので、半導体チップにクラックが発生するのを防止
することが可能となる。As described above, according to the present invention, since the semiconductor chip is fixed on the metal pedestal provided in the ceramic package, it is possible to absorb the stress due to heat at the time of fixing to the metal by the pedestal. Becomes Therefore, the stress applied to the semiconductor chip can be reduced, so that it is possible to prevent the semiconductor chip from being cracked.
第１図は本考案のセラミックパッケージを説明する断面
図、 第２図は本考案の実施例に係るセラミックパッケージを
説明する図、 第３図は本考案の別の実施例に係るメタル台座を説明す
る図、 第４図は従来例に係るセラミックパッケージを説明する
図である。 （符号の説明） １，８…セラミック基体、 ２…半導体チップ、 ３…ボンディングワイヤ、 ４…Auペースト又はAuメッキ、 ５…Au又はAuSi、 ６…メタル台座、 ７，１５…空洞部、 ９…メタライズ層（Ｗ）、 １０，１２…Niメッキ、 １１…コバール材、 １３…ロー材（Ag,Cu）、 １４…Auメッキ。1 is a cross-sectional view illustrating a ceramic package of the present invention, FIG. 2 is a view illustrating a ceramic package according to an embodiment of the present invention, and FIG. 3 is a metal pedestal according to another embodiment of the present invention. 4 and FIG. 4 are views for explaining a ceramic package according to a conventional example. (Explanation of reference numerals) 1, 8 ... Ceramic substrate, 2 ... Semiconductor chip, 3 ... Bonding wire, 4 ... Au paste or Au plating, 5 ... Au or AuSi, 6 ... Metal pedestal, 7, 15 ... Cavity part, 9 ... Metallized layer (W), 10, 12 ... Ni plating, 11 ... Kovar material, 13 ... Raw material (Ag, Cu), 14 ... Au plating.
Claims (1)
ージにおいて、 セラミック基体に固着され、該セラミック基体との間に
空洞部を備えるメタル台座と、 該メタル台座に固着された半導体チップとを有すること
を特徴とするセラミックパッケージ。1. A ceramic package for storing a semiconductor chip, comprising: a metal pedestal fixed to a ceramic base and having a cavity between the ceramic base; and a semiconductor chip fixed to the metal pedestal. And ceramic package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114866U JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114866U JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6420727U JPS6420727U (en) | 1989-02-01 |
| JPH0621237Y2 true JPH0621237Y2 (en) | 1994-06-01 |
Family
ID=31356000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987114866U Expired - Lifetime JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621237Y2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111050A (en) * | 1980-12-26 | 1982-07-10 | Fujitsu Ltd | Semiconductor device |
| US4415025A (en) * | 1981-08-10 | 1983-11-15 | International Business Machines Corporation | Thermal conduction element for semiconductor devices |
| JPS6183041U (en) * | 1984-11-07 | 1986-06-02 |
-
1987
- 1987-07-27 JP JP1987114866U patent/JPH0621237Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6420727U (en) | 1989-02-01 |
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