JPS62147736A - Method for mounting semiconductor element - Google Patents
Method for mounting semiconductor elementInfo
- Publication number
- JPS62147736A JPS62147736A JP28877985A JP28877985A JPS62147736A JP S62147736 A JPS62147736 A JP S62147736A JP 28877985 A JP28877985 A JP 28877985A JP 28877985 A JP28877985 A JP 28877985A JP S62147736 A JPS62147736 A JP S62147736A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor element
- metal foil
- elements
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体素子を装置基
板に搭載する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a method for mounting a semiconductor element on a device substrate.
従来、半導体素子を装置基枡に搭載するには、第３図の
断面図に示すように、ウェーハから個々に分割された半
導体素子２０を、あらかじめ金メツキ１２等でメタライ
ズされた装置基数８の半魯体素子搭載部に、共晶合金、
半田、または樹脂接着材などの接合材１３により、８１
の半導体素子２０を押しつけるか、甘たは、こすりつけ
て（スクラブして）搭載）ていた。Conventionally, in order to mount semiconductor elements on a device base, as shown in the cross-sectional view of FIG. Eutectic alloy in the half-metal element mounting part,
81 by a bonding material 13 such as solder or resin adhesive.
The semiconductor element 20 was mounted by pressing it or, better yet, rubbing it (scrubbing).
しかしながら、従来の技術においては、素子の大型化、
消費゛ルカの増大に伴ない、半導体系子の接合性が極め
て嵐要になってきており、半導体素子の搭載には、基敬
材との接合強度、並びに熱放散性がより一／ｌ’！求さ
れている。However, in the conventional technology, the size of the element and
With the increase in energy consumption, the bonding properties of semiconductor devices have become extremely important, and when mounting semiconductor devices, bonding strength with the base material and heat dissipation properties are becoming more important. ! being sought after.
接合方法は、接合材の種類により、主に三つに分類され
、共晶合金法、半田接合法、樹脂接着法が挙げられる。Bonding methods are mainly classified into three types depending on the type of bonding material, including eutectic alloy method, solder bonding method, and resin bonding method.
この中で、共晶合金法が最も接合強度、熱放散性が萬＜
、広く一般に使用きれていルカ、反面コストが高い。こ
れとは逆に、後者の二号法は、コストが低く、作票性も
高いが、接合強度および熱放散性において劣る。Among these, the eutectic alloy method has the highest bonding strength and heat dissipation.
However, it is not widely used, but on the other hand, it is expensive. On the contrary, the latter method No. 2 is low in cost and has high formability, but is inferior in bonding strength and heat dissipation.
共晶合金法には、Ａｕ−８ｉの共晶合金法が広く用いら
れ、半導体素子の８ｉと基板に施したＡｕメッキとを、
共晶点以上の温度の下にこすりつけることによって形成
し、接合を完了させる。この方法には、Ａｕ ８ｉロ
ウ材を供給したり、又は、累子儀面にＡｕのメタライズ
をあらかじめ九して、共晶合金化を促進させてやること
もある。しかしながら、大型半導体素子は、基板の平坦
度との影瞥、また、荷厘スジラブ振幅の制限を受けて、
十分な接合面を形成することが難しくなり、半導体素子
裏面の中央、若しくは周辺部に共晶合金の未反応部分が
生じる。この未反応部分は、熱ストレスを受けた除、熱
膨張差の歪により、半導体素子にクラックを引き起こす
こととなる。The eutectic alloy method of Au-8i is widely used, and the 8i of the semiconductor element and the Au plating applied to the substrate are
The bond is formed by rubbing at a temperature above the eutectic point to complete the bond. In this method, eutectic alloying may be promoted by supplying Au 8i brazing material or by pre-metallizing Au on the cylindrical surface. However, large semiconductor devices are limited by the flatness of the substrate and the amplitude of the load strip.
It becomes difficult to form a sufficient bonding surface, and an unreacted portion of the eutectic alloy occurs in the center or periphery of the back surface of the semiconductor element. This unreacted portion will cause cracks in the semiconductor element due to distortion caused by the difference in thermal expansion when subjected to thermal stress.
本発明の半導体索子搭載方法は、あらかじめ、ウェーハ
裏面にプリフォームされた合金ロウ材で金属箔を完全な
状態に接合し、個々の素子に分割した後、装置基板の搭
載部に前記金属箔面をロウ材により接合し搭載するもの
である。In the method for mounting a semiconductor cable of the present invention, a metal foil is completely bonded in advance using a preformed alloy brazing material on the back side of a wafer, and after dividing into individual elements, the metal foil is placed on a mounting portion of a device board. The surfaces are joined with brazing material and mounted.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）ないしｔｄｌは不発明の搭載方法を説明す
るための工程１［の斜視図（ａｌおよび町面図１ｂ）〜
（ｄ）である。まず、第１図ｔｄｌのように、予じめＡ
ｕ−８ｉロウ材２が被着された８１ウエーノ１１を、Ｎ
還元雰囲気中若しくはＪｃ空中において、共晶点以上の
温度を加え、Ｓｉ ＋７ ｘ−／％ １上のＡｕ−８ｉ
ｏり材２ｔ−溶融する。その状態時に、第１図（ｂ）の
ように、金属箔３をボイドが入らない様にウエーノ１１
に徐々に互層し、Ａｕ Ｓｉ共晶合釡層５でもって金
属箔３とウエーノ）１を固着する。この時の金属箔は、
Ｓｉ と熱Ｗｅ張の近イコバー７’（Ｆｅ−２８Ｎｉ
−１８Ｃｏ）、４２アロイ（Ｆｅ−４２Ｎｉ ） ’＃
が選択対象となり、厚さは、数十ミクロン以下が適当で
ある。Figures 1(a) to tdl are perspective views (al and town plan 1b) of process 1 for explaining the uninvented loading method.
(d). First, as shown in Fig. 1 tdl, A
N
In a reducing atmosphere or in Jc air, a temperature above the eutectic point is applied to Au-8i on Si +7
2t of oring material - melt. In this state, as shown in FIG.
The metal foil 3 and the wafer 1 are bonded together by the Au-Si eutectic alloy layer 5. The metal foil at this time is
Near 7' (Fe-28Ni) of Si and thermal We
-18Co), 42 alloy (Fe-42Ni)'#
is selected, and the appropriate thickness is several tens of microns or less.
また、Ａｕメッキ４が施され、適度な小さい穴があけら
れていると良い。つぎに、第１図（Ｃ）のように、Ｓｉ
ウェーハ１をスクライブ綴６に沿いＩｆ！ｔｌ々の半導
体素子１０に分割する。それから、第１図（ｄｌのよう
に、銀メツキ９等を施した装置基板８上に銀ペースト寺
の樹脂接眉剤、または〔Ｓ ｎ −２５Ａｇ−ｔｏｓｂ
） 吟の手出合金７を用いで半導体素子１０を固シ１
搭載する。It is also good if Au plating 4 is applied and appropriately small holes are drilled. Next, as shown in Fig. 1(C), Si
If! wafer 1 along scribe line 6! It is divided into tl semiconductor elements 10. Then, as shown in FIG.
) Harden the semiconductor element 10 using Gin's Tade Alloy 7
Mount.
第２図（ａ） 、 （ｂ）は本発明の他の実Ｍ例につい
て説明するだめの断面図である。第２図１８）は、金属
箔３ｆ：接層したウェーハ１に、さらに、金属箔面に半
纏体素子搭載用の銀ペーストロウ材１１を形成した状態
を示し、同図（ｂ）は、銀ベーストロウ材の破着された
ウェーハを個々の半導体素子２０に分割した状態を示す
。その後、半導体素子２０を、第１図（ｄ）のように、
装ｆｉｔ基板に搭載する。FIGS. 2(a) and 2(b) are sectional views for explaining another practical example of the present invention. FIG. 2 18) shows a state in which a silver paste solder material 11 for mounting a semi-integrated element is further formed on the metal foil surface on the wafer 1 in contact with the metal foil 3f, and FIG. A state in which the wafer with the base tow material broken is divided into individual semiconductor devices 20 is shown. After that, as shown in FIG. 1(d), the semiconductor element 20 is
Mount it on the mounting board.
以上説明したように本発明は、ウエーノＳ晟面にあらか
じめ施した合金ロウ拐により金属箔を接合し、それから
個々の半導体素子に分割した恢、装置基板に、合金半日
または樹脂嶺看例で搭載することにより、半導体素子の
Ｓｉ晟面に安定かつ十分な合金層を形成することで、ｂ
ｉ艮面の濡れ性を同上し、ボイド福回赳することができ
る。こうして、Ｓｉ裏■に金鵬鳩を設けることにより、
たとえこの釜属ノ１Ｆの接合で小゛イド、鴻γし不足が
兄生じても、８４＊聞の部分的熱ストレスは葦林番箔に
より分散緩和さｎ１午尋体系子のククツク臀の１４否は
回遊することができる。”、ｆｆｃｌ この１求に、ボ
イドなく菫属箔を板層した半導体素子は、装置基板に１
戊ト威点半田、または、ｌＶ（脂做眉創で容易に搭載す
ることが可能となり、匝来に比べ、半導体素子搭載の除
に行なわｎ″Ｃいたスクラブなどは直方省略することが
でき、この工性を而）噴することができる。As explained above, the present invention involves bonding a metal foil by applying an alloy brazing process to the surface of Ueno S in advance, and then dividing the semiconductor elements into individual semiconductor elements. By forming a stable and sufficient alloy layer on the Si surface of the semiconductor device, b
The wettability of the surface is the same as above, and it is possible to eliminate voids. In this way, by providing the gold dove on the back side of Si,
Even if a shortcoming occurs due to small id and heat γ in the joint of this pot genus 1F, the partial heat stress of 84 * time will be dispersed and alleviated by Ashibayashi banhaku, and the 14 No, you can go around. ", ffcl According to this first request, a semiconductor element with a plate layer of violet foil without voids can be fabricated with one layer on the device board.
It is now possible to easily mount it with soldering or LV (fatty eyebrows), and compared to the conventional method, it is possible to omit the scrubbing that is done before mounting the semiconductor element. This technique can be ejected.
使米、この半導体索子の搭載に除しては装置基叡の恰祇
部の形状及びｌｆＩ槓による影＃を受けていた平坦度、
若しくは、スクラブ低部、荷重の制約が、間接的に８１
手樽体系子の合金ロウ材による；宗れ性具合に反映して
いた点から、本発明の半導１２１ｉ：菓子のｉ載方法に
よりＳｉ半廊体素子の均一、かつ、安定な接合面の噌れ
性は半導体索子の接合５虫度並びに熱敢畝注の同上を生
み、大型化、消費電力の増大に対処できるものとなる。In addition to the mounting of this semiconductor cable, the shape of the base of the device and the flatness that was affected by the lfI turret,
Or, the scrub lower part, load constraint may indirectly be 81
Due to the alloy brazing material of the hand-barrel type element; from the point of view that it was reflected in the degree of warping resistance, the semiconductor 121i of the present invention: A uniform and stable bonding surface of the Si half-wall element was achieved by the i-mounting method of the confectionery. The elasticity produces the same degree of bonding of semiconductor cords as well as the same as that of hot ridge injection, and it becomes possible to cope with the increase in size and power consumption.
また、半導不素子のｆｆｉ載を安定かつ簡略に行うこと
が可能となる。Furthermore, it becomes possible to stably and simply mount semiconductor non-conductive elements on the ffi.
第１図（ａ）ないしくｄ）は本発明の一実施例を説明す
るための工程順の糾祝図（ａ）、町面図＋ｂｌ〜ｔｄ）
である。
、５ｇ２図（ａ） 、 ｔｂ）は本発明の他の実施例を
説明するための断面図、８ｇ３図は従来の方法で搭載さ
れた半得体素子と取付袈ｆｉｔ基板を示す断面図である
。
１・・・・・・８ｉ１７エーハ、２・・・・・・Ａｕ−
８ｉロク材、３・・・・・・金橋箔（コバール）、４・
・・・・・Ａｕメッキ虐、５・・・・・・Ａｕ−８ｉ共
晶合金ノー、６・・・・・・スクライプ迩、７・・・・
・手出、８・・・・・装置基板、９・・・・・・罎メッ
キ層、１０．２０・・・・・・半導体索子、１１・・・
・・・Ａｇペース８ Ｉ 区Figure 1 (a) to d) is a concluding diagram of the process order for explaining one embodiment of the present invention (a), town map + bl to td)
It is. , 5g2 (a) and tb) are cross-sectional views for explaining other embodiments of the present invention, and 8g3 are cross-sectional views showing a semiconductor element and a fitting board mounted by a conventional method. 1...8i17Aha, 2...Au-
8i Roku material, 3...Kanbashi foil (Kovar), 4.
...Au plating, 5...Au-8i eutectic alloy, 6...Scripe, 7...
- Output, 8... Device board, 9... Plating layer, 10.20... Semiconductor wire, 11...
...Ag Pace 8 I Ward
Claims (1)
金属箔の固着されたウェーハを個々の半導体素子に分割
する工程と、前記半導体素子の金属箔面を装置基板に固
着搭載する工程とを含むことを特徴とする半導体素子の
搭載方法。 ２）上記ウェーハの金属箔への固着は、プリフォームさ
れた金属合金、或いは、樹脂接着剤によりなされること
を特徴とする特許請求の範囲第１項の半導体素子の搭載
方法。 ３）上記金属箔は、前記ウェーハと熱膨張の近い金属で
、厚さは５０ミクロン以下であり、しかも、前記固着す
る金属となじむ合金層が形成されていることを特徴とす
る特許請求の範囲第１項の半導体素子の搭載方法。[Claims] 1) A step of fixing a metal foil to one surface of a semiconductor wafer and then dividing the wafer to which the metal foil is attached into individual semiconductor elements, and fixing the metal foil surface of the semiconductor element to a device substrate. A method for mounting a semiconductor element, comprising the step of mounting. 2) The method for mounting a semiconductor element according to claim 1, wherein the wafer is fixed to the metal foil using a preformed metal alloy or a resin adhesive. 3) The metal foil is a metal whose thermal expansion is similar to that of the wafer, has a thickness of 50 microns or less, and has an alloy layer formed thereon that is compatible with the fixed metal. 1. Method for mounting a semiconductor element according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28877985A JPS62147736A (en) | 1985-12-20 | 1985-12-20 | Method for mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28877985A JPS62147736A (en) | 1985-12-20 | 1985-12-20 | Method for mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62147736A true JPS62147736A (en) | 1987-07-01 |
Family
ID=17734604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28877985A Pending JPS62147736A (en) | 1985-12-20 | 1985-12-20 | Method for mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62147736A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0352242A (en) * | 1989-07-20 | 1991-03-06 | Matsushita Electric Ind Co Ltd | Junction-metal-film forming and diebonding methods |
| EP0552466A2 (en) * | 1992-01-24 | 1993-07-28 | Honda Giken Kogyo Kabushiki Kaisha | Method for joining semiconductor substrates |
-
1985
- 1985-12-20 JP JP28877985A patent/JPS62147736A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0352242A (en) * | 1989-07-20 | 1991-03-06 | Matsushita Electric Ind Co Ltd | Junction-metal-film forming and diebonding methods |
| EP0552466A2 (en) * | 1992-01-24 | 1993-07-28 | Honda Giken Kogyo Kabushiki Kaisha | Method for joining semiconductor substrates |
| EP0552466A3 (en) * | 1992-01-24 | 1996-08-07 | Honda Motor Co Ltd | Method for joining semiconductor substrates |
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