JPH0352242A - Junction-metal-film forming and diebonding methods - Google Patents
Junction-metal-film forming and diebonding methodsInfo
- Publication number
- JPH0352242A JPH0352242A JP1187850A JP18785089A JPH0352242A JP H0352242 A JPH0352242 A JP H0352242A JP 1187850 A JP1187850 A JP 1187850A JP 18785089 A JP18785089 A JP 18785089A JP H0352242 A JPH0352242 A JP H0352242A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- bonding metal
- wafer
- foil
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 29
- 239000002184 metal Substances 0.000 claims abstract description 63
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000011888 foil Substances 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 37
- 239000011521 glass Substances 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000001105 regulatory effect Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 20
- 239000011800 void material Substances 0.000 description 5
- 238000010030 laminating Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
- H01L2224/75302—Shape
- H01L2224/75303—Shape of the pressing surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置のウェハに接合金属膜を形成する方
法、及びそのウェハから得たチップを用いて被ポンディ
ング体上にポンディングする方法に関するものであり、
例えばパワーＩＣ等のチップから発生した熱を放散させ
るために、このチップと回路基板の間に介装されるヒー
トシンクにチップをボンディングする場合等に好適に適
用できるグイボンディング方法に関するものである．従
来の技術
従来、ヒートシンクにチップを接合する際には、第６図
に示すように、ヒートシンク３０を、ヒータ３２にて加
熱されたトンネル炉３１内に挿入し、Ｎ，ガスとＨ８ガ
スの混合ガス雰囲気中で搬送しながら加熱し、このトン
ネル炉３１の土壁の所定位置に形成した開口部３３から
ヒートシンク３０上に半田箔３４を装着し、トンネル炉
３１内を搬送される間にこの半田ｗＩ３４を溶融させて
溶融半田ｗＡ３５を形成し、その後トンネル炉３１の後
方位置で土壁に形成した開口部３６から、ヒートシンク
３０上にチップ３７を装着している．なお、チップ３７
の接合面には、銀又は金を蒸着した下地処理層３Ｂが形
成されている．
発明が解決しようとする課題
しかしながら、溶融半田膜３５は、チップ３７の接合面
に形成された下地処理層３８の銀又は金に対して濡れ性
が高くないために、チップ３７を載置して接合した場合
、第７図に示すように、チップ３７と溶融半田膜３５の
間にかみこんだ気体により空隙（ボイド）３９が発生し
易く、チップ３７の動作時の発熱によってこのボイド３
９内のガスが膨張してチップ３７にクランクを発生した
り、ストレスのために特性に悪影響を与えるという問題
があった．
又、トンネル炉３１内を高度に不活性又は還元性ガス雰
囲気にしないと、このトンネル炉３１内を搬送される間
に溶融半田膜３５が酸化して適正な接合状態が得られな
いため、ガスの消費量が多くなりしかも酸化し易いとい
う問題があった。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming a bonding metal film on a wafer of a semiconductor device, and a method of bonding a chip obtained from the wafer onto an object to be bonded. and
The present invention relates to a bonding method that can be suitably applied, for example, to bonding a chip to a heat sink interposed between the chip and a circuit board in order to dissipate heat generated from the chip, such as a power IC. Conventionally, when bonding a chip to a heat sink, as shown in FIG. 6, the heat sink 30 is inserted into a tunnel furnace 31 heated by a heater 32, and a mixture of N gas and H8 gas is The solder foil 34 is heated while being transported in a gas atmosphere, and is attached onto the heat sink 30 through an opening 33 formed at a predetermined position in the earthen wall of this tunnel furnace 31 . After melting wI34 to form molten solder wA35, a chip 37 is mounted on the heat sink 30 through an opening 36 formed in the earthen wall at the rear of the tunnel furnace 31. In addition, chip 37
A base treatment layer 3B, in which silver or gold is vapor-deposited, is formed on the bonding surface. Problems to be Solved by the Invention However, since the molten solder film 35 does not have high wettability with respect to the silver or gold of the base treatment layer 38 formed on the bonding surface of the chip 37, it is difficult to place the chip 37 on it. When bonded, as shown in FIG. 7, voids 39 are likely to be generated due to the gas trapped between the chip 37 and the molten solder film 35, and the voids 39 are likely to be formed due to the heat generated during operation of the chip 37.
There was a problem in that the gas in the chip 9 expanded, causing the chip 37 to crank, and the stress adversely affecting the characteristics. Furthermore, unless the inside of the tunnel furnace 31 is made into a highly inert or reducing gas atmosphere, the molten solder film 35 will be oxidized while being transported through the tunnel furnace 31 and a proper bonding state will not be obtained. There was a problem that the consumption amount was large and it was easy to oxidize.
本発明は上記従来の問題点に鑑み、ウェハに接合金属膜
を形成する方法、及びそのウェハから得たチップを用い
ることによりボンディングしたときに接合金属部にボイ
ドが発生せず、かつ加熱接合時に不活性又は還元性雰囲
気に保つためのガス消費量を少なくできるとともに接合
金属が酸化し難いグイボンディング方法を提供すること
を目的とする．
課題を解決するための手段
本発明の接合金属膜形成方法は、ウェハの接合金属膜形
成面に接合金属箔を積層するとともにこの接合金属箔側
を接合金属に対して濡れ性の悪い材料から成る支持板上
にｅ置し、不活性又は還元性雰囲気中で加熱することを
特徴とする。In view of the above-mentioned conventional problems, the present invention provides a method of forming a bonding metal film on a wafer, and a chip obtained from the wafer, so that voids are not generated in the bonding metal part when bonding is performed, and the bonding metal film is not generated during heat bonding. The purpose of the present invention is to provide a bonding method that reduces the amount of gas consumed to maintain an inert or reducing atmosphere and prevents the bonding metal from oxidizing. Means for Solving the Problems The bonding metal film forming method of the present invention includes laminating a bonding metal foil on the bonding metal film forming surface of a wafer, and also laminating the bonding metal foil side with a material that has poor wettability with respect to the bonding metal. It is characterized by being placed on a support plate and heated in an inert or reducing atmosphere.
好適には、ウェハに接合金属箔を積層した後、接合金属
膜形成面と接合金属箔の間に介在した気体を鋭気するよ
うに押圧する．また、前記支持板として透明板を用い、
加熱して形成された接合金属膜の形成状態を検査するの
が好ましい．また、本発明のグイボンディング方法は、
前記接合金属膜を形成されたウェハをグイシングして得
られたチップを、加熱された被ボンディング体の接合面
上に載置してボンディングすることを特徴とする．
又、チップを載置する前に被ボンディング体の接合面上
に溶融接合金属を塗布してもよい．作 用
本発明の接合金属膜形成方法によると、ウェハと支持板
の間に接合金属箔を挟んで加熱することにより、接合金
属箔が支持板にて表面を規制された状態で溶融し、平滑
な表面性状の接合金属膜を容易に形成でき、かつその際
にバッチ方式の加熱炉を用いることができ、接合金属の
酸化を防止するための不活性又は還元性ガスの消費量も
少なくて済む．
また、ウェハの接合金属膜形成面と積層金属箔との間の
気体を脱気しておくことにより、接合金属膜にボイドが
発生するのを確実に防止でき、さらに透明の支持板を用
いて裏面から検査することにより、ボイドの有無を予め
知ることができる。Preferably, after laminating the bonding metal foil on the wafer, the gas interposed between the bonding metal film forming surface and the bonding metal foil is pressed sharply. Further, a transparent plate is used as the support plate,
It is preferable to inspect the formation state of the bonded metal film formed by heating. Furthermore, the Gui bonding method of the present invention includes:
The method is characterized in that a chip obtained by guising the wafer on which the bonding metal film is formed is placed on the bonding surface of a heated object to be bonded and bonded. Alternatively, a molten bonding metal may be applied to the bonding surface of the object to be bonded before placing the chip thereon. Effect: According to the bonding metal film forming method of the present invention, by sandwiching the bonding metal foil between the wafer and the support plate and heating it, the bonding metal foil melts with its surface regulated by the support plate, forming a smooth surface. It is possible to easily form a bonding metal film with the same properties, and a batch-type heating furnace can be used at that time, and the consumption of inert or reducing gas to prevent oxidation of the bonding metal is also small. In addition, by deaerating the gas between the bonding metal film forming surface of the wafer and the laminated metal foil, it is possible to reliably prevent the formation of voids in the bonding metal film. By inspecting from the back side, the presence or absence of voids can be known in advance.
又、本発明のグイボンディング方法によると、上記のよ
うに表面の平滑な接合金属膜を備えたチップを用い、加
熱された被ボンディング体の接合面に載置して接合する
ので、ボイドのない状態で接合することができるととも
に、不活性又は還元性ガスの消費量を少なくしながらそ
の酸化を防止できる．又、被ボンディング体の接合面に
予め溶融接合金属を塗布しておくと、互いの濡れ性が良
いため、より信頼性の高い接合が可能となる。Furthermore, according to the Gui bonding method of the present invention, a chip having a bonding metal film with a smooth surface as described above is used and is bonded by placing it on the bonding surface of the heated object to be bonded, so that there is no void. In addition to being able to join in the same state, it is also possible to prevent oxidation while reducing the consumption of inert or reducing gases. Moreover, if a molten bonding metal is applied in advance to the bonding surfaces of the objects to be bonded, the mutual wettability will be good, so that more reliable bonding will be possible.
実施例
以下、本発明の接合金属膜形成方法及びそれを利用した
グイボンディング方法の一実施例を第１図〜第４図に基
づいて説明する．
まず、接合金属膜としての半田膜を形成したチップを得
る方法を、第１図（ａ）〜（ｄ）を参照しながら説明す
る．
第１図において、１は縦横に多数のパワーＩＣ等を形成
したウェハであり、接合金属膜を形成すべき面には銀又
は金を蒸着した下地処理層２が形成されている。３は半
田箔、４は透明でかつ表面が高精度の平面度に仕上げら
れたガラス基板である．
まず、第ｉ図（ａ）に示すように、ガラス基板４上に半
田箔３及びウェハ１を積層する。このとき、第２図に示
すように、ウエハ１の下地処理層２の上に半田箔３を積
層した後、押圧ローラ５にて一端側から順次押圧して密
着させることによってそれらの間に介在する空気を脱気
しておくのが好ましい．
次に、この積層したものを、第１図０）に示すように、
酸化防止のためにバッチ式還元炉６内に挿入して１１１
８３５０℃に加熱し、半田箔３を加熱溶融し、ウェハ１
に一体化した半田膜７を形成するとともに、その表面を
ガラス基板４にて平面に形成する．還元炉６内にはＮ８
ガスとＨｔガスの混合ガスが充填されるが、バッチ式で
あるため、その消費量は少なくて済む。EXAMPLE Hereinafter, an example of a bonding metal film forming method of the present invention and a bonding method using the same will be explained based on FIGS. 1 to 4. First, a method for obtaining a chip on which a solder film is formed as a bonding metal film will be explained with reference to FIGS. 1(a) to 1(d). In FIG. 1, numeral 1 is a wafer on which a large number of power ICs and the like are formed vertically and horizontally, and a base treatment layer 2 in which silver or gold is vapor-deposited is formed on the surface on which a bonding metal film is to be formed. 3 is a solder foil, and 4 is a transparent glass substrate whose surface is finished to a highly accurate flatness. First, as shown in FIG. i(a), the solder foil 3 and the wafer 1 are laminated on the glass substrate 4. At this time, as shown in FIG. 2, after laminating the solder foil 3 on the base treatment layer 2 of the wafer 1, the solder foil 3 is sequentially pressed from one end side with a pressing roller 5 to make them adhere to each other, thereby interposing the solder foil 3 between them. It is preferable to evacuate the air. Next, as shown in Fig. 1 0), this laminated material is
Insert into batch type reduction furnace 6 to prevent oxidation 111
The solder foil 3 is heated to 8350°C, melted, and the wafer 1
A solder film 7 is formed integrally with the glass substrate 4, and its surface is formed flat on the glass substrate 4. There is N8 in the reduction furnace 6.
Although it is filled with a mixed gas of gas and Ht gas, the consumption amount is small because it is a batch type.
その後、還元炉６から取り出し、第１図（Ｃ）に示すよ
うに、ガラス基板４の裏面から形成された半田膜７の表
面性状を検査し、ボイドの有無を検査する．即ち、第３
図に詳細に示すように、ガラス基板４を通してこれに密
着している半田ＷＡ７の表面を検査することによりボイ
ド８を容易に検出することができ、又そのボイド８の位
置を記録してお く 。Thereafter, the glass substrate 4 is taken out from the reduction furnace 6, and the surface properties of the solder film 7 formed from the back surface of the glass substrate 4 are inspected for the presence or absence of voids, as shown in FIG. 1(C). That is, the third
As shown in detail in the figure, the void 8 can be easily detected by inspecting the surface of the solder WA 7 that is in close contact with the glass substrate 4, and the position of the void 8 can be recorded. .
次に、第１図（ｄ）に示すように、ウェハ１を各ＩＣ毎
にグイシングして各チ７ブ９に分離し、ガラス基板４か
ら取り出す。このとき、半田に対してガラス基板４は濡
れ性が悪いので、各チソブ９は簡単に取り出すことがで
きる。又、上記のようにボイド８の位置が記録されてい
るので、各チップ９にダイシングしたときの不良半田膜
を有するチップ９をー々検査しなくても特定することが
できる．
次に、このチップ９をヒートシンク１０にボンディング
する際には、第４図に示すように、底壁に適当ピッチで
ヒータ１２を内蔵したトンネル炉ｌ１内にヒートシンク
１０を挿入し、Ｎ８ガスとＨｚガスの混合ガス雰囲気中
で搬送しながら加熱し、このトンネル炉１１の土壁の所
定位置に形成した開口部ｌ３から加熱されたヒートシン
ク１０上にチップ９を装着し、加圧することによってボ
イドを生ずるこεなく接合することができる．尚、ヒー
トシンク１０は銅のブロックにて構處され、その上面に
は半田との濡れ性を良くするためにニッケルメフキｌ４
が形成きれている．上記実施例では、ヒートシンクｌＯ
側には半田層を形成していないが、第５図に示すように
、ヒートシンク１０上に溶融半田層を形成し、その上に
チップ９を装着するようにしてもよい．第５図において
、トンネル炉１１の上壁１１ａの所定位置に形成した開
口部１６の上方には、接合材としての溶融半田１５を滴
下するディスベンサ１７が配置されている．このディス
ペンサ１７は、内部に溶融半田１５を収容するとともに
、その上部空間にエアやＮ！ガス等の加圧気体１日を供
給することによって所定量の溶融半田１５を下方に位置
するヒートシンク１０の上面に滴下するように構戒され
ている．又、溶融半田ｌ５の収容部の外周にはヒータ１
９が設けられている．ディスベンサ１７から辷一トシン
ク１０の搬送方向後方の位置において、トンネル炉！１
の上壁１１ａ内面には、ステンレス調や超硬材等の溶融
半田１５に対して濡れ性の悪い板材から成るブレーナ２
０が、ヒートシンク１０の上面との間に適当な間隙が形
成されるように固定されている。Next, as shown in FIG. 1(d), the wafer 1 is separated into chips 9 by dicing each IC, and then taken out from the glass substrate 4. At this time, since the glass substrate 4 has poor wettability with respect to solder, each solder plate 9 can be easily taken out. Furthermore, since the positions of the voids 8 are recorded as described above, it is possible to identify chips 9 having defective solder films when each chip 9 is diced without inspecting each chip 9 individually. Next, when bonding this chip 9 to the heat sink 10, as shown in FIG. The chip 9 is heated while being transported in a mixed gas atmosphere, and the chip 9 is mounted on the heated heat sink 10 through an opening l3 formed at a predetermined position in the earthen wall of the tunnel furnace 11, and voids are created by applying pressure. It is possible to join without any trouble. The heat sink 10 is constructed of a copper block, and the top surface of the heat sink 10 is coated with nickel foil l4 to improve wettability with solder.
is completely formed. In the above embodiment, the heat sink lO
Although no solder layer is formed on the side, a molten solder layer may be formed on the heat sink 10 and the chip 9 may be mounted on it, as shown in FIG. In FIG. 5, a dispenser 17 is arranged above an opening 16 formed at a predetermined position on the upper wall 11a of the tunnel furnace 11 to drip molten solder 15 as a bonding material. This dispenser 17 accommodates the molten solder 15 inside, and has air or N! in its upper space. By supplying pressurized gas such as gas, a predetermined amount of molten solder 15 is dripped onto the upper surface of the heat sink 10 located below. Further, a heater 1 is installed on the outer periphery of the housing portion for the molten solder l5.
9 is provided. At a position rearward in the conveyance direction from the disvenser 17 to the dispensing sink 10, the tunnel furnace! 1
On the inner surface of the upper wall 11a, there is a brainer 2 made of a plate material that has poor wettability with respect to the molten solder 15, such as stainless steel or carbide material.
0 is fixed such that an appropriate gap is formed between the heat sink 10 and the upper surface of the heat sink 10.
又、このブレーナ２０からヒートシンク１０の搬送方向
後方の位置において、トンネル炉１１の上壁１１ａに形
成された開口部２１がら、チップ９を吸着したコレット
２２にてヒートシンク１０上にチップ９を装着するよう
に構威されている。Further, at a position rearward from the brainer 20 in the conveying direction of the heat sink 10, the chip 9 is mounted on the heat sink 10 through an opening 21 formed in the upper wall 11a of the tunnel furnace 11, using a collet 22 that has adsorbed the chip 9. It is structured like this.
以上の構威において、トンネル炉１１内に挿入したヒー
トシンク１０は、開口部ｌ６の下方位置でディスベンサ
１７にてその上面に所定量の溶融半田１５が滴下、塗布
され、次にブレーナ２ｏの下を通過する際に、塗布され
た溶融半田１５が均一な所定の厚さに平坦化され、その
後開口部２１の下方位置でチップ９がヒートシンク１０
上に装着される．この時、溶融半田１５が平坦化されて
いるので、チップ９の半田膜７との間に空隙が生じず、
ボイドなしに確実に接合される．尚、上記実施例では接
合材として半田を用いた例を示したが、本発明はその他
の接合材を用いる場合にも適用可能である。In the above configuration, a predetermined amount of molten solder 15 is dropped onto the upper surface of the heat sink 10 inserted into the tunnel furnace 11 by the dispenser 17 at a position below the opening l6, and then applied under the brainer 2o. During the passage, the applied molten solder 15 is flattened to a uniform predetermined thickness, and then the chip 9 is placed under the opening 21 on the heat sink 10.
It is mounted on top. At this time, since the molten solder 15 is flattened, no gap is created between it and the solder film 7 of the chip 9.
It is reliably joined without voids. Note that although the above-mentioned embodiment shows an example in which solder is used as the bonding material, the present invention is also applicable to cases in which other bonding materials are used.
発明の効果
本発明の金属膜形成方法によれば、ウェハと支持板の間
に接合金属箔を挟んで加熱することにより、接合金属箔
が支持板にて表面を規制されて溶融し、平滑な表面性状
の接合金属膜を容易に形成することができる。また、そ
の際にバッチ方式の加熱炉を用いることができ、接合金
属の酸化を防止するための不活性又は還元性ガスの消費
量も少なくて済むという効果を発揮する．
また、ウエハの接合金属膜形成面と積層金属箔との間の
気体を脱気すると、それらの間にボイドが発生するのを
より確実に防止でき、さらに透明の支持板を用いて裏面
から検査することにより、ボイドの有無を予め知ること
ができる．又、本発明のグイボンディング方法によると
、上記のように表面の平滑な接合金属膜を備えたチップ
を用い、加熱された被ボンディング体の接合面に載置し
て接合するので、ボイドのない状態で接合することがで
きるとともに、不活性又は還元性ガスの消費量を少なく
しながらその酸化を防止できる．又、被ボンディング体
の接合面に予め溶融接合金属を塗布しておくと、互いの
濡れ性が良いため、より信頼性の高い接合が可能となる
等、大なる効果を発揮する．Effects of the Invention According to the metal film forming method of the present invention, by sandwiching the bonding metal foil between the wafer and the support plate and heating it, the surface of the bonding metal foil is regulated by the support plate and melted, resulting in smooth surface texture. A bonding metal film can be easily formed. In addition, a batch-type heating furnace can be used at this time, which has the effect of requiring less consumption of inert or reducing gas to prevent oxidation of the joining metal. In addition, by deaerating the gas between the bonding metal film forming surface of the wafer and the laminated metal foil, it is possible to more reliably prevent the formation of voids between them.In addition, inspection can be performed from the back side using a transparent support plate. By doing this, it is possible to know in advance whether or not there are voids. Furthermore, according to the Gui bonding method of the present invention, a chip having a bonding metal film with a smooth surface as described above is used and is bonded by placing it on the bonding surface of the heated object to be bonded, so that there is no void. In addition to being able to join in the same state, it is also possible to prevent oxidation while reducing the consumption of inert or reducing gases. In addition, if the bonding surfaces of the objects to be bonded are coated with molten bonding metal in advance, they will have good mutual wettability, making it possible to achieve more reliable bonding, which is highly effective.
第１図（ａ）〜（ｄ）は本発明の接合金属膜の形成方法
の一実施例の工程説明図、第２図は同ウェハと接合金属
箔の押圧工程の説明図、第３図は同接合金属膜の検査工
程の詳細説明図、第４図は本発明のグイボンディング方
法の一実施例のボンディング工程を示す断面図、笹５図
は本発明のダイボンディング方法の他の実施例のボンデ
ィング工程を示す断面図、第６図は従来例のダイボンデ
ィング装置の断面図、第７図は同チ２プ装着時の問題点
を示す断面図である．
１・・・・・・ウェハ、３・・・・・・半田箔、４・・
・・・・ガラス基板、５・・・・・・押圧ローラ、６・
・・・・・バッチ式還元炉、７・・・・・・半田膜、８
・・・・・・ボイド、９・・・・・・チップ、１０・・
・・・・ヒートシンク、１１・・・・・・トンネル炉、
１５溶融半田．FIGS. 1(a) to (d) are process explanatory diagrams of an embodiment of the bonding metal film forming method of the present invention, FIG. 2 is an explanatory diagram of the pressing process of the same wafer and bonding metal foil, and FIG. 4 is a cross-sectional view showing the bonding process of one embodiment of the die bonding method of the present invention, and Figure 5 is a detailed explanatory diagram of the inspection process of the same bonding metal film. FIG. 6 is a cross-sectional view showing the bonding process, FIG. 6 is a cross-sectional view of a conventional die bonding apparatus, and FIG. 7 is a cross-sectional view showing problems when attaching the die bonding device. 1...Wafer, 3...Solder foil, 4...
...Glass substrate, 5...Press roller, 6.
... Batch type reduction furnace, 7 ... Solder film, 8
...Void, 9...Chip, 10...
...Heat sink, 11...Tunnel furnace,
15 Melted solder.
Claims (5)
るとともにこの接合金属箔側を接合金属に対して濡れ性
の悪い材料から成る支持板上に載置し、不活性又は還元
性雰囲気中で加熱することを特徴とする接合金属膜形成
方法。(1) A bonding metal foil is laminated on the bonding metal film forming surface of the wafer, and the bonding metal foil side is placed on a support plate made of a material with poor wettability to the bonding metal, and the bonding metal foil is placed in an inert or reducing atmosphere. A bonding metal film forming method characterized by heating inside.
成面と接合金属箔の間に介在した空気を脱気するように
押圧することを特徴とする請求項１記載の接合金属膜形
成方法。(2) After the bonding metal foil is laminated on the wafer, the bonding metal film formation according to claim 1, characterized in that pressing is performed to remove air interposed between the bonding metal film forming surface and the bonding metal foil. Method.
属膜の形成状態を検査することを特徴とする請求項１又
は２記載の接合金属膜形成方法。(3) The bonding metal film forming method according to claim 1 or 2, characterized in that the formation state of the bonding metal film formed by heating is inspected using a transparent support plate.
成されたウェハをダイシングして得られたチップを、加
熱された被ボンディング体の接合面上に載置してボンデ
ィングすることを特徴とするダイボンディング方法。(4) A chip obtained by dicing a wafer on which a bonding metal film has been formed by the method according to claim 1, 2 or 3 is placed on the bonding surface of a heated bonding object and bonded. A die bonding method characterized by:
上に溶融接合金属を塗布することを特徴とする請求項４
記載のダイボンディング方法。(5) Claim 4 characterized in that a molten bonding metal is applied on the bonding surface of the bonded object before placing the chip.
Die bonding method described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1187850A JP2616026B2 (en) | 1989-07-20 | 1989-07-20 | Bonding metal film forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1187850A JP2616026B2 (en) | 1989-07-20 | 1989-07-20 | Bonding metal film forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0352242A true JPH0352242A (en) | 1991-03-06 |
| JP2616026B2 JP2616026B2 (en) | 1997-06-04 |
Family
ID=16213311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1187850A Expired - Lifetime JP2616026B2 (en) | 1989-07-20 | 1989-07-20 | Bonding metal film forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2616026B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176890A (en) * | 1999-12-21 | 2001-06-29 | Rohm Co Ltd | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62147736A (en) * | 1985-12-20 | 1987-07-01 | Nec Corp | Method for mounting semiconductor element |
-
1989
- 1989-07-20 JP JP1187850A patent/JP2616026B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62147736A (en) * | 1985-12-20 | 1987-07-01 | Nec Corp | Method for mounting semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176890A (en) * | 1999-12-21 | 2001-06-29 | Rohm Co Ltd | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2616026B2 (en) | 1997-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI309062B (en) | ||
| US3724068A (en) | Semiconductor chip packaging apparatus and method | |
| JP4848153B2 (en) | Manufacturing method of semiconductor device | |
| US20070131353A1 (en) | Apparatus and clocked method for pressure-sintered bonding | |
| US6346433B1 (en) | Method of coating semiconductor wafer with resin and mold used therefor | |
| TW201232674A (en) | Method and apparatus of compression molding for reducing viods in molding compound | |
| JP4800524B2 (en) | Semiconductor device manufacturing method and manufacturing apparatus | |
| US20010008775A1 (en) | Resin sealing method and resin sealing apparatus | |
| JP2000216115A (en) | Method of processing semiconductor technological product | |
| US6803253B2 (en) | Method for laminating and mounting semiconductor chip | |
| JPH1027836A (en) | Manufacture of semiconductor device and semiconductor manufacturing device | |
| JP2009130218A (en) | Bonding device and bonding method | |
| JPH11163006A (en) | Method for bonding pellet | |
| JP3390409B2 (en) | Support frame attaching device | |
| JPH0352242A (en) | Junction-metal-film forming and diebonding methods | |
| JPH10335391A (en) | Heating of substrate | |
| JP2000138255A (en) | Method and system for manufacturing semiconductor device | |
| JP2002110736A (en) | Semiconductor device and its manufacturing method | |
| JP2005123609A (en) | Die bonder equipment and method for adhering semiconductor chip using same | |
| JP2002270628A (en) | Bonding method and apparatus | |
| JPS644339B2 (en) | ||
| JP2738070B2 (en) | Die bonding method | |
| US6372526B1 (en) | Method of manufacturing semiconductor components | |
| JPH065652A (en) | Wire bonding device | |
| JP3028031B2 (en) | Die bonding apparatus and die bonding method |