JPH05144989A - Production of lead frame and method for bonding semiconductor element using the frame - Google Patents
Production of lead frame and method for bonding semiconductor element using the frameInfo
- Publication number
- JPH05144989A JPH05144989A JP3333970A JP33397091A JPH05144989A JP H05144989 A JPH05144989 A JP H05144989A JP 3333970 A JP3333970 A JP 3333970A JP 33397091 A JP33397091 A JP 33397091A JP H05144989 A JPH05144989 A JP H05144989A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor element
- die pad
- lead frame
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造に使用
するリードフレームの製造方法と、このリードフレーム
のダイパッド上に半導体素子を接合する半導体素子の接
合方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a lead frame used for manufacturing a semiconductor device and a method of bonding a semiconductor element to a semiconductor element on a die pad of the lead frame.
【０００２】[0002]
【従来の技術】ダイオードや集積回路（ＩＣ）等の半導
体装置を製造する場合に用いられるリードフレームは、
銅等から成る薄板状の金属テープをプレス金型により打
ち抜き加工して、半導体素子を搭載するためのダイパッ
ドや外部回路と接続するためのリード等を形成して製造
している。このように製造されたリードフレームのダイ
パッド上に半導体素子を接合する方法として、金（Ａ
ｕ）とシリコン（Ｓｉ）との共晶接合法が多く用いられ
ている。この方法は、上面に金めっきを施したダイパッ
ドを４００℃〜４５０℃に加熱しておき、このダイパッ
ド上にシリコンからなる半導体素子を搭載する。これに
より、ダイパッド上面の金と半導体素子裏面のシリコン
との間で金とシリコンの共晶合金を形成して、半導体素
子をダイパッド上に接合するものである。そして、ダイ
パッド上に接合された半導体素子は金線等のボンディン
グワイヤーによりリードフレームのインナーリードと接
続され、モールド樹脂にて一体封止される。また、モー
ルド後、外部回路と接続するためのアウターリードには
ハンダめっきを施し、例えばプリント配線板に設けられ
た取り付けパッドと容易にハンダ付けされる。2. Description of the Related Art Lead frames used for manufacturing semiconductor devices such as diodes and integrated circuits (ICs) are
A thin metal tape made of copper or the like is punched by a press die to form a die pad for mounting a semiconductor element, leads for connecting to an external circuit, and the like. As a method for bonding a semiconductor element onto the die pad of the lead frame manufactured as described above, gold (A
The eutectic bonding method of u) and silicon (Si) is often used. In this method, a die pad having an upper surface plated with gold is heated to 400 ° C. to 450 ° C., and a semiconductor element made of silicon is mounted on the die pad. As a result, a eutectic alloy of gold and silicon is formed between the gold on the upper surface of the die pad and the silicon on the back surface of the semiconductor element, and the semiconductor element is bonded onto the die pad. Then, the semiconductor element bonded on the die pad is connected to the inner lead of the lead frame by a bonding wire such as a gold wire, and is integrally sealed with a molding resin. Also, after molding, the outer leads for connecting to an external circuit are plated with solder, and are easily soldered to, for example, a mounting pad provided on a printed wiring board.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うなリードフレームを用いて半導体素子を接合する場
合、以下に示す問題がある。すなわち、リードフレーム
のアウターリードにハンダめっきを施すための多くの工
程数とこの作業を行うためのハンダめっき装置が必要と
なる。これにともない、有害なめっき液を使用するた
め、各種の安全対策や公害対策を行う必要がある。ま
た、ダイパッド上に半導体素子を接合する共晶接合法を
用いることにより、ダイパッドを４００℃〜４５０℃に
加熱する必要があるとともに、不活性ガス雰囲気内でこ
の作業を行わなければならない。これにより、半導体装
置の製造コストの低減や、短納期を図ることが困難とな
る。よって、本発明は半導体装置を低コストで製造し、
かつ短納期で製造可能なリードフレームの製造方法とこ
れを用いた半導体素子の接合方法を提供することを目的
とする。However, when a semiconductor element is bonded using such a lead frame, there are the following problems. That is, a large number of steps for applying solder plating to the outer leads of the lead frame and a solder plating apparatus for performing this work are required. Along with this, since a harmful plating solution is used, it is necessary to take various safety measures and pollution measures. Further, it is necessary to heat the die pad to 400 ° C. to 450 ° C. by using the eutectic bonding method for bonding the semiconductor element on the die pad, and this work must be performed in an inert gas atmosphere. As a result, it becomes difficult to reduce the manufacturing cost of the semiconductor device and shorten the delivery time. Therefore, the present invention manufactures a semiconductor device at low cost,
Another object of the present invention is to provide a lead frame manufacturing method which can be manufactured in a short delivery time and a semiconductor element bonding method using the same.
【０００４】[0004]
【課題を解決するための手段】本発明のリードフレーム
の製造方法とそれを用いた半導体素子の接合方法は以上
の課題を解決するために成されたものである。すなわ
ち、金属テープ上面でかつその両側端から所定幅を残し
た状態に第１金属が圧延加工され、金属テープ上面でか
つ前記両所定幅に第２金属が圧延加工されて成るリード
フレーム母材を用いたリードフレームの製造方法におい
て、この金属テープ上面の第１金属を打ち抜いてダイパ
ッドとインナーリードとを形成し、第２金属を打ち抜い
てインナーリードと連結したアウターリードを形成する
リードフレームの製造方法である。また、半導体素子の
裏面に第１金属と等しい金属を薄膜状に被着して、ダイ
パッド上面の第１金属とこの半導体素子の裏面の金属と
を超音波を用いて接合する半導体素子の接合方法であ
る。The method of manufacturing a lead frame and the method of joining a semiconductor device using the same according to the present invention have been made to solve the above problems. That is, a lead frame base material is formed by rolling the first metal on the upper surface of the metal tape and leaving a predetermined width from both ends thereof, and rolling the second metal on the upper surface of the metal tape and to both the predetermined widths. In the method of manufacturing a lead frame used, a method of manufacturing a lead frame, in which a first metal on the upper surface of the metal tape is punched to form a die pad and an inner lead, and a second metal is punched to form an outer lead connected to the inner lead. Is. Further, a semiconductor element bonding method in which a metal equivalent to the first metal is deposited in a thin film shape on the back surface of the semiconductor element, and the first metal on the upper surface of the die pad and the metal on the back surface of the semiconductor element are bonded using ultrasonic waves. Is.
【０００５】[0005]
【作用】予め、金属テープ上面に圧延加工された第１金
属を打ち抜き加工することにより、上面にこの第１金属
が設けられたダイパッドおよびインナーリードが形成さ
れる。さらに、第２金属を打ち抜き加工することによ
り、上面にこの第２金属が設けられたアウターリードが
形成される。また、半導体素子の裏面にダイパッド上面
に設けられた第１金属と等しい金属を薄膜状に被着し、
この半導体素子をダイパッド上に搭載する。そして、こ
の半導体素子に超音波を加えることにより、ダイパッド
上面の第１金属と半導体素子裏面の金属が溶着して、半
導体素子とダイパッドとが接合される。The die pad and inner lead having the first metal provided on the upper surface are formed by punching the first metal rolled on the upper surface of the metal tape in advance. Further, by punching the second metal, an outer lead having the second metal provided on the upper surface is formed. Also, a metal equivalent to the first metal provided on the upper surface of the die pad is deposited on the back surface of the semiconductor element in a thin film form,
This semiconductor element is mounted on the die pad. Then, by applying ultrasonic waves to this semiconductor element, the first metal on the upper surface of the die pad and the metal on the rear surface of the semiconductor element are welded, and the semiconductor element and the die pad are joined.
【０００６】[0006]
【実施例】以下に本発明のリードフレームの製造方法と
それを用いた半導体素子の接合方法を図面に基づいて説
明する。図１（ａ）〜（ｂ）は、本発明のリードフレー
ムの製造方法を工程順に説明する斜視図、図１（ｃ）
は、リードフレームのダイパッド上に半導体素子を接合
した状態を説明する斜視図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame manufacturing method of the present invention and a semiconductor element joining method using the same will be described below with reference to the drawings. 1A and 1B are perspective views illustrating a method of manufacturing a lead frame of the present invention in the order of steps, and FIG.
FIG. 6 is a perspective view illustrating a state in which a semiconductor element is bonded onto a die pad of a lead frame.
【０００７】先ず、本発明のリードフレームの製造方法
を工程順に説明する。図１（ａ）に示すように、例えば
銅から成る幅３０ｍｍ程度、厚さ０．１ｍｍ程度の金属
テープ１上面の中央部分、すなわち後述するダイパッド
およびインナーリードが形成される部分に、例えば２０
μｍ厚のアルミニウムから成る第１金属２を搭載して圧
延加工する。また、この第１金属２の両側部、すなわち
後述するアウターリードが形成される部分に、例えば１
０μｍ厚のハンダ箔から成る第２金属３を搭載して圧延
加工する。これにより、金属テープ１の上面に第１金属
２と第２金属３がそれぞれ圧着された状態のリードフレ
ーム母材１０となる。なお、このリードフレーム母材１
０はフープ状態となっているが、図ではその一部のみを
示している。First, a method for manufacturing a lead frame of the present invention will be described in the order of steps. As shown in FIG. 1A, for example, a central portion of the upper surface of the metal tape 1 having a width of about 30 mm and a thickness of about 0.1 mm made of copper, that is, a portion where a die pad and inner leads to be described later are formed, for example, 20
A first metal 2 made of aluminum having a thickness of μm is mounted and rolled. Further, on both sides of the first metal 2, that is, on a portion where an outer lead described later is formed, for example,
A second metal 3 made of a solder foil having a thickness of 0 μm is mounted and rolled. As a result, the lead frame base material 10 is obtained in which the first metal 2 and the second metal 3 are pressed onto the upper surface of the metal tape 1. In addition, this lead frame base material 1
Although 0 is in the hoop state, only a part thereof is shown in the figure.
【０００８】次に、第１金属２と第２金属３が圧着され
た金属テープ１を所定のプレス金型により打ち抜き加工
する。すなわち、図１（ｂ）に示すように、金属テープ
１上面の第１金属２を打ち抜いて、ダイパッド１１およ
びインナーリード１２ａを形成する。そして、金属テー
プ１上面の第２金属３を打ち抜いて、アウターリード１
２ｂを形成する。これにより、ダイパッド１１とインナ
ーリード１２ａの上面にアルミニウムから成る第１金属
２が設けられ、また、アウターリード１２ｂの上面にハ
ンダ箔から成る第２金属３が設けられた状態のリードフ
レーム１０ａが製造される。Next, the metal tape 1 on which the first metal 2 and the second metal 3 are pressure bonded is punched by a predetermined press die. That is, as shown in FIG. 1B, the first metal 2 on the upper surface of the metal tape 1 is punched out to form the die pad 11 and the inner leads 12a. Then, the second metal 3 on the upper surface of the metal tape 1 is punched out, and the outer lead 1
2b is formed. As a result, the lead frame 10a in which the first metal 2 made of aluminum is provided on the upper surfaces of the die pad 11 and the inner leads 12a and the second metal 3 made of solder foil is provided on the upper surfaces of the outer leads 12b is manufactured. To be done.
【０００９】そして、図１（ｃ）に示すように、リード
フレーム１０ａのダイパッド１１上に半導体素子１３を
接合し、各インナーリード１２ａと半導体素子１３とを
ボンディングワイヤー１４にて接続する。Then, as shown in FIG. 1C, the semiconductor element 13 is bonded onto the die pad 11 of the lead frame 10a, and the inner leads 12a and the semiconductor element 13 are connected by the bonding wires 14.
【００１０】次に、図２に基づいて半導体素子１３とダ
イパッド１１との接合について説明する。すなわち、半
導体素子１３の裏面には、ダイパッド１１の上面に設け
られた第１電極２と等しい金属、例えばアルミニウムが
薄膜状に蒸着されている。この半導体素子１３とダイパ
ッド１１とを接合するには、半導体素子１３をダイパッ
ド１１の上面に設けられた第１金属２上に搭載し、この
半導体素子１３に超音波振動を加えることにより、半導
体素子１３裏面の金属（第１金属２と等しいアルミニウ
ム等）と第１金属２との接触部分が溶着する。これによ
り、常温で半導体素子１３をダイパッド１１上に接合す
ることができる。Next, the bonding between the semiconductor element 13 and the die pad 11 will be described with reference to FIG. That is, on the back surface of the semiconductor element 13, the same metal as the first electrode 2 provided on the upper surface of the die pad 11, for example, aluminum is vapor-deposited in a thin film shape. In order to bond the semiconductor element 13 and the die pad 11, the semiconductor element 13 is mounted on the first metal 2 provided on the upper surface of the die pad 11, and ultrasonic vibration is applied to the semiconductor element 13 to form the semiconductor element. 13 A contact portion between the metal (aluminum or the like equivalent to the first metal 2) on the back surface and the first metal 2 is welded. Thereby, the semiconductor element 13 can be bonded onto the die pad 11 at room temperature.
【００１１】また、半導体素子１３とインナーリード１
２ａとをボンディングワイヤー１４にて接続するには、
まず、半導体素子１３の上面に設けられた例えばアルミ
ニウムから成る電極パッド１５と、これと同様アルミニ
ウムから成るボンディングワイヤー１４とを超音波を用
いてボンディングする。そして、このボンディングワイ
ヤー１４をインナーリード１２ａの上面に設けられた第
１金属２に前記同様超音波を用いてボンディングする。
これにより、前記同様常温にてワイヤーボンディングを
行うことができる。Further, the semiconductor element 13 and the inner lead 1
To connect 2a with the bonding wire 14,
First, the electrode pad 15 made of, for example, aluminum provided on the upper surface of the semiconductor element 13 and the bonding wire 14 made of aluminum similarly to this are bonded by using ultrasonic waves. Then, the bonding wire 14 is bonded to the first metal 2 provided on the upper surface of the inner lead 12a by using ultrasonic waves as described above.
As a result, wire bonding can be performed at room temperature as described above.
【００１２】このようにダイパッド１１上に半導体素子
１３を接合し、この半導体素子１３とインナーリード１
２ａとをボンディングワイヤー１４にて接続した後、所
定形状のキャビティを有する金型を用いて、これらをモ
ールド樹脂１６にて一体封止する。（図２参照）これに
より、モールド樹脂１６の外形側面からアウターリード
１２ｂが導出されることになる。このアウターリード１
２ｂの上面には、前述のごとくハンダ箔から成る第２金
属３が設けられているので、プリント配線板等の外部回
路と接続する場合、容易にハンダ付け作業を行うことが
できる。In this way, the semiconductor element 13 is bonded onto the die pad 11, and the semiconductor element 13 and the inner lead 1 are joined together.
After connecting 2a with the bonding wire 14, these are integrally sealed with the mold resin 16 using a mold having a cavity of a predetermined shape. (See FIG. 2) As a result, the outer lead 12b is led out from the outer side surface of the mold resin 16. This outer lead 1
Since the second metal 3 made of solder foil is provided on the upper surface of 2b as described above, the soldering work can be easily performed when connecting to an external circuit such as a printed wiring board.
【００１３】次に、本発明の他の実施例を図３に基づい
て説明する。すなわち、図３（ａ）の斜視図に示すよう
に、金属テープ１の中央部分に略四角形の第１金属２を
圧延加工し、この第１金属２の周辺を囲む状態に第２金
属３を圧延加工する。そして、図３（ｂ）に示すよう
に、第１金属２を打ち抜いてダイパッド１１を形成し、
さらにこのダイパッド１１の周囲全体から複数のインナ
ーリード１２ａが配置された状態に形成する。また、第
２金属３を打ち抜いてアウターリード１２ｂを形成す
る。これにより、ダイパッド１１の上面と、この周囲全
体に配置されたインナーリード１２ａの上面とに第１金
属２が設けられ、さらにアウターリード１２ｂの上面に
第２金属３が設けられたリードフレーム１０ａが製造さ
れる。このように製造されたリードフレーム１０ａは、
高密度実装に対応したいわゆるＱＦＰ（Ｑｕａｄ Ｆｌ
ａｔ Ｐａｃｋａｇｅ）構造の半導体装置を製造する場
合に使用されるものであり、半導体素子１３の接合およ
びワイヤーボンディングは、前述と同様、超音波を用い
て行うことができる。Next, another embodiment of the present invention will be described with reference to FIG. That is, as shown in the perspective view of FIG. 3A, a substantially square first metal 2 is rolled in the central portion of the metal tape 1, and the second metal 3 is placed in a state of surrounding the periphery of the first metal 2. Roll it. Then, as shown in FIG. 3B, the die pad 11 is formed by punching out the first metal 2.
Further, a plurality of inner leads 12a is formed from the entire periphery of the die pad 11. Further, the second metal 3 is punched out to form the outer leads 12b. As a result, the first metal 2 is provided on the upper surface of the die pad 11 and the upper surfaces of the inner leads 12a arranged all around the die pad 11, and the lead frame 10a in which the second metal 3 is further provided on the upper surface of the outer lead 12b is formed. Manufactured. The lead frame 10a manufactured in this way is
So-called QFP (Quad Fl) compatible with high-density mounting
It is used when manufacturing a semiconductor device having an at package) structure, and the bonding and wire bonding of the semiconductor element 13 can be performed using ultrasonic waves, as in the above.
【００１４】なお、上記説明した金属テープ１は銅に限
定されず、通常のリードフレーム母材１０として使用さ
れる鉄−ニッケル４２合金でもよい。また、第１金属２
はアルミニウムの代わりに金を用いてもよい。さらに、
第２金属３はハンダ箔に限定されず、ハンダ付けの良好
な金属を用いれば良い。また、それぞれの実施例で説明
したリードフレーム１０ａは、金属テープ１の長辺方向
に沿って１列にダイパッド１１およびこれに対応したイ
ンナーリード１２ａとアウターリード１２ｂが形成され
ているが、これらのダイパッド１１およびインナーリー
ド１２ａとアウターリード１２ｂが２列以上並列に形成
されているものであっても良い。The metal tape 1 described above is not limited to copper, but may be an iron-nickel 42 alloy used as a normal lead frame base material 10. Also, the first metal 2
May use gold instead of aluminum. further,
The second metal 3 is not limited to the solder foil, and a metal having good soldering may be used. In the lead frame 10a described in each embodiment, the die pads 11 and the corresponding inner leads 12a and outer leads 12b are formed in one row along the long side direction of the metal tape 1. The die pad 11, the inner leads 12a, and the outer leads 12b may be formed in parallel in two or more rows.
【００１５】[0015]
【発明の効果】以上説明したリードフレームの製造方法
とそれを用いた半導体素子の接合方法によれば次のよう
な効果がある。すなわち、予めアウターリードにハンダ
箔が設けられているのでハンダめっき処理を施す必要が
ない。したがって、リードフレームを製造する工程数を
低減することができる。また、このめっき作業を行うた
めのハンダめっき装置や各種の安全対策および公害対策
を行う必要がない。さらに、半導体素子とダイパッドと
の接合を超音波を用いて行うため、ダイパッドを加熱す
ることなく常温で行える。したがって、半導体装置の製
造コストの低減や、短納期が可能となる。半導体装置の
製造に関して、低温処理で製造することができ、熱応力
等の品質信頼性で有利である。また、ボンディングがア
ルミニウムのワイヤーにアルミニウムの電極で、異種金
属（例えば金ワイヤー）を用いることがないので、極部
電池による電極の腐食にも有利となり、品質的に有利で
ある。The lead frame manufacturing method and the semiconductor element joining method using the same have the following effects. That is, since the outer lead is provided with the solder foil in advance, it is not necessary to perform the solder plating treatment. Therefore, the number of steps for manufacturing the lead frame can be reduced. Further, it is not necessary to take a solder plating device for carrying out this plating work and various safety measures and pollution measures. Further, since the semiconductor element and the die pad are bonded using ultrasonic waves, it can be performed at room temperature without heating the die pad. Therefore, the manufacturing cost of the semiconductor device can be reduced and the delivery time can be shortened. Regarding the manufacturing of a semiconductor device, it can be manufactured by low-temperature processing, and is advantageous in quality reliability such as thermal stress. Further, since the bonding is an aluminum wire to an aluminum wire and a dissimilar metal (for example, a gold wire) is not used, it is advantageous for corrosion of the electrode by the polar battery, which is advantageous in terms of quality.
【図１】本発明のリードフレームの製造方法を説明する
斜視図で、（ａ）は圧延加工した状態、（ｂ）は打ち抜
き加工した状態、（ｃ）はダイボンディングした状態で
ある。FIG. 1 is a perspective view illustrating a lead frame manufacturing method of the present invention, in which (a) is a rolled state, (b) is a punched state, and (c) is a die-bonded state.
【図２】半導体素子とダイパッドとを接合した状態を示
す断面図である。FIG. 2 is a cross-sectional view showing a state in which a semiconductor element and a die pad are bonded together.
【図３】本発明の他の実施例を説明する斜視図で、
（ａ）は圧延加工した状態、（ｂ）は打ち抜き加工した
状態である。FIG. 3 is a perspective view illustrating another embodiment of the present invention,
(A) is a rolled state, (b) is a punched state.
１ 金属テープ ２ 第１金属 ３ 第２金属 １０ リードフ
レーム母材 １０ａ リードフレーム １１ ダイパッ
ド １２ａ インナーリード １２ｂ アウタ
ーリード １３ 半導体素子 １４ ボンディ
ングワイヤー1 Metal Tape 2 First Metal 3 Second Metal 10 Lead Frame Base Material 10a Lead Frame 11 Die Pad 12a Inner Lead 12b Outer Lead 13 Semiconductor Element 14 Bonding Wire
Claims (2)
定幅を残した状態に第１金属が圧延加工され、前記金属
テープ上面でかつ前記両所定幅に第２金属が圧延加工さ
れて成るリードフレーム母材を用いたリードフレームの
製造方法において、 前記金属テープ上面の前記第１金属を打ち抜いてダイパ
ッドとインナーリードとを形成し、前記第２金属を打ち
抜いて前記インナーリードと連結したアウターリードを
形成することを特徴とするリードフレームの製造方法。1. A lead formed by rolling a first metal on a top surface of a metal tape and leaving a predetermined width from both ends thereof, and rolling a second metal on the top surface of the metal tape and both the predetermined widths. In a method of manufacturing a lead frame using a frame base material, an outer lead connected to the inner lead by punching out the first metal on the upper surface of the metal tape to form a die pad and an inner lead. A method of manufacturing a lead frame, which comprises:
等しい金属を半導体素子の裏面に薄膜状に被着して、前
記ダイパッド上面の前記第１金属と前記半導体素子の裏
面の前記金属とを超音波を用いて接合することを特徴と
する半導体素子の接合方法。2. A metal equivalent to the first metal provided on the upper surface of the die pad is deposited on the back surface of the semiconductor element in a thin film form to remove the first metal on the upper surface of the die pad and the metal on the back surface of the semiconductor element. A method for joining semiconductor elements, which comprises joining using ultrasonic waves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3333970A JPH05144989A (en) | 1991-11-21 | 1991-11-21 | Production of lead frame and method for bonding semiconductor element using the frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3333970A JPH05144989A (en) | 1991-11-21 | 1991-11-21 | Production of lead frame and method for bonding semiconductor element using the frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05144989A true JPH05144989A (en) | 1993-06-11 |
Family
ID=18272031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3333970A Pending JPH05144989A (en) | 1991-11-21 | 1991-11-21 | Production of lead frame and method for bonding semiconductor element using the frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05144989A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009016842A1 (en) * | 2009-04-08 | 2010-10-21 | Tyco Electronics Amp Gmbh | Cable grille for electronics housing and manufacturing process |
| US8927342B2 (en) | 2008-10-13 | 2015-01-06 | Tyco Electronics Amp Gmbh | Leadframe for electronic components |
-
1991
- 1991-11-21 JP JP3333970A patent/JPH05144989A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8927342B2 (en) | 2008-10-13 | 2015-01-06 | Tyco Electronics Amp Gmbh | Leadframe for electronic components |
| DE102009016842A1 (en) * | 2009-04-08 | 2010-10-21 | Tyco Electronics Amp Gmbh | Cable grille for electronics housing and manufacturing process |
| US8723032B2 (en) | 2009-04-08 | 2014-05-13 | Tyco Electronics Amp Gmbh | Conductor grid for electronic housings and manufacturing method |
| DE102009016842B4 (en) * | 2009-04-08 | 2015-01-22 | Tyco Electronics Amp Gmbh | Cable grille for electronics housing and manufacturing process |
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