JPH06209022A - Semiconductor jig and semiconductor device - Google Patents

Abstract

PURPOSE:To acquire a semiconductor jig and a package wherein a chip is prevented from warping when a semiconductor chip is die-bonded and inductance of a connection wire can be reduced. CONSTITUTION:An overhang part 1a is provided to an upper part 1 of a jig main body of a semiconductor jig, a semiconductor substrate 6 is fixed to a die pad part 3a of the semiconductor jig, a gold plating layer 4 which is exposed from a GaAs substrate 5 of the semiconductor substrate 6 is covered with the overhang part 1a, the overhang part 1a and the gold plating layer 5 of the semiconductor substrate 6 are bonded by resin bond 9 and the jig main body upper part 1 with the overhang part 1a is fixed to the jig main body 3, and an input/output line 2 of a semiconductor jig and an input/output line 12 of the semiconductor substrate 6 are connected by a wire 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor jig and a semiconductor device, and more particularly, when a semiconductor chip is mounted on the jig, the warp of the chip can be reduced and the inductance of a wire connecting the chip and the jig can be reduced. The present invention relates to a semiconductor jig and a semiconductor device capable of reducing the power consumption.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a conventional jig in which a semiconductor chip is die-bonded to a chip mounting area called a die pad portion of the jig. In the figure, reference numeral 3 denotes a semiconductor jig main body in which an insulating member such as ceramic is used for the main body, and a metal (not shown) is metallized on the surface, and the inner bottom surface thereof is a die pad portion 3a for die bonding. Has become. A semiconductor chip 6 having a gold plating layer 4 formed on the back surface of an ultrathin GaAs substrate 5 is fixed to the front surface of the die pad portion 3a via a eutectic alloy solder 11. Further, 15 is a warp amount of the semiconductor chip 6 at the time of die bonding.

FIG. 3 is a perspective view of the tip of a suction jig called a collet, which is used to support the semiconductor chip when the semiconductor chip is mounted on the mounting portion of the jig, and FIG. 5 is a semiconductor chip. FIG. 9 is a diagram showing a state in which the collet is pressed so as not to warp when it is mounted on a semiconductor jig. In these drawings, reference numeral 20 denotes a collet body, which has a structure having a suction head 20b at the tip of a support rod 20a. This suction head 20b has a structure in which the bottom surface is engraved, leaving the peripheral portion thereof,
This engraved portion serves as a suction portion 22 for sucking the semiconductor chip 6. The suction portion 22 is formed according to the shape of the chip to be sucked. Also, the suction unit 22
A vacuum hole 21 formed by penetrating the suction portion 20b and the support rod 20a is opened in the central portion of the.

FIG. 6 is a perspective view showing a semiconductor device in which a semiconductor chip is mounted on a semiconductor jig. In the figure,
Reference numeral 2 is an input / output line formed by a method such as vapor deposition or plating, and is formed of a conductive metal such as Au. Reference numerals 7 and 8 denote input / output portions of the semiconductor device, and 10 denotes input / output lines 2 formed in the input / output portions 7 and 8 and a GaAs substrate 5 of the semiconductor chip 6.
Which is a wire for connecting to the input / output line 12 formed in. Further, as shown in FIG. 6, the semiconductor chip 6 is made of GaAs.
It is composed of a substrate 5 and a plating layer 4 formed on the back surface of the GaAs substrate 5 and wider than the GaAs substrate 5.

Next, the operation will be described. Collet 20
When the semiconductor chip 6 is mounted on a carrier, a package, or the like, the semiconductor chip 6 is positioned in the suction portion 22, and in this state, the semiconductor chip 6 is vacuum-sucked through the vacuum hole 21 and the semiconductor chips 6 are conveyed one by one. However, as shown in FIG. 4, for example, ultra-thin GaAs with a thickness of about 30 μm is used.
Semiconductor chip 6 having a structure in which the gold plating layer 4 is formed on the substrate 5.
When die-bonding to the die pad portion 3a with the AuSu solder material 11 or the like, since the difference in thermal expansion coefficient between the GaAs substrate 5 and the gold plating layer 4 is normal, the amount of chip warp caused by heating the die pad portion 3a during die bonding. 15 will occur. Therefore, in the conventional example, as shown in FIG. 5, after the semiconductor chip 6 is transferred to the die pad portion 3a by using the collet 20, the GaAs substrate 5 is cooled while being pressed by the collet 20 to prevent the return. , The warp of the chip 6 was suppressed.

[0006]

Since the collet and the semiconductor jig of the conventional semiconductor device are configured as described above, when a plurality of semiconductor chips of the same kind are arranged and bonded to the jig or the package, the die pad is used. Since the whole is heated, there is a problem that the semiconductor chip soldered first warps at the time of die bonding of the subsequent chip, resulting in a die bonding failure.

Further, when the input / output line on the chip and the input / output line of the jig are connected by a wire, the length of the wire is increased by the exposed plating layer, and the effect of the inductance of the wire cannot be ignored. was there.

The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor jig capable of preventing the warp of the chip when the chip is mounted on the jig or the package. It is also intended to obtain a semiconductor device which can reduce the inductance of the connecting wire.

[0009]

A semiconductor jig according to the present invention is provided with an overhang portion on an upper portion of a main body of the semiconductor jig, and a plating layer exposed from a substrate of a semiconductor chip is provided by the overhang portion. The cover is used to fix the semiconductor chip to the semiconductor jig.

Also, the semiconductor device according to the present invention has a substrate having input / output lines formed on both sides of the upper surface, a plating layer is formed on the back surface, and both ends of the plating layer are exposed from the substrate. A semiconductor chip and an upper and lower jig main body having an input / output line formed on the upper surface and an overhang-shaped protrusion are provided, and a semiconductor jig for mounting the semiconductor chip is provided. Both ends of the exposed plating layer are covered with protrusions on the upper part of the jig body, and the protrusions and both ends of the plating layer are adhered to each other to connect the input / output line of the semiconductor jig and the input / output line of the semiconductor chip. The connection is made by a wire.

[0011]

According to the present invention, the overhang-shaped protruding portion is provided on the upper portion of the main body of the semiconductor jig, and the overhang portion and the plating layer of the semiconductor chip are adhered to each other by resin bonding or the like to attach the semiconductor chip to the semiconductor jig. Since it is fixed to the semiconductor chip, the warp of the chip during die bonding can be suppressed by the overhang portion, and the warp of the semiconductor chip can be prevented.

Further, according to the present invention, a semiconductor chip having a plating layer formed on the back surface and both ends of the plating layer exposed from the substrate is mounted on a semiconductor jig, and the overhanging portion on the upper part of the jig body and the substrate are mounted. Since both ends of the plating layer exposed from above are bonded with resin bonds, etc., the input / output line formed on the upper surface of the upper part of the jig body and the input / output line of the semiconductor chip are connected by wires. The length of the wire can be shortened and its inductance can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 is a perspective view showing an overhang portion of a semiconductor jig according to a first embodiment of the present invention.
FIG. 3 is a perspective view showing a semiconductor device in which a semiconductor substrate is mounted on a semiconductor jig. In these figures, the same reference numerals as those in FIG. 6 denote the same or corresponding parts, 1 is an upper part of the main body of the semiconductor jig, and 1a is an overhang portion formed on the upper part 1 of the jig main body. The input / output line 2 is formed on the upper surface thereof by a method such as vapor deposition and plating. The line 2 is made of a conductive metal such as Au. Reference numeral 9 is a resin bond for bonding the overhang portion 1a and the gold plating layer 4 exposed from the GaAs substrate 5 of the semiconductor substrate 6.

Next, the mounting method will be described. First,
The semiconductor substrate 6 is fixed to the die pad portion 3a of the jig body 3 using the eutectic alloy solder 11. Next, the exposed gold plating layer 4 of the semiconductor substrate 6 is covered with the overhang portions 1a of the jig body upper portion 1 from both sides of the semiconductor substrate 6 mounted on the jig body 3, and the overhang portion 1a and the semiconductor substrate 6 are covered.
The gold plating layer 4 is adhered to the jig body 3 by a resin bond 9, and the jig body upper portion 1 is fixed to the jig body 3 with an adhesive. Next, the input / output line 2 on the upper part 1 of the jig main body and the input / output line 12 on the GaAs substrate 5 are connected by the wire 10.

As described above, in this embodiment, the overhanging portion is provided on the upper portion of the main body of the semiconductor jig, and the overhanging portion and the gold plating layer of the semiconductor chip are bonded by resin bond or the like. Since it is fixed to the tool, the warp of the semiconductor chip due to the difference in thermal expansion coefficient between the GaAs substrate and the gold plating layer, which has been a problem in the past, is suppressed by the overhang part on the top of the main body, preventing the chip from warping during die bonding. be able to. Further, by covering the gold plating layer exposed from the GaAs substrate of the semiconductor chip with this overhang portion, the input / output line on the upper part of the main body of the semiconductor jig and the input / output line of the substrate of the semiconductor chip are in close proximity to each other. Since the line of the semiconductor jig and the line of the semiconductor chip are connected by the wire, the length of the connecting wire can be shortened and the inductance thereof can be reduced.

Example 2. 7 is a perspective view showing an overhang portion of a semiconductor jig according to a second embodiment of the present invention, and FIG. 8 is a perspective view showing a semiconductor device in which a semiconductor substrate is mounted on the semiconductor jig. In these figures, the same reference numerals as those in FIG. 6 indicate the same or corresponding portions, 1b is a trapezoidal convex portion formed in a stripe shape in the lower portion of the jig body upper portion 1, and 3b is an upper surface of the jig body 3. The trapezoidal convex portion 1b
It is a trapezoidal concave groove formed in a stripe shape for fitting with.

In the second embodiment, the concave groove portion 3 of the jig body 3 is used.
By fitting the trapezoidal convex portion 1b of the jig main body upper portion 1b to the jig main body upper portion 1, the jig main body upper portion 1 is fixed to the jig main body 3, and the semiconductor chip 6 is exposed by the overhang portion 1a of the jig main body upper portion 1. Since the layer 4 is covered,
Similarly, it is possible to prevent chip warpage during die bonding and reduce inductance.

[0018]

As described above, according to the semiconductor jig of the present invention, the overhang-shaped protrusion is provided on the upper portion of the main body of the semiconductor jig, and the overhang-shaped protrusion is exposed from the substrate of the semiconductor chip. Since both ends of the plated layer are adhered to each other by resin bonding or the like and the upper portion of the main body is fixed to the semiconductor jig, there is an effect that the projection can prevent warpage of the chip during die bonding.

Further, according to the semiconductor device of the present invention, the input / output line formed on the upper surface of the upper portion of the jig body having the overhang-shaped protrusion and the input / output line formed on the substrate of the semiconductor chip are provided. Since the line of the semiconductor jig and the line of the semiconductor chip which are close to each other and the line of the semiconductor chip are connected to each other by the wire, the length of the connecting wire can be shortened, and the inductance thereof can be reduced.

[Brief description of drawings]

FIG. 1 is a perspective view showing an overhang portion of a semiconductor jig according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a view showing a collet of a conventional semiconductor device.

FIG. 4 is a view showing a state in which a chip is mounted on a conventional semiconductor jig.

FIG. 5 is a side view showing a state in which warping is suppressed by a collet when a chip is mounted on a conventional semiconductor jig.

FIG. 6 is a perspective view showing a semiconductor device in which a chip is mounted on a conventional semiconductor jig.

FIG. 7 is a perspective view showing an overhang portion of a semiconductor jig according to a second embodiment of the present invention.

FIG. 8 is a perspective view showing a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

 1 jig upper part 1a overhang part 1b trapezoidal convex part 2 input / output line on jig 3 jig body 3a die pad part 3b trapezoidal concave groove part 4 gold plating layer 5 GaAs substrate 6 semiconductor substrate 7, 8 input / output Part 9 Resin bond 10 Wire 11 Eutectic alloy solder 12 Input / output line on semiconductor substrate 15 Semiconductor substrate warp amount 20 Collet body 20a Support rod 20b Suction head 21 Vacuum hole 22 Suction part

Claims (2)

[Claims] 1. A semiconductor comprising a substrate having input / output lines formed on both sides of its upper surface and a plating layer formed on the back surface of the substrate, and both ends of the plating layer being exposed from the substrate. A semiconductor jig for mounting a chip, wherein the semiconductor jig has a protrusion having an overhang shape that covers both ends of the exposed plating layer of the semiconductor chip mounted on the semiconductor jig. A semiconductor jig having an upper part of a tool body. 2. A semiconductor comprising a substrate having input / output lines formed on both sides of its upper surface and a plating layer formed on the back surface of the substrate, and both ends of the plating layer being exposed from the substrate. A semiconductor jig for mounting the semiconductor chip, which has a chip and an upper part of a jig body having overhang-shaped protrusions at both ends, and an input / output line is formed on the upper surface of the upper part of the jig body. And covering both ends of the exposed plating layer of the semiconductor chip with projections on the upper part of the jig body, and adhering the projections to both ends of the plating layer, and the input / output line of the semiconductor jig. A semiconductor device, characterized in that the input / output line of the semiconductor chip is connected by a wire.