JPH0424947A - Ceramic package for semiconductor - Google Patents
Ceramic package for semiconductorInfo
- Publication number
- JPH0424947A JPH0424947A JP12521290A JP12521290A JPH0424947A JP H0424947 A JPH0424947 A JP H0424947A JP 12521290 A JP12521290 A JP 12521290A JP 12521290 A JP12521290 A JP 12521290A JP H0424947 A JPH0424947 A JP H0424947A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- ceramic package
- board
- alloy
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 8
- 238000005219 brazing Methods 0.000 claims description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000011162 core material Substances 0.000 abstract description 4
- 229910018459 Al—Ge Inorganic materials 0.000 abstract description 3
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 229910018182 Al—Cu Inorganic materials 0.000 abstract description 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 1
- 229910018520 Al—Si Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 16
- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000000945 filler Substances 0.000 description 3
- 229910000833 kovar Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体用セラミックスパッケージ、詳しくは金
属製の半導体素子搭載部材とセラミックス枠体とを、ア
ルミニウム合金系ろう材を介して接合したセラミックス
パッケージの製造技術に間する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a ceramic package for semiconductors, more specifically, a ceramic package in which a metal semiconductor element mounting member and a ceramic frame are bonded via an aluminum alloy brazing material. manufacturing technology.
〈従来の技術〉
従来の半導体用セラミックスパッケージとしては、以下
のものが知られている。<Prior Art> The following are known as conventional ceramic packages for semiconductors.
例えば第３図に示すように、アルミナのパッケージ３１
にキャビティ３２を形成し、このキャビティ３２の底面
にシリコンチップ３３をダイボンディングしたものであ
る。更に、ワイヤボンディングによりチップ３３とリー
ドとを接続し、蓋材３４によって封止したものである。For example, as shown in FIG.
A cavity 32 is formed in the cavity 32, and a silicon chip 33 is die-bonded to the bottom surface of the cavity 32. Further, the chip 33 and the leads are connected by wire bonding and sealed with a cover material 34.
しかしながら、このアルミナセラミックスパッケージ３
１は放熱性に劣るため、高出力用のパワーＩＣチップの
搭載パッケージとしては使用することができないもので
あった。However, this alumina ceramic package 3
1 could not be used as a mounting package for high-output power IC chips because of its poor heat dissipation properties.
この放熱性を改良したセラミックスパッケージとして、
第４図に示すように、アルミナの枠体４１と、ＩＣチッ
プ４２の柊載基板４３と、を別々に形成したものがある
。搭載基板４３は金属、汐えばコバール合金、タングス
テン−銅合金、モ１゜ブデンー銅合金等によって形成さ
れ、ＩＣチップ４２からの放熱性を改良したものである
。ある（は、搭載基板４３を放熱性の優れた無酸素銅と
しＩＣチップと無酸素銅との熱膨張係数差を緩和するた
めにＩＣチップ４２搭載部にコバール合金、タングステ
ンあるいはモリブデンの薄板を接着した構造に形成され
たものもある。As a ceramic package with improved heat dissipation,
As shown in FIG. 4, there is one in which an alumina frame 41 and a substrate 43 on which an IC chip 42 is mounted are formed separately. The mounting board 43 is made of metal, such as Kovar alloy, tungsten-copper alloy, molybdenum-copper alloy, etc., and has improved heat dissipation from the IC chip 42. (In this case, the mounting board 43 is made of oxygen-free copper with excellent heat dissipation properties, and a thin plate of Kovar alloy, tungsten, or molybdenum is bonded to the mounting part of the IC chip 42 in order to alleviate the difference in thermal expansion coefficient between the IC chip and the oxygen-free copper.) Some are formed in a similar structure.
この場合、セラミックス（アルミナ）枠体４１の接合面
部分を接着性を高めるためメタライズ（例えば加湿窒素
中でＭｏ−Ｍｎコーティング）４４し、ニッケルメッキ
４５し、このＮｊメツキ層４５と金属基板４３とをＡｇ
−Ｃｕ合金系ろう材（８５／１５ｗｔ％）４６によりろ
う付けすることにより、これらを接合している。また、
これらをガラスにより接合したものも知られている。In this case, the bonding surface of the ceramic (alumina) frame 41 is metalized (e.g., Mo-Mn coating in humidified nitrogen) 44 and nickel plated 45 to improve adhesion, and the Nj plating layer 45 and the metal substrate 43 are bonded together. Ag
These are joined by brazing with a -Cu alloy brazing filler metal (85/15 wt%) 46. Also,
It is also known that these are bonded together using glass.
〈発明が解決しようとする課題〉
しかしながら、このような従来の半導体用セラミックス
パッケージにあっては、セラミックス枠体と金属基板と
の熱膨張係数の差が大きく、それらの接合部でセラミッ
クス枠体に割れ等の変形が生じ易い。また、メタライズ
そのものも面倒であった。更に、Ａ ｇ −Ｃｕ合金は
、その接合温度が８２０〜８５０℃と高いため、その熱
変形が顕著であった。また、ガラスによる接合は密着強
度が弱く、接合時にわれが生じるという課題があった。<Problem to be solved by the invention> However, in such conventional ceramic packages for semiconductors, there is a large difference in coefficient of thermal expansion between the ceramic frame and the metal substrate, and the ceramic frame is Deformation such as cracking is likely to occur. Moreover, metallization itself was troublesome. Furthermore, since the A g -Cu alloy has a high bonding temperature of 820 to 850°C, its thermal deformation was significant. Furthermore, bonding using glass has a problem in that adhesive strength is weak and cracks occur during bonding.
そこで、本発明は、放熱性に優れ、搭載部材に変形等か
生じず、しかも枠体との接合強度の高い半導体用セラミ
ックスパッケージを提供することを、その目的としてい
る。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a ceramic package for semiconductors that has excellent heat dissipation properties, does not cause deformation of the mounting member, and has high bonding strength with the frame.
く課題を解決するための手段〉
本発明は、半導体素子が搭載される素子搭載部材と、こ
の半導体素子を取り囲むようにしてこの素子搭載部材に
接合される枠体と、この半導体素子を封止する蓋体と、
を有する半導体用セラミックスパッケージにおいて、上
記素子搭載部材を金属板で、上記枠体をセラミックスに
よってそれぞれ形成するとともに、これらをアルミニウ
ム合金系のろう材を介して接合した半導体用セラミック
スパッケージである。Means for Solving the Problems> The present invention provides an element mounting member on which a semiconductor element is mounted, a frame that is joined to the element mounting member so as to surround the semiconductor element, and a frame body that seals the semiconductor element. A lid body that
In this ceramic package for semiconductors, the element mounting member is formed of a metal plate, the frame body is formed of ceramics, and these are bonded together via an aluminum alloy brazing material.
〈作用〉
本発明に係る半導体用セラミックスパッケージにあって
は、素子搭載部材として金属板を用いているため、放熱
性に優れている。そして、セラミックス枠体と素子搭載
部材との接合は、アルミニウム合金系のろう材を介して
行っているため、これらの接合強度は充分に高められて
いるとともに、熱応力によるひずみは緩和、吸収される
。<Function> The semiconductor ceramic package according to the present invention has excellent heat dissipation properties because a metal plate is used as the element mounting member. Furthermore, since the ceramic frame and the element mounting member are bonded via an aluminum alloy brazing filler metal, the bonding strength is sufficiently increased, and strain caused by thermal stress is alleviated and absorbed. Ru.
〈実施例〉 以下、本発明の実施例を図面を参照して説明する。<Example> Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例に係る半導体用セラミックス
パッケージを示す断面図である。FIG. 1 is a sectional view showing a ceramic package for semiconductors according to an embodiment of the present invention.
この図において、１１は半導体素子搭載部材である金属
製の基板（メタル基板）であって、このメタル基板１１
上には半導体素子（ＩＣチップ）１２がハンダ／ｊ１３
を介して搭載されている。メタル基板】】としてはＣｕ
−Ｍｏ合金、Ｃｕ−Ｗ合金、コバール合金等が使用され
る。いずれも放熱性を高めるものである。In this figure, 11 is a metal substrate (metal substrate) that is a semiconductor element mounting member, and this metal substrate 11
A semiconductor element (IC chip) 12 is soldered on top
It is loaded via. Metal substrate] is Cu
-Mo alloy, Cu-W alloy, Kovar alloy, etc. are used. Both improve heat dissipation.
このメタル基板１１の端縁部はアルミナ（Ａ１２０３）
製の枠体１４に接合されており、このアルミナ製の枠体
１４によって上記ＩＣチップ１２は取り囲まれている。The edge of this metal substrate 11 is made of alumina (A1203)
The IC chip 12 is joined to a frame body 14 made of alumina, and the IC chip 12 is surrounded by this frame body 14 made of alumina.
そして、このＩＣチップ１２と、枠体１４に設けられた
リードと、はボンディングワイヤ１５によって接続され
ている。This IC chip 12 and leads provided on the frame 14 are connected by bonding wires 15.
１６はこの枠体１４の上面に接着された蓋体であって、
ＩＣチップ１２をこのパッケージ中に封止している。こ
の蓋体１６は例えは金属板によって形成されている。16 is a lid bonded to the upper surface of this frame 14,
The IC chip 12 is sealed in this package. This lid body 16 is formed of a metal plate, for example.
ここで、上記基板１１と枠体１４との接合部は、アルミ
ニウムの芯材１７と、このアルミニウム芯材】７を上下
から挟むアルミニウム合金系のろう材１８Ａ、１８Ｂと
によって構成されている。このろう材１８Ａ、１８Ｂと
しては、例えばＡＩ−Ｓｉ、Ａｌ−Ｇｅ、ＡＩ −Ｃｕ
合金系のもの等が使用される。このように積層構造の芯
材としてアルミニウム１７を使用しているため、熱膨張
係数差による熱伸縮をこの軟らかいアルミニウム層１７
によって吸収、緩和することができる。Here, the joint between the substrate 11 and the frame 14 is constituted by an aluminum core material 17 and aluminum alloy brazing materials 18A and 18B that sandwich the aluminum core material 7 from above and below. Examples of the brazing materials 18A and 18B include AI-Si, Al-Ge, and AI-Cu.
Alloy-based materials are used. Since aluminum 17 is used as the core material of the laminated structure, the soft aluminum layer 17 is able to absorb thermal expansion and contraction due to the difference in thermal expansion coefficient.
It can be absorbed and relaxed by.
そして、このようなセラミックスパッケージにあって、
まず、アルミナの枠体１４にメタル基板１１が接合され
る。And, in such a ceramic package,
First, the metal substrate 11 is bonded to the alumina frame 14.
このとき、Ａｌ−５ｉ系のろう材１８Ａ、１８Ｂでは５
８０〜６２０℃の温度で接合され、Ａｔ−Ｇｅ系の場合
は４４０〜５００°Ｃてあり、Ａｌ−Ｃｕ系の場合は５
６０〜６００℃である。したがって、この接合時の熱ひ
ずみは低減されるためメタル基板１１に加わる熱ひずみ
も低減される。At this time, for Al-5i brazing materials 18A and 18B, 5
Bonding is performed at a temperature of 80 to 620°C, 440 to 500°C for At-Ge type, and 500°C for Al-Cu type.
The temperature is 60-600°C. Therefore, since the thermal strain during this bonding is reduced, the thermal strain applied to the metal substrate 11 is also reduced.
次いて、ＩＣチップ１２がメタル基板１１上にハンダ１
３等により搭載される。Next, the IC chip 12 is placed on the metal substrate 11 with solder 1.
It will be carried by 3rd class.
更に、ワイヤボンディング後、蓋体Ｉ６を接合すること
により、ＩＣチップ１２を封止したセラミックスパッケ
ージが形成される。Further, after wire bonding, a lid I6 is bonded to form a ceramic package in which the IC chip 12 is sealed.
第２図は本発明の他の実施例を示している。FIG. 2 shows another embodiment of the invention.
この実施例では、メタル基板２１として多層基板を使用
したものである。すなわち、例えばＣｕ−Ｗ合金の基板
２１の表面にはＴ １． Ａ １１ Ｚ ｒ等により
コーティングＮ２２が形成されている。In this embodiment, a multilayer substrate is used as the metal substrate 21. That is, for example, the surface of the substrate 21 made of Cu-W alloy has T 1. Coating N22 is formed of A 11 Z r or the like.
枠体２３としては例えばＡＩＮ（窒化アルミニウム）を
使用する。コーティング層２２はわれを防止するもので
ある。As the frame 23, for example, AIN (aluminum nitride) is used. The coating layer 22 prevents cracks.
接合部にはアルミニウム合金系のろう材２４を用いるも
のとする。例えばＡｌ−Ｓｉ合金、 Ａｌ−Ｇｅ合金
系のものを使用する。An aluminum alloy brazing filler metal 24 is used for the joint portion. For example, an Al-Si alloy or an Al-Ge alloy is used.
〈効果〉
以上説明してきたように、本発明に係る半導体用セラミ
ックスパッケージによれは、放熱性に優れ、接合強度が
高く、熱応力等によるひずみ、変形や割れが生しること
がない。<Effects> As described above, the semiconductor ceramic package according to the present invention has excellent heat dissipation, high bonding strength, and no distortion, deformation, or cracking due to thermal stress or the like.
第１図は本発明の一実施例に係る半導体用セラミックス
パッケージの概略構造を示す断面図、第２図は本発明の
他の実施例を示すセラミックスパッケージの一部を示す
断面図、第３図は従来の半導体用セラミックスパッケー
ジをを示す断面図、第４図は別の従来例としての半導体
用セラミックスパッケージを示す断面図である。
１１ ・ ・ ・ ・ ・ ・ ・ ・ ・１２ ・
・ ・ ・ ・ ・ ・ ・ ・１４ ・ ・ ・ ・
・ ・ ・ ・ ・１６ ・ ・ ・ ・ ・ ・
・ ・ ・１８Ａ、１８Ｂ ・ ・ ・ ・
・メタル基板、
・ＩＣチップ、
・アルミナ枠体、
・蓋体、
・ろう材。FIG. 1 is a cross-sectional view showing a schematic structure of a ceramic package for semiconductors according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a part of a ceramic package according to another embodiment of the present invention, and FIG. 4 is a sectional view showing a conventional ceramic package for semiconductors, and FIG. 4 is a sectional view showing another ceramic package for semiconductors as another conventional example. 11 ・ ・ ・ ・ ・ ・ ・ ・ ・12 ・
・ ・ ・ ・ ・ ・ ・ ・14 ・ ・ ・ ・
・ ・ ・ ・ ・16 ・ ・ ・ ・ ・ ・
・ ・ ・18A, 18B ・ ・ ・ ・ ・Metal substrate, ・IC chip, ・Alumina frame, ・Lid, ・Brazing metal.
Claims (1)
に接合される枠体と、 この半導体素子を封止する蓋体と、を有する半導体用セ
ラミックスパッケージにおいて、 上記素子搭載部材を金属板で、上記枠体をセラミックス
によってそれぞれ形成するとともに、これらをアルミニ
ウム合金系のろう材を介して接合したことを特徴とする
半導体用セラミックスパッケージ。[Scope of Claims] The device includes an element mounting member on which a semiconductor element is mounted, a frame body that is joined to the element mounting member so as to surround the semiconductor element, and a lid body that seals the semiconductor element. A ceramic package for semiconductors, characterized in that the element mounting member is formed of a metal plate, the frame body is formed of ceramics, and these are bonded together via an aluminum alloy brazing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12521290A JPH0424947A (en) | 1990-05-15 | 1990-05-15 | Ceramic package for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12521290A JPH0424947A (en) | 1990-05-15 | 1990-05-15 | Ceramic package for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0424947A true JPH0424947A (en) | 1992-01-28 |
Family
ID=14904652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12521290A Pending JPH0424947A (en) | 1990-05-15 | 1990-05-15 | Ceramic package for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0424947A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012238687A (en) * | 2011-05-11 | 2012-12-06 | Sony Corp | Semiconductor package, semiconductor device manufacturing method and solid state image pickup device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62199038A (en) * | 1986-02-27 | 1987-09-02 | Hitachi Ltd | Semiconductor package structure |
-
1990
- 1990-05-15 JP JP12521290A patent/JPH0424947A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62199038A (en) * | 1986-02-27 | 1987-09-02 | Hitachi Ltd | Semiconductor package structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012238687A (en) * | 2011-05-11 | 2012-12-06 | Sony Corp | Semiconductor package, semiconductor device manufacturing method and solid state image pickup device |
| US10483308B2 (en) | 2011-05-11 | 2019-11-19 | Sony Corporation | Reducing thickness of module in solid state imaging device |
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