JPS6420727U - - Google Patents
Info
- Publication number
- JPS6420727U JPS6420727U JP1987114866U JP11486687U JPS6420727U JP S6420727 U JPS6420727 U JP S6420727U JP 1987114866 U JP1987114866 U JP 1987114866U JP 11486687 U JP11486687 U JP 11486687U JP S6420727 U JPS6420727 U JP S6420727U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- ceramic package
- metal pedestal
- cavity
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
第１図は本考案のセラミツクパツケージを説明
する断面図、第２図は本考案の実施例に係るセラ
ミツクパツケージを説明する図、第３図は本考案
の別の実施例に係るメタル台座を説明する図、第
４図は従来例に係るセラミツクパツケージを説明
する図である。
（符号の説明）、１，８…セラミツク基体、２
…半導体チツプ、３…ボンデイングワイヤ、４…
Ａｕペースト又はＡｕメツキ、５…Ａｕ又はＡｕ
Ｓｉ、６…メタル台座、７，１５…空洞部、９…
メタライズ層（Ｗ）、１０，１２…Ｎｉメツキ、
１１…コバール材、１３…ロー材（Ａｇ，Ｃｕ）
、１４…Ａｕメツキ。
Fig. 1 is a sectional view illustrating a ceramic package according to the present invention, Fig. 2 is a sectional view illustrating a ceramic package according to an embodiment of the present invention, and Fig. 3 is a diagram illustrating a metal pedestal according to another embodiment of the present invention. FIG. 4 is a diagram illustrating a ceramic package according to a conventional example. (Explanation of symbols), 1, 8...Ceramic base, 2
...Semiconductor chip, 3...Bonding wire, 4...
Au paste or Au plating, 5...Au or Au
Si, 6...Metal pedestal, 7, 15...Cavity part, 9...
Metallized layer (W), 10, 12...Ni plating,
11...Kovar material, 13...Raw material (Ag, Cu)
, 14...Au metsuki.
Claims (1)
において、 半導体チツプを固着するための空洞部を備える
メタル台座を有するセラミツクパツケージ。[Scope of Claim for Utility Model Registration] A ceramic package for storing a semiconductor chip, which has a metal pedestal with a cavity for fixing the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114866U JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987114866U JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6420727U true JPS6420727U (en) | 1989-02-01 |
| JPH0621237Y2 JPH0621237Y2 (en) | 1994-06-01 |
Family
ID=31356000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987114866U Expired - Lifetime JPH0621237Y2 (en) | 1987-07-27 | 1987-07-27 | Ceramic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621237Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111050A (en) * | 1980-12-26 | 1982-07-10 | Fujitsu Ltd | Semiconductor device |
| JPS5833860A (en) * | 1981-08-10 | 1983-02-28 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Thermal bridge element |
| JPS6183041U (en) * | 1984-11-07 | 1986-06-02 |
-
1987
- 1987-07-27 JP JP1987114866U patent/JPH0621237Y2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57111050A (en) * | 1980-12-26 | 1982-07-10 | Fujitsu Ltd | Semiconductor device |
| JPS5833860A (en) * | 1981-08-10 | 1983-02-28 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Thermal bridge element |
| JPS6183041U (en) * | 1984-11-07 | 1986-06-02 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0621237Y2 (en) | 1994-06-01 |