JPH02283054A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH02283054A JPH02283054A JP1105027A JP10502789A JPH02283054A JP H02283054 A JPH02283054 A JP H02283054A JP 1105027 A JP1105027 A JP 1105027A JP 10502789 A JP10502789 A JP 10502789A JP H02283054 A JPH02283054 A JP H02283054A
- Authority
- JP
- Japan
- Prior art keywords
- sealing resin
- lead frame
- semiconductor device
- die pad
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 229920005989 resin Polymers 0.000 abstract description 20
- 239000011347 resin Substances 0.000 abstract description 20
- 238000007789 sealing Methods 0.000 abstract description 20
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000644 propagated effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 239000012141 concentrate Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置の組立工程で用いられるリードフ
レームの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a lead frame used in the assembly process of semiconductor devices.
［発明の概要］
本発明は、半導体装置の組立工程で用いられるリードフ
レームの半導体素子搭載部の辺を波形状あるいは曲線状
にすることにより、封止樹脂との熱膨張差により生ずる
応・力集中によるリードフレ。[Summary of the Invention] The present invention provides a method for reducing stress and stress caused by the difference in thermal expansion with the sealing resin by making the sides of the semiconductor element mounting portion of a lead frame used in the assembly process of semiconductor devices wave-shaped or curved. Lead fret due to concentration.
−ムと封止樹脂との界面に生ずる剥離、あるいは［従来
の技術］
半導体装置は、集積回路が形成された半導体素子のホン
ディングパッドとこれに対応したリードフレームの各リ
ードとを接続し、ついで各リードの先端部を残して射出
成型機等によりプラスチックで一体的に成型する。そし
て成型されたプラスチックパッケージの外側において各
リードを切断し、必要に応じてリードを適宜折り曲げて
半導体装置を製造している。第３図は、従来の半導体装
置の一例を示す斜視図である。図において、３は半導体
素子、４はリードフレーム２０半導体素子３搭載部であ
るグイパッド、５はリードフレーム２に設けた多数のリ
ード、６は半導体素子３のポンディングパッドとこれに
対応するリード５とを接続するワイヤ、７は半導体素子
３等を一体的に成型するエポキシ樹脂等の封止樹脂であ
る。- peeling that occurs at the interface between the film and the sealing resin, or [prior art] A semiconductor device connects the bonding pad of a semiconductor element on which an integrated circuit is formed and each lead of a corresponding lead frame. Next, each lead is integrally molded with plastic using an injection molding machine or the like, leaving only the tip end. Then, each lead is cut on the outside of the molded plastic package, and the leads are bent as necessary to manufacture a semiconductor device. FIG. 3 is a perspective view showing an example of a conventional semiconductor device. In the figure, 3 is a semiconductor element, 4 is a lead frame 20 and a lead pad which is a mounting part of the semiconductor element 3, 5 is a large number of leads provided on the lead frame 2, and 6 is a bonding pad of the semiconductor element 3 and the corresponding lead 5. A wire 7 connecting the two is a sealing resin such as epoxy resin that integrally molds the semiconductor element 3 and the like.
ところで、特に客先の仕様に応じて”ＪＭする分野の半
導体素子３は、高集積化、高機能化等の二−ズによる工
１０ビンの増大にともなって多ビン化するとともに大型
化する傾向にあり、ソー１５間隔の微細化、あるいは封
止樹脂７０蒲型化等、半導体装置１が小型化する傾向に
ある中で、半導体装置１の平面面積に対する半導体素子
６の平面面積の占める割合が大きくなってきている。By the way, semiconductor devices 3 in the field of JM, especially in accordance with customer specifications, tend to become larger and have more bins as the number of 10 bins increases due to needs such as higher integration and higher functionality. As the semiconductor device 1 tends to become smaller due to the miniaturization of the spacing between the saws 15 or the molding of the sealing resin 70, the ratio of the planar area of the semiconductor element 6 to the planar area of the semiconductor device 1 is increasing. It's getting bigger.
［発明が解決しようとする課題］
しかし、前述の従来技術では、封止樹脂７（主としてエ
ポキシ樹脂）は、半導体素子５（主としてＳｉ）及びリ
ードフレーム２（主として４２７０イ）と熱膨張係数が
大きく相違しており、また自然放置しておいても容易に
吸湿することから、半導体装置１には、封止樹脂７によ
り成型された後常温まで冷える過程で、第４図に矢印で
示すように中心方向に集中するような熱収縮応力が作用
し、特にダイパッド４周辺部に熱収縮応力が集中し、ダ
イパッド４と封止樹脂７界面における密着性が低下する
という課題を有する。また、半導体装置１を基板実装す
る際、封止樹脂７がりフロー等により２５０℃前後の高
温下にさらされる過程で、封止樹脂７から吸湿された水
分の気化膨張により、封止樹脂７の半導体素子３やダイ
パッド４の端面付近に内部応力が集中し、第５図に示す
ようなパッケージクラック８を起こすという課題を有す
る。これらの現象は、半導体装置１が大型になるほど、
あるいは半導体装置１千面面積に対するダイパッド４（
半導体素子３）平面面積の占める割合が大きくなどほど
顕著である。[Problems to be Solved by the Invention] However, in the prior art described above, the sealing resin 7 (mainly epoxy resin) has a coefficient of thermal expansion larger than that of the semiconductor element 5 (mainly Si) and the lead frame 2 (mainly 4270). Since the semiconductor device 1 is molded with the sealing resin 7 and cools down to room temperature, the semiconductor device 1 has moisture as shown by the arrow in FIG. There is a problem in that heat shrinkage stress concentrates toward the center, and particularly heat shrinkage stress concentrates around the die pad 4, reducing adhesion at the interface between the die pad 4 and the sealing resin 7. Furthermore, when the semiconductor device 1 is mounted on a board, the sealing resin 7 is exposed to high temperatures of around 250° C. due to the flow of the sealing resin 7, and the sealing resin 7 is expanded due to vaporization of moisture absorbed from the sealing resin 7. There is a problem in that internal stress concentrates near the end faces of the semiconductor element 3 and the die pad 4, causing package cracks 8 as shown in FIG. These phenomena occur as the semiconductor device 1 becomes larger.
Alternatively, the die pad 4 (
Semiconductor element 3) The larger the proportion of the planar area, the more noticeable the problem.
そこで本発明はこのような課題を解決しようとするもの
で、その目的とするところは、高品質で信頼性の優れた
半導体装置を得ることのできるリードフレームを提供す
るところＫある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a lead frame that allows a semiconductor device with high quality and excellent reliability to be obtained.
［課題を解決するための手段］
本発明のリードフレームは、半導体素子搭載部の辺を波
形状あるいは曲線状にすることを特徴とする。[Means for Solving the Problems] The lead frame of the present invention is characterized in that the sides of the semiconductor element mounting portion are wave-shaped or curved.
［実施例コ
本発明の詳細な説明するにあたり、第３図に示した従来
例と同一または相当部分には同じ符号を付し説明を省略
する。[Embodiment] In describing the present invention in detail, the same or corresponding parts as in the conventional example shown in FIG. 3 are given the same reference numerals, and their explanation will be omitted.
第１図（α）は本発明の実施例を示す平面図、＜ｈ＞は
そのエーエ断面図であり、ダイパッド４の各辺に数個の
半円状突起と半円状窪みを交互に並べ波形状にしたもの
である。従来の各辺直線状のダイパッド４の場合、封止
樹脂７成型時に発生する熱収縮応力あるいは基板実装時
に発生する熱膨張応力は、グイパッド４端面に一直線状
に集中するためパッケージクラック８等も容易に伝播す
るのに対し本実施例では、各辺が波形状になっているた
め、上記に示すような熱収縮応力あるいは熱膨張応力が
分散するためパッケージクラック等は容易に伝播せず、
リードフレーム２と封止樹脂７との界面に生ずる剥離を
低減し、またパッケージクランク８をおさえる。FIG. 1 (α) is a plan view showing an embodiment of the present invention, and <h> is a cross-sectional view thereof, in which several semicircular protrusions and semicircular depressions are arranged alternately on each side of the die pad 4. It has a wave shape. In the case of the conventional die pad 4, which has straight lines on each side, the thermal shrinkage stress generated during molding of the sealing resin 7 or the thermal expansion stress generated during board mounting is concentrated in a straight line on the end surface of the die pad 4, making it easy to cause package cracks 8. However, in this example, since each side is wave-shaped, the thermal shrinkage stress or thermal expansion stress as shown above is dispersed, so package cracks etc. do not propagate easily.
Peeling occurring at the interface between the lead frame 2 and the sealing resin 7 is reduced, and the package crank 8 is suppressed.
第２図は、本発明の他の実施例を示す平面図であり、ダ
イパッド４を円形状にしたものである。FIG. 2 is a plan view showing another embodiment of the present invention, in which the die pad 4 has a circular shape.
従来の各辺直線状のダイパッド４の場合、平面的に見て
方形状であるため各辺中央部から端部にかけて半導体装
置１の中心からの距離が一定でなくグイバッド４各辺場
所によってはたらく熱収縮応力あるいは熱膨張応力の大
きさが変りてくる。そのため応力の集中が生じやすい。In the case of the conventional die pad 4, which has linear shapes on each side, since it is rectangular in plan view, the distance from the center of the semiconductor device 1 from the center to the end of each side is not constant, and heat acts on each side of the die pad 4 depending on the location. The magnitude of shrinkage stress or thermal expansion stress changes. Therefore, stress concentration tends to occur.
これに対し本実施例は、ダイパッド４が円形状のため半
導体装置１の中心からの距離が一定であり、熱収縮応力
あるいは熱ゴ張応力が平均化し、リードフレーム２と封
止樹脂７との界面に生ずる剥流を低減し、またパッケー
ジクラック８をおさえる。On the other hand, in this embodiment, since the die pad 4 has a circular shape, the distance from the center of the semiconductor device 1 is constant, the heat shrinkage stress or the heat stiffening stress is averaged, and the relationship between the lead frame 2 and the sealing resin 7 is This reduces separation occurring at the interface and suppresses package cracks 8.
本発明は上記実施例の形状に限定するものではな（、要
は発生した熱収縮応力あるいは熱膨張応力を分散し、ダ
イパッド４と封止樹脂７との界面に生ずる剥離及びパッ
ケージクラック８０発生を低減する機能を有するもので
あればよい。なお第１図の実施例では、波形の形状、大
きさ及び機等適宜変更することができる。また、各辺間
じ形状、同じ寸法でな（てもよい。さらに第２図の実施
例では、径の寸法等適宜変更することができ、その形状
は楕円形や放物線の組み合わせでもよい。The present invention is not limited to the shape of the above embodiment (the point is to disperse the generated thermal contraction stress or thermal expansion stress and prevent peeling and package cracks 80 occurring at the interface between the die pad 4 and the sealing resin 7. Any material may be used as long as it has the function of reducing the Furthermore, in the embodiment shown in FIG. 2, the diameter and other dimensions can be changed as appropriate, and the shape may be a combination of an ellipse or a parabola.
［発明の効果コ
以上の説明から明らかなように、本発明は半導体素子搭
載部の辺を波形状あるいは曲線状にしたので、封止樹脂
成型時に発生する熱収縮応力や基板実装時に発生する熱
膨張応力を分散できる。このため、ダイパッドと封止樹
脂との界面に生じる剥離を低減し、パッケージクラック
の発生をおさえることができ、高品質で信頼性の高い半
導体装置を得ることができる。[Effects of the Invention] As is clear from the above description, in the present invention, the sides of the semiconductor element mounting portion are made wave-shaped or curved, so that the heat shrinkage stress generated during molding of the sealing resin and the heat generated during board mounting are reduced. Expansion stress can be dispersed. Therefore, it is possible to reduce peeling that occurs at the interface between the die pad and the sealing resin, suppress the occurrence of package cracks, and obtain a high-quality and highly reliable semiconductor device.
第１図（ｃＬ）は本発明の実施例を示す平面図、第１図
（ｂ）はそのニー１断面図。
第２図は本発明の他の実施例を示す平面図。
第３図は従来の半導体装置の一例を示す斜視図第４図及
び第５図はその状態図である。
１・・・・・・・・・半導体装置
２・・・・・・・・・リードフレーム
３・・・・・・・・・半導体素子
タ １ 口 （α）
メ １ 口 （ｂ）
！２ 図
・・・・・・・・・ダイパッド
・・・・・・・・・リード
、・・・・・・・・ワイヤ
・・・・・・・・・封止樹脂
・・・・・・・・・パッケージクラFIG. 1(cL) is a plan view showing an embodiment of the present invention, and FIG. 1(b) is a sectional view of knee 1 thereof. FIG. 2 is a plan view showing another embodiment of the invention. FIG. 3 is a perspective view showing an example of a conventional semiconductor device, and FIGS. 4 and 5 are state diagrams thereof. 1... Semiconductor device 2... Lead frame 3... Semiconductor element (α) Me (b)! 2 Diagram: Die pad, lead, wire, sealing resin, etc.・・・Package class
Claims (1)
ことを特徴とするリードフレーム。A lead frame characterized by having the sides of the semiconductor element mounting area wave-shaped or curved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1105027A JPH02283054A (en) | 1989-04-25 | 1989-04-25 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1105027A JPH02283054A (en) | 1989-04-25 | 1989-04-25 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02283054A true JPH02283054A (en) | 1990-11-20 |
Family
ID=14396554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1105027A Pending JPH02283054A (en) | 1989-04-25 | 1989-04-25 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02283054A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161954A (en) * | 1993-12-10 | 1995-06-23 | Nec Corp | Cavity case for solid-state image pick-up element |
| US5468993A (en) * | 1992-02-14 | 1995-11-21 | Rohm Co., Ltd. | Semiconductor device with polygonal shaped die pad |
| US5519576A (en) * | 1994-07-19 | 1996-05-21 | Analog Devices, Inc. | Thermally enhanced leadframe |
| US5898216A (en) * | 1995-11-14 | 1999-04-27 | Sgs-Thomson Microelectronics S.A. | Micromodule with protection barriers and a method for manufacturing the same |
-
1989
- 1989-04-25 JP JP1105027A patent/JPH02283054A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5468993A (en) * | 1992-02-14 | 1995-11-21 | Rohm Co., Ltd. | Semiconductor device with polygonal shaped die pad |
| KR100299800B1 (en) * | 1992-02-14 | 2001-10-22 | 사토 게니치로 | Semiconductor device |
| JPH07161954A (en) * | 1993-12-10 | 1995-06-23 | Nec Corp | Cavity case for solid-state image pick-up element |
| US5519576A (en) * | 1994-07-19 | 1996-05-21 | Analog Devices, Inc. | Thermally enhanced leadframe |
| US5898216A (en) * | 1995-11-14 | 1999-04-27 | Sgs-Thomson Microelectronics S.A. | Micromodule with protection barriers and a method for manufacturing the same |
| US6071758A (en) * | 1995-11-14 | 2000-06-06 | Sgs-Thomson Microelectronics S.A. | Process for manufacturing a chip card micromodule with protection barriers |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5332921A (en) | Resin-seal type semiconductor device | |
| US5488254A (en) | Plastic-molded-type semiconductor device | |
| KR930020649A (en) | Lead frame, semiconductor integrated circuit device using same, and manufacturing method thereof | |
| JP2000156433A (en) | Electronic device | |
| US8445998B1 (en) | Leadframe structures for semiconductor packages | |
| US11676931B2 (en) | Semiconductor package | |
| JP4390317B2 (en) | Resin-sealed semiconductor package | |
| JPH02283054A (en) | Lead frame | |
| JPS6215844A (en) | Semiconductor lead frame | |
| JPS59219942A (en) | Chip carrier | |
| JP2861725B2 (en) | Semiconductor device and its lead frame | |
| JPS6223097Y2 (en) | ||
| JPH04106941A (en) | Resin-sealed type semiconductor device | |
| JPH0547963A (en) | Package | |
| JPS60127747A (en) | Resin-sealed semiconductor device | |
| JPH01220465A (en) | Semiconductor device | |
| JPS635250Y2 (en) | ||
| JP2795245B2 (en) | Resin-sealed semiconductor device | |
| JPS63248155A (en) | Semiconductor device | |
| JPS629735Y2 (en) | ||
| JPH0870087A (en) | Lead frame | |
| JP2653951B2 (en) | Resin-sealed semiconductor device | |
| JPH03109755A (en) | Resin-sealed ic | |
| JPS63281451A (en) | Semiconductor device | |
| JPWO2018216412A1 (en) | Power module substrate and power module |