JPS60154652A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60154652A
JPS60154652A JP59010178A JP1017884A JPS60154652A JP S60154652 A JPS60154652 A JP S60154652A JP 59010178 A JP59010178 A JP 59010178A JP 1017884 A JP1017884 A JP 1017884A JP S60154652 A JPS60154652 A JP S60154652A
Authority
JP
Japan
Prior art keywords
pad
semiconductor device
bonding
pads
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59010178A
Other languages
Japanese (ja)
Inventor
Takayuki Okinaga
隆幸 沖永
Hiroshi Tate
宏 舘
Kanji Otsuka
寛治 大塚
Masayuki Shirai
優之 白井
Ken Okuya
謙 奥谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59010178A priority Critical patent/JPS60154652A/en
Publication of JPS60154652A publication Critical patent/JPS60154652A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the size of a pellet by disposing the outside end of a bonding pad of arbitrary row at the outer side from the inside end of the bonding pad of the outside row adjacent to the arbitrary row, thereby reducing the width of a bonding pad forming strip. CONSTITUTION:Zigzag pads formed in two rows along the end 8 of a pellet 3 are formed in hexagonal shape in which the corners of the sides which approach each other, thereby forming the outside end 5 of the inside pad 4a at the outer side from the inside end 5a of the bonding pad 4a. When the width of the end is reduced as above, zigzag pads arranged in the state that the distance between the pads of inside rows is narrower than the width of the pad can be intruded to the interior of the rows adjacent at the ends of the pads, and the width of the pad molding can be reduced in the state that the function as the bonding pad is maintained. Accordingly, even if the pellet of high integration is placed, the size can be reduced without disordering the normal function.

Description

【発明の詳細な説明】 し技術分野〕 本発明は、ベレットと外部端子との電気的接続をワイヤ
ボンディングにて行なう半導体装置の性能向上に適用し
て有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a technique that is effective when applied to improving the performance of a semiconductor device in which a bullet and an external terminal are electrically connected by wire bonding.

〔背景技術〕　“ ワイヤボンディングによりベレットと外部端子との電気
的接続を行なう半導体装置におい（は、ベレットの高集
積化に伴ないポンディングパッドをベレットの端部に沿
って一列に形ｂｙシただけでは対応できないため、２列
以上で形成することが必要になると考えられる。[Background technology] “In semiconductor devices that electrically connect a pellet and an external terminal by wire bonding, bonding pads are formed in a line along the edge of the pellet as the pellet becomes more highly integrated. Since this cannot be achieved with just one row, it is considered necessary to form two or more rows.

このようなベレットでは、隣接してボンディングされる
ワイヤどうしの接触を避けるために、千鳥状にポンディ
ングパッド（以下千鳥パッドと言う）を配列し℃形成す
ることか考えられる。In such a bullet, bonding pads (hereinafter referred to as staggered pads) may be arranged in a staggered manner to avoid contact between wires that are bonded adjacent to each other.

ところが、前記ポンディングパッドではその形状をほぼ
四角形で形成する場合、ポンディングパッド形成帯とし
て、少なくとも該ポンディングパッド巾の２倍より大き
な巾乞ベレットの回路形成部周囲に確保する必要がある
ため、ベレット端部きくしなければならなくなり、コス
ト上および半導体装置の小型化の観点からも問題である
ことが本発明者によって見い出された。However, when the above-mentioned bonding pad is formed into a substantially rectangular shape, it is necessary to secure a band for forming the bonding pad around the circuit forming portion of the belt with a width that is at least twice as large as the width of the bonding pad. The inventor of the present invention has found that the end of the pellet must be sharpened, which is a problem from the viewpoint of cost and miniaturization of the semiconductor device.

し発明の目的〕 本発明の目的は、高集積度のベレットの小型化に適用し
て有効な技術を提供することにある。OBJECTS OF THE INVENTION It is an object of the present invention to provide an effective technique that can be applied to downsizing highly integrated pellets.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明丁ねば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、ベレットの端部に沿っＣ２またはそれ以上の
列で形成されている所定の形状からなる千鳥パッドにお
いて、任意列のポンディングパッドの外側端部を、該列
に隣接する外側列のポンディングパッドの内側端部より
外側に位置せしめることにより、ボンディング機能ケ害
することなくホンティングパッド形成帯の巾を縮小する
ことができろことにより、ベレットの小型−化を達成す
るものである。That is, in a staggered pad having a predetermined shape formed in C2 or more rows along the edge of the pellet, the outer end of the pounding pad in any row is connected to the pad in the outer row adjacent to the staggered pad. By locating it outside the inner end of the pad, it is possible to reduce the width of the band forming the honting pad without impairing the bonding function, thereby achieving miniaturization of the bullet.

し実施例１〕 第１図は、本発明による実施例１である樹脂封止型半導
体装置を、そのほぼ中心部における断面図で示したもの
である。Embodiment 1] FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to Embodiment 1 of the present invention, taken approximately at the center thereof.

本実施例１０半導体装置は、／Ｉ２アロイまたはコバー
ル等の金属からなるリードフレームのタブ１にろう材２
ヶ介して取り付けられたシリコン等から１工ろベレット
３および該ベレット３のポンディングパッド４とリード
フレームの内部リード５とを電気的に接続しているワイ
ヤ６を、エポキシ樹脂等でモールドした後、外部リード
７を切断し、折曲げ成形してなるものである。This embodiment 10 semiconductor device has a brazing material 2 on a tab 1 of a lead frame made of metal such as /I2 alloy or Kovar.
After molding with epoxy resin or the like the wire 6 electrically connecting the bonding pad 4 of the bullet 3 and the internal lead 5 of the lead frame to the bullet 3 made of silicon or the like attached through the hole. , the external lead 7 is cut and bent.

第２図は、本実施例１０半導体装置の特徴であるベレッ
ト３の一部をワイヤ６を省略して示した拡大平面図であ
る。本図では、ベレット３の端部８に沿って２列に形成
きれている千鳥パッドを示してあり、該千鳥パッドは互
いに近接する側のコーナーを切除した六角形状で形成す
ることにより、内側パッド４ａの外側端部５を外側パッ
ド４ｂの内側端部５ａより外側の位置に形成し得たもの
である。FIG. 2 is an enlarged plan view showing a part of the bullet 3, which is a feature of the semiconductor device of the tenth embodiment, with the wire 6 omitted. In this figure, two rows of staggered pads are shown along the end 8 of the bellet 3, and the staggered pads are formed in a hexagonal shape with corners close to each other cut off, so that the inner pads The outer end 5 of the outer pad 4a can be formed at a position outside the inner end 5a of the outer pad 4b.

第２図に示すように、同列で隣接しているパッド間の距
離が該パッド巾より狭く配列形成された千鳥パッドの場
合は、パッド長さの２倍ン超える巾のポンディングパッ
ド形成帯が必要とされる、ただし、ペレット端部８に沿
っｆこ方向のパッド寸法をパッド巾、ペレット端部８に
垂直な方向のそれをパッド長とする。As shown in Fig. 2, in the case of staggered pads arranged in such a way that the distance between adjacent pads in the same row is narrower than the pad width, the bonding pad formation band has a width exceeding twice the pad length. The required pad dimension in the direction f along the pellet end 8 is the pad width, and that in the direction perpendicular to the pellet end 8 is the pad length.

一部、超音波ボンディングによるワイヤボンディングで
は、パッド上にワイヤの一部が押しつぶされた状態でボ
ンディングされるため、ボンディング領域としては所定
長さの中央部に一定の巾を有するものであれば、全体を
同じ巾で形成することは必要でない。In some wire bonding using ultrasonic bonding, a part of the wire is bonded onto the pad in a crushed state, so if the bonding area has a certain width at the center of a predetermined length, It is not necessary to form the whole with the same width.

そこで、四角形状のホンディングパッドの不要部である
コーナ部を除去し、末端中が縮小された形状にすること
により、内側列のパッド間の距離がパッド巾より狭い状
態で配列されている千鳥パッドであつ又も、第２図に示
すように互いにパッドの端部な隣接する列の内部まで食
い込ませることができることにより、ポンディングパッ
ドと１２での機能ヶ維持した状態で該パッド形成帯の巾
を縮小させることができるものである。Therefore, by removing the unnecessary corner parts of the rectangular honding pads and creating a shape with the middle of the end reduced, the pads in the inner row are arranged in a staggered manner with the distance between them narrower than the pad width. As shown in FIG. 2, even if the pad is a pad, it is possible to dig into the interior of adjacent rows at the ends of the pads, so that the pad forming band can be formed while maintaining the function of the padding pad 12. The width can be reduced.

従って、本実施例１０半導体装置では、高集積度のベレ
ットを搭載しても、通常の機能を害することなく小型化
を達成することができるものである。Therefore, in the semiconductor device of Example 10, even if a highly integrated pellet is mounted, it is possible to achieve miniaturization without impairing normal functions.

なお、本実施例１に示す千鳥パッドはアルミニウムの蒸
着等の通常の方法により容易に形成することができるも
のである。Note that the staggered pad shown in Example 1 can be easily formed by a conventional method such as aluminum vapor deposition.

し実施例２］ 第３図は、本発明による実施例２である半導体装置のベ
レットを示−ｒ概略部分平面図である。Embodiment 2] FIG. 3 is a schematic partial plan view showing a bellet of a semiconductor device according to Embodiment 2 of the present invention.

本実施例２０半導体装置は、前記実施例］と同様のもの
で、ベレット３のポンディングパッドのみが僅かに異な
るものである。The semiconductor device of this Embodiment 20 is similar to that of the previous embodiment, and only the bonding pad of the pellet 3 is slightly different.

すなわち、本実施例２における千鳥パッドは前記実施例
１に示した千鳥パッドを、ベレット端部（辺）８に対し
て所定の角度に傾斜させて形成したもので、パッドも六
角形の類似した形状からなるものである。That is, the staggered pad in Example 2 is formed by slanting the staggered pad shown in Example 1 at a predetermined angle with respect to the end (side) 8 of the pellet, and the pad also has a similar hexagonal shape. It consists of a shape.

本実施例２に示す千鳥パッドは、前記実施例１に示した
ものと同様の効果を有するものであるか、加えて、該パ
ッドから離れているリードと超音波ボンディングする場
合′Ｋ特に有効なものである。The staggered pad shown in Example 2 has the same effect as that shown in Example 1, and in addition, it is particularly effective when performing ultrasonic bonding with a lead that is distant from the pad. It is something.

〔実施例３〕 第４図は、本廃明による実施例３である半導体装置のペ
レットを示す概略部分平面図である。[Example 3] FIG. 4 is a schematic partial plan view showing a pellet of a semiconductor device according to Example 3 according to the present invention.

本実施例３０半導体装置は、第４図に示すようにペレッ
ト３の千鳥パッド７３列で形成したところに特徴がある
もので、他は全て前記実施例１０半導体装置と同一のも
のである。The semiconductor device of Example 30 is characterized in that it is formed of 73 rows of staggered pads of pellets 3, as shown in FIG. 4, and is otherwise the same as the semiconductor device of Example 10.

本実施例３における千鳥パッドの形状は、実施例１に示
したパッドの残っているコーナーＹ　も切除し、六角形
状にすることにより３列又はそれ以上の千鳥パッドであ
ってもポンディングパッド形成帯の巾を縮小可能にした
ものである。従って、ポンディングパッドが２列配列で
も足りない、高集積度のペレットに適用して有効なもの
である。The shape of the staggered pad in Example 3 is such that the remaining corner Y of the pad shown in Example 1 is also cut out and the shape is made into a hexagonal shape, so that even if there are three or more rows of staggered pads, a pounding pad can be formed. This allows the width of the obi to be reduced. Therefore, it is effective when applied to highly integrated pellets in which even two rows of bonding pads are insufficient.

し実施例４］ 第５図は、本発明による実施例４である半導体装置のベ
レツトの一部を示−ｆ概略平面図であ２）。Embodiment 4] FIG. 5 is a schematic plan view showing a portion of a semiconductor device according to Embodiment 4 of the present invention.

本実施例４０半導体装置は、第５図に示てようにペレッ
ト３の千鳥パッドが円形状で形成さｉｌてなるもので、
その他はほとんど前記実施例１０半導体装置と同一のも
のである。In the semiconductor device of Example 40, as shown in FIG. 5, the staggered pads of the pellet 3 are formed in a circular shape.
Most of the other features are the same as those of the semiconductor device of Example 10.

すなわち、前記実施例１より実施例４までは、超音波ボ
ンディングに適用して有効な千鳥パッド１であるに対し
、本実施例４に示すものはネイルヘッドボンディングに
適用して有効な形状のポンディングパッドからなる千鳥
パッドを有するものである。That is, the staggered pads 1 in Examples 1 to 4 are effective when applied to ultrasonic bonding, whereas the pad shown in Example 4 is a pump with a shape that is effective when applied to nail head bonding. It has staggered pads consisting of ding pads.

〔効果〕〔effect〕

（１）、ワイヤボンディングにて電気的接続してなる半
導体装置について、そのペレットに２列以上で形成され
ている千鳥パッドにおいて、任意列のポンディングパッ
ドの外側端部を該列に隣接する外側列のボンデインクパ
ッドの内側端部より外側に位置するように形成すること
により、ホンディングパッド形成帯の巾を縮めることが
できる。(1) Regarding a semiconductor device electrically connected by wire bonding, in the staggered pads formed in two or more rows on the pellet, the outer end of the bonding pad in any row is connected to the outside adjacent to the row. By forming the bonding pad forming band so as to be located outside the inner end of the bonding ink pad in the row, the width of the bonding pad forming band can be reduced.

（２）、ポンディングパッドを末端中が縮小された形状
で形成することにより、超音波ボンディング用のポンデ
ィングパッドとしての機能を維持したまま、前記（１１
の効果を得ることができる。(2) By forming the bonding pad with a reduced shape at the end, it is possible to maintain the function as a bonding pad for ultrasonic bonding while maintaining the function as a bonding pad for ultrasonic bonding.
effect can be obtained.

（３）、ポンディングパッドをほぼ円形状で形成するこ
とにより、ネイルヘッドボンディングに適したポンディ
ングパッドとしての機能を維持したまま、前記（１）の
効果を得ることができる。(3) By forming the bonding pad into a substantially circular shape, the effect of (1) above can be obtained while maintaining the function as a bonding pad suitable for nail head bonding.

（４）、前記（１）および（２）、または（１）および
（３）より、ワイヤボンディングの信頼性が高い、高集
積度の小型ペレットを形成することができるので、半導
体の小型化を行なうことができる。(4) According to (1) and (2) or (1) and (3) above, it is possible to form highly integrated small pellets with high wire bonding reliability, which contributes to the miniaturization of semiconductors. can be done.

（５）、前記（１）または（２）において、ボンデイン
クパッドを所定の角度で傾斜させて形成することにより
、離れているパッドとリードとをボンディングする場合
の千鳥パッドとすることができる。(5) In (1) or (2) above, by forming the bonding ink pads at a predetermined angle, it is possible to form a staggered pad when bonding pads and leads that are separated from each other.

以上本発明者によっ壬なされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもなしＳ。Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say, S.

たとえば、実施例では、六角形、六角形および円形のポ
ンディングパッドのものについて説明したが、それに限
るものでなく、本発明の目的に合致する形状からなるも
のであれば、如何なるものであってもよく、特に、ネイ
ルヘッドボンディング用のポンディングパッドとしては
、はぼ正六角形または正八角形等の形状であってもよい
ことは言うまでもない。For example, in the embodiments, hexagonal, hexagonal, and circular pounding pads have been described, but the present invention is not limited to these, and any shape may be used as long as it conforms to the purpose of the present invention. It goes without saying that the bonding pad for nail head bonding may have a substantially regular hexagonal shape, a regular octagonal shape, or the like.

〔利用分野〕[Application field]

以上の説明では王として本発明者によってな畜れた発明
をその背景となった利用分野である樹脂封止型半導体装
置に適用した場合について説明ｌ〜たが、それに限定さ
れるものでは１ｒ　＜、たとえば、セラミックパッケー
ジからなる半導体装置等の、ワイヤボンディングで電気
的接続を行ＩＩっている半導体装置であれば、如何なる
ものについても適用して有効な技術である。In the above explanation, we have explained the case in which the invention developed by the present inventor is applied to a resin-sealed semiconductor device, which is the background field of application, but the invention is not limited thereto. The present invention is an effective technique that can be applied to any semiconductor device in which electrical connections are made by wire bonding, such as a semiconductor device made of a ceramic package.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明による実施例１である樹脂封正型半導
体装置ヶ示す断面図、 第２図は、実施例】の半導体装置におけるべ１ノツトの
一部を示す概略平面図、 第３図は、本発明による実施例２である半導体装置にお
けるベレットの一部暑示す概略平面図、第４図は、本発
明による実施例３である半導体装置におけるベレットの
一部な示す概略平面図、第５図は、本発明による実施例
４である半導体装置におけるベレットの一部を示す概略
平面図である。 １・・・タブ、２・・・ろう、ｋ、３・・・ベレット、
４・・・ポンディングパッド、４ａ・・・内側パッド、
４ｂ・・・外側パッド、５・・・外側端部、５ａ・・・
内側端部、６・・・ワイヤ、７・・・外部リード、８・
・・端部。 第　１　図 第　２　図 ２、プ 第　３　図　７−３ 第　４　図 す 第　５　図1 is a sectional view showing a resin-encapsulated semiconductor device according to the first embodiment of the present invention; FIG. 2 is a schematic plan view showing a part of the bottom of the semiconductor device according to the embodiment; FIG. 4 is a schematic plan view showing a portion of a pellet in a semiconductor device according to a second embodiment of the present invention, and FIG. 4 is a schematic plan view showing a portion of a pellet in a semiconductor device according to a third embodiment of the present invention. FIG. 5 is a schematic plan view showing a part of a pellet in a semiconductor device according to a fourth embodiment of the present invention. 1...tab, 2...wax, k, 3...beret,
4...ponding pad, 4a...inner pad,
4b...Outside pad, 5...Outside end, 5a...
Inner end, 6... Wire, 7... External lead, 8...
··edge. Figure 1 Figure 2 Figure 2, Figure 3 Figure 7-3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】 １、　ポンディングパッドがベレット端部に沿ってほぼ
平行に２またはそれ以上の列で千鳥状に配列して形成さ
れてなる半導体装置において、任意列のポンディングパ
ッドの外側端部が、該列に隣接する外側列のボンディン
グバンドの内側端部より外側に位蓋して形成されでいる
ことを特徴とする半導体装置。 ２、ポンディングパッドが、末端の巾が縮小された形状
で形成され℃いることを特徴とする特許請求の範囲第１
項記載の半導体装置。 ３、　ポンディングパッドが、はぼ円形状で形成されて
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。 ４、ポンディングパッドが、その全部または一部を所定
の角度に傾斜させて形成されていることを特徴とする特
許請求の範囲第２項記載の半導体装ｆ、。[Claims] 1. In a semiconductor device in which bonding pads are arranged in a staggered manner in two or more rows substantially parallel to each other along the edge of a pellet, the outer side of a given row of bonding pads 1. A semiconductor device characterized in that an end portion is formed so as to extend outward from an inner end portion of a bonding band in an outer row adjacent to the row. 2. Claim 1, characterized in that the bonding pad is formed in a shape with a reduced width at the end.
1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1, wherein the bonding pad is formed in a substantially circular shape. 4. The semiconductor device f according to claim 2, wherein the bonding pad is formed so that all or part of it is inclined at a predetermined angle.
JP59010178A 1984-01-25 1984-01-25 Semiconductor device Pending JPS60154652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59010178A JPS60154652A (en) 1984-01-25 1984-01-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59010178A JPS60154652A (en) 1984-01-25 1984-01-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60154652A true JPS60154652A (en) 1985-08-14

Family

ID=11743027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59010178A Pending JPS60154652A (en) 1984-01-25 1984-01-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60154652A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107549A (en) * 1987-10-20 1989-04-25 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH04214987A (en) * 1990-12-13 1992-08-05 Daikin Ind Ltd Coupled compression equipment
US5300815A (en) * 1992-07-17 1994-04-05 Lsi Logic Corporation Technique of increasing bond pad density on a semiconductor die
US6590296B2 (en) * 2000-12-04 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device with staggered hexagonal electrodes and increased wiring width
EP3246940A1 (en) * 2016-05-19 2017-11-22 MediaTek Inc. Semiconductor package assembly

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107549A (en) * 1987-10-20 1989-04-25 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH04214987A (en) * 1990-12-13 1992-08-05 Daikin Ind Ltd Coupled compression equipment
US5300815A (en) * 1992-07-17 1994-04-05 Lsi Logic Corporation Technique of increasing bond pad density on a semiconductor die
US6590296B2 (en) * 2000-12-04 2003-07-08 Oki Electric Industry Co., Ltd. Semiconductor device with staggered hexagonal electrodes and increased wiring width
US6798077B2 (en) 2000-12-04 2004-09-28 Oki Electric Industry Co., Ltd. Semiconductor device with staggered octagonal electrodes and increased wiring width
EP3246940A1 (en) * 2016-05-19 2017-11-22 MediaTek Inc. Semiconductor package assembly
US10199318B2 (en) 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
US10468341B2 (en) 2016-05-19 2019-11-05 Mediatek Inc. Semiconductor package assembly

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