JP2015032826A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device.SOLUTION: A carrier 110 includes a carrier surface 111. The carrier surface 111 includes a protective layer installation region 111a. A first protective layer 120 is installed in the protective layer installation region 111a, and includes a first surface 121. The first surface 121 includes a first installation region 121a, a first anti-stress region 121b, and a first exposed region 121c. The first anti-stress region 121b is located in a corner of the first installation region 121a. A second protective layer 130 is installed in the first installation region 121a, and includes a second surface 131. The second surface 131 includes a second installation region 131a, a second anti-stress region 131b, and a second exposed region 131c. The second anti-stress region 131b is located in a corner of the second installation region 131c. A third protective layer 140 is installed in the second installation region 131a.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which stress is not concentrated in a corner.

  FIG. 7 shows a conventional semiconductor device 200 having a carrier 210, a first protective layer 220, a second protective layer 230, and a third protective layer 240. The carrier has a surface 211, the first protective layer 220 is disposed on the surface 211, and the first protective layer 220 has a first side wall 221 and a second side wall 222 connected to the first side wall 221. Have. The second protective layer 230 is disposed on the first protective layer 220, and the second protective layer 230 has a third side wall 231 and a fourth side wall 232 connected to the third side wall 231. The third protective layer 240 is disposed on the second protective layer 230, and the third protective layer 240 has a fifth side wall 241 and a sixth side wall 242 connected to the fifth side wall 241.

JP 2001-15738 A

  However, in the conventional semiconductor device described above, the sizes of the first protective layer 220, the second protective layer 230, and the third protective layer 240 are different, and the third sidewall 231 and the second protective layer 230 of the second protective layer 230 are different. The connection location of the four side walls 232 is a right angle, and the connection locations of the fifth side wall 241 and the sixth side wall 242 of the third protection layer 240 are also a right angle. Therefore, the first protection layer 220, the second protection layer When the layer 230 and the third protective layer 240 are overlaid on the surface 211 of the carrier 210, stress concentrates on the connection portion of the third side wall 231 and the fourth side wall 232 of the second protective layer 230. As a result, a rupture or rupture occurred at the connection point between the third side wall 231 and the fourth side wall 232, affecting the yield of the semiconductor device 200.

  Accordingly, the present inventor considered that the above-mentioned drawbacks can be improved and, as a result of intensive studies, has arrived at a proposal of a semiconductor device of the present invention that effectively improves the above-described problems by rational design.

  The present invention has been made in view of such conventional problems. In order to solve the above problems, it is a main object of the present invention to provide a semiconductor device. That is, by providing the anti-stress region on the surface of each protective layer, the stress is not concentrated on the corner of each protective layer, and the corner portion of the semiconductor device is prevented from being ruptured or torn.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention has a first corner and a second corner, and includes a carrier, a first protective layer, a second protective layer, and a third protection. With layers. The carrier has a carrier surface including a protective layer installation region and a protective layer exposure region located outside the protective layer installation region. The first protective layer is installed in the protective layer installation region, the first installation region, at least one first antistress region, and the first exposure located outside the first installation region and the first antistress region. A first surface having a region is provided, and the first anti-stress region is located at a corner of the first installation region. The second protective layer is installed in the first installation region, exposes the first anti-stress region and the first exposed region, the second installation region, at least one second anti-stress region, and the second installation region. And a second surface comprising a second exposed region located outside the second anti-stress region, wherein the second anti-stress region is located at a corner of the second installation region. The third protective layer is installed in the second installation area, and exposes the second anti-stress area and the second exposed area. The first anti-stress region and the second anti-stress region are located at the first corner, and the area of the first anti-stress region is greater than or equal to the area of the second anti-stress region.

  The first protective layer according to the present invention has the first anti-stress region, and the second protective layer has the second anti-stress region, whereby stress of the semiconductor device is applied to the first corner. The concentration of the semiconductor device is not concentrated, and a decrease in the yield of the semiconductor device caused by the rupture or tearing of the first corner of the semiconductor device is prevented.

1 is an exploded oblique view showing a semiconductor device according to a first embodiment of the present invention. 1 is a tilt view illustrating a semiconductor device according to a first embodiment of the present invention. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. 1 is a tilt view illustrating a semiconductor device according to a first embodiment of the present invention. It is an inclination figure which shows the semiconductor device by 2nd Embodiment of this invention. It is a top view which shows the semiconductor device by 2nd Embodiment of this invention. It is an inclination figure which shows the conventional semiconductor device.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments described below.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. The semiconductor device 100 has a first corner 100a and a second corner 100b, and the semiconductor device 100 includes a carrier 110, a first protective layer 120, a second protective layer 130, and a third protective layer 140. The carrier 110 has a carrier surface 111, and the carrier surface 111 has a protective layer installation region 111a and a protective layer exposure region 111b located outside the protective layer installation region 111a. The first protective layer 120 is installed in the protective layer installation region 111a, the first protective layer 120 has a first surface 121, the first surface 121 is a first installation region 121a, at least one first anti-stress region 121b, And a first exposed region 121c located outside the first installation region 121a and the first anti-stress region 121b. The first anti-stress region 121b is located at the corner of the first installation region 121a, the second protective layer 130 is installed in the first installation region 121a, and the second protective layer 130 has the first anti-stress region 121b and the first exposure. Region 121c is exposed. The second protective layer 130 has a second surface 131. The second surface 131 is a second installation region 131a, at least one second antistress region 131b, and outside the second installation region 131a and the second antistress region 131b. The second exposed region 131c is located at the corner of the second installation region 131a.

  The second protective layer 130 has a first side wall 132, a second side wall 133, and a first series of connecting walls 134 connected to the first side wall 132 and the second side wall 133 (see FIGS. 2 and 3). The first side wall 132 has a first bottom side 132a composed of a first end point P1, and the second side wall 133 has a second bottom side 133a composed of a second end point P2. The first extension line L1 formed extending from the first end point P1 of the first base 132a and the second extension line L2 formed extending from the second end P2 of the second base 133a intersect each other. The first reference point A1 is formed, and the region formed by connecting the first reference point A1, the first end point P1, and the second end point P2 is the first antistress region 121b. In this preferred embodiment, the first series of tangent walls 134 are planar.

  In addition, the 3rd protective layer 140 is installed in the 2nd installation area | region 131a, and the 2nd resistance stress area | region 131b and the 2nd exposure area | region 131c are exposed in the 3rd protection layer 140. The first anti-stress region 121b and the second anti-stress region 131b are located at the first corner 100a, and the area of the first anti-stress region 121b is not smaller than the area of the second anti-stress region 131b (FIGS. 1 to 3). reference). In this preferred embodiment, the third protective layer 140 has a third side wall 141, a fourth side wall 142, and a second connecting wall 143 connected to the third side wall 141 and the fourth side wall 142. The third side wall 141 has a third bottom side 141a composed of a third end point P3, and the fourth side wall 142 has a fourth bottom side 142a composed of a fourth end point P4. The third extension line L3 formed extending from the third end point P3 of the third base 141a and the fourth extension line L4 formed extending from the fourth end point P4 of the fourth base 142a intersect each other. A region formed by connecting the second reference point A2, the second reference point A2, the third end point P3, and the fourth end point P4 is the second anti-stress region 131b. The second connecting wall 143 is a plane and has a first distance D1 between the second reference point A2 and the third end point P3, and between the second reference point A2 and the fourth end point P4. There are two distances D2, and the first distance D1 is equal to the second distance D2.

  In this preferred embodiment, the first side wall 132 of the second protective layer 130 further has a first top side 132b consisting of a fifth end point P5, and the second side wall 133 has a second top side 133b consisting of a sixth end point P6. Have. There is a third distance D3 between the fifth end point P5 and the third end point P3, and the third distance D3 is the shortest distance from the first top side 132b to the third bottom side 141a. There is a fourth distance D4 between the sixth end point P6 and the fourth end point P4, and the fourth distance D4 is the shortest distance from the second top side 133b to the fourth bottom side 142a (see FIGS. 2 and 3). ).

  As shown in FIGS. 1 and 4, the first surface 121 of the first protective layer 120 further includes at least one third anti-stress region 121d, and the third anti-stress region 121d is a corner of the first installation region 121a. Located in. In the second protective layer 130, the third anti-stress region 121d is exposed, the second surface 131 of the second protective layer 130 has at least one fourth anti-stress region 131d, and the fourth anti-stress region 131d is the second installation. The fourth anti-stress region 131d is exposed at the corner of the region 131a and in the third protective layer 140. The third anti-stress region 121d and the fourth anti-stress region 131d are located at the second corner 100b, and the area of the third anti-stress region 121d is not smaller than the area of the fourth anti-stress region 131d. 3 and 4, the second protective layer 130 further includes a fifth side wall 135 and a third connecting wall 136 connected to the first side wall 132 and the fifth side wall 135. The first bottom side 132a of the first side wall 132 has a seventh end point P7, the fifth side wall 135 has a fifth bottom side 135a composed of the eighth end point P8, and the third connecting wall 136 is a plane. The fifth extended line L5 formed extending from the seventh end point P7 of the first base 132a and the sixth extended line L6 formed extending from the eighth end P8 of the fifth base 135a intersect each other. The region formed by connecting the third reference point A3 and the third reference point A3, the seventh end point P7, and the eighth end point P8 is a third anti-stress region 121d.

  3 and 4, the third protective layer 140 further includes a sixth side wall 144 and a fourth connecting wall 145 connected to the third side wall 141 and the sixth side wall 144. The third base 141a of the third side wall 141 has a ninth end point P9, the sixth side wall 144 has a sixth base side 144a consisting of a tenth end point P10, and the fourth connecting wall 145 is a plane. The seventh extension line L7 formed by extending from the ninth end point P9 of the third base 141a and the eighth extension line L8 formed by extending from the tenth end P10 of the sixth base 144a intersect each other. A region formed by connecting the fourth reference point A4, the fourth reference point A4, the ninth end point P9, and the tenth end point P10 is a fourth resistance stress region 131d.

  The first top side 132b of the first side wall 132 of the second protective layer 130 has a tenth end point P11, and the fifth side wall 135 has a third top side 135b made of the twelfth end point P12. There is a fifth distance D5 between the tenth end point P11 and the ninth end point P9, and the fifth distance D5 is the shortest distance from the first top side 132b to the third bottom side 141a. There is a sixth distance D6 between the twelfth end point P12 and the tenth end point P10, and the sixth distance D6 is the shortest distance from the third top side 135b to the sixth bottom side 144a. According to the present embodiment, the seventh distance D7 is between the third reference point A3 and the seventh end point P7, and the eighth distance D8 is between the third reference point A3 and the eighth end point P8. And the seventh distance D7 is equal to the eighth distance D8. Between the fourth reference point A4 and the ninth end point P9, there is a ninth distance D9, between the fourth reference point A4 and the tenth end point P10, there is a tenth distance D10, and a ninth distance D9. Is equal to the tenth distance D10.

  The first and second anti-stress regions 121b and 131b according to the present invention are located at the first corner 100a, and the third and fourth anti-stress regions 121d and 131d are located at the second corner 100b. This prevents stress from concentrating on the first corner portion 100a and the second corner portion 100b, and the second series of connecting walls 134 and the third connecting wall 136 of the second protective layer 130 and the second portion of the third protective layer 140. The connecting wall 143 and the fourth connecting wall 145 have an effect of preventing stress from concentrating on the corner. Therefore, the semiconductor device 100 prevents the yield of the semiconductor device 100 from deteriorating due to tearing or rupture at the first corner 100a or the second corner 100b.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. The difference from the first preferred embodiment is that the first connecting wall 134, the second connecting wall 143, the third connecting wall 136, and the fourth connecting wall 145 are arc surfaces, and the first connecting wall 134, the second connecting wall 145 143, the third connecting wall 136, and the fourth connecting wall 145 are arcuate surfaces, the stress of the semiconductor device 100 causes a connection portion (first corner portion) of the first side wall 132 and the second side wall 133 of the second protective layer 130. In other words, it is possible to prevent the semiconductor device 100 from concentrating on the first side wall 132 and the second side wall 133 of the semiconductor device 100 from being broken or ruptured.

  As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

100: Semiconductor device,
100a: first corner,
100b: second corner,
110: Carrier,
111: Carrier surface,
111a: protective layer installation area,
11b: protective layer exposed region,
120: first protective layer,
121: first surface,
121a: first installation area,
121b: first antistress region,
121c: first exposure region,
121d: third antistress region,
130: second protective layer,
131: second surface;
131a: second installation area,
131b: second antistress region,
131c: second exposed region,
131d: fourth antistress region,
132: first side wall,
132a: first base,
132b: first apex side,
133: the second side wall,
133a: second base,
133b: second top side,
134: first series of tangent walls,
135: the fifth side wall,
135a: the fifth base,
135b: the third top side,
136: Third connecting wall
140: third protective layer,
141: the third side wall,
141a: Third base,
142: the fourth side wall,
142a: the fourth base,
143: second connecting wall,
144: Sixth side wall,
144a: sixth base,
145: Fourth connecting wall,
A1: First reference point,
A2: Second reference point,
A3: Third reference point,
A4: Fourth reference point,
D1: First distance,
D2: second distance,
D3: Third distance
D4: Fourth distance,
D5: Fifth distance,
D6: Sixth distance,
D7: Seventh distance,
D8: Eighth distance,
D9: Ninth distance
D10: Tenth distance,
L1: First extension line,
L2: second extension line,
L3: Third extension line,
L4: Fourth extension line,
L5: Fifth extension line,
L6: Sixth extension line,
L7: Seventh extension line,
L8: Eighth extension line,
P1: first end point,
P2: second end point,
P3: Third endpoint
P4: Fourth endpoint,
P5: Fifth endpoint
P6: Sixth endpoint,
P7: 7th endpoint
P8: Eighth endpoint
P9: Ninth endpoint
P10: Tenth endpoint
P11: Tenth end point,
P12: the twelfth endpoint
200: Semiconductor device,
210: Carrier
211: surface,
220: first protective layer,
221: first side wall,
222: second side wall,
230: second protective layer,
231: the third side wall,
232: the fourth side wall,
240: third protective layer,
241: the fifth side wall,
242: Sixth side wall.

Claims (15)

A semiconductor device having a first corner and a second corner,
A carrier having a carrier surface comprising a protective layer installation region, and a protective layer exposure region located outside the protective layer installation region;
It is installed in the protective layer installation area, and comprises a first installation area, at least one first anti-stress area, and a first exposed area located outside the first installation area and the first anti-stress area. A first protective layer having a first surface, wherein the first anti-stress region is located at a corner of the first installation region;
Installed in the first installation region, exposing the first anti-stress region and the first exposed region, a second installation region, at least one second anti-stress region, and the second installation region and the A second protective layer having a second surface comprising a second exposed region located outside the second anti-stress region, wherein the second anti-stress region is located at a corner of the second installation region;
A third protective layer that is installed in the second installation region and exposes the second anti-stress region and the second exposed region;
The semiconductor device, wherein the first and second anti-stress regions are located at the first corner, and an area of the first anti-stress region is greater than or equal to an area of the second anti-stress region. . The second protective layer has a first side wall, a second side wall, and a first series of connecting walls that connect the first side wall and the second side wall,
The first side wall has a first base consisting of a first end point;
The second side wall has a second base comprising a second end point;
First, an intersection where a first extension line formed by extending from the first end point of the first base and a second extension line formed by extending from the second end point of the second base intersect is first. Defined as a reference point,
2. The semiconductor device according to claim 1, wherein a region formed by connecting the first reference point, the first end point, and the second end point is defined as the first antistress region. . The third protective layer has a third side wall, a fourth side wall, and a second connecting wall that connects the third side wall and the fourth side wall,
The third side wall has a third base consisting of a third end point;
The fourth side wall has a fourth base consisting of a fourth end point;
A second reference point is an intersection at which a third extension line formed by extending from the third end point of the third base and a fourth extension line formed by extending from the fourth end point of the fourth base intersect. Defined as a point,
2. The semiconductor device according to claim 1, wherein a region formed by connecting the second reference point, the third end point, and the fourth end point is defined as the second anti-stress region. A first distance between the second reference point and the third end point;
A second distance between the second reference point and the fourth end point;
The semiconductor device according to claim 3, wherein the first distance and the second distance are the same. The second protective layer has a first side wall, a second side wall, and a first series of connecting walls that connect the first side wall and the second side wall,
The first side wall has a first apex consisting of a fifth end point;
The second side wall has a second apex consisting of a sixth end point;
A third distance between the fifth end point and the third end point;
The third distance is the shortest distance from the first top side to the third base side,
A fourth distance between the sixth end point and the fourth end point;
4. The semiconductor device according to claim 3, wherein the fourth distance is a shortest distance from the second top side to the fourth bottom side.   The semiconductor device according to claim 2, wherein the first contact wall is a flat surface or an arc surface.   The semiconductor device according to claim 3, wherein the second connecting wall is a flat surface or an arc surface. The first surface of the first protective layer has at least one third anti-stress region located at a corner of the first installation region;
The second protective layer exposes the third anti-stress region;
The second surface of the second protective layer has at least one fourth anti-stress region located at a corner of the second installation region;
The third protective layer exposes the fourth anti-stress region;
The third anti-stress region and the fourth anti-stress region are located at the second corner;
The semiconductor device according to claim 1, wherein an area of the third resistance stress region is equal to or greater than an area of the fourth resistance stress region. The second protective layer has a first side wall, a fifth side wall, and a third connecting wall that connects the first side wall and the fifth side wall,
The first side wall has a first base composed of a seventh end point;
The fifth side wall has a fifth base consisting of an eighth end point;
A third reference point is an intersection where a fifth extension line formed extending from the seventh end point of the first base and a sixth extension line formed extending from the eighth end point of the fifth base intersect. Defined as a point,
9. The semiconductor device according to claim 8, wherein a region formed by connecting the third reference point, the seventh end point, and the eighth end point is defined as the third anti-stress region. The third protective layer has a third side wall, a sixth side wall, and a fourth connecting wall that connects the third side wall and the sixth side wall,
The third side wall has a third base consisting of a ninth end point;
The sixth side wall has a sixth base consisting of a tenth end point;
A fourth reference point is an intersection where a seventh extension line formed extending from the ninth end point of the third base and an eighth extension line formed extending from the tenth end point of the sixth base intersect. Defined as a point,
The semiconductor device according to claim 8, wherein a region formed by connecting the fourth reference point, the ninth end point, and the tenth end point is defined as the fourth resistance stress region. The second protective layer has a first side wall, a fifth side wall, and a third connecting wall that connects the first side wall and the fifth side wall,
The first side wall has a first apex consisting of a tenth end point;
The fifth side wall has a third apex consisting of a twelfth end point;
A fifth distance between the tenth end point and the ninth end point;
The fifth distance is the shortest distance from the first top side to the third base side,
A sixth distance between the twelfth end point and the tenth end point;
The semiconductor device according to claim 10, wherein the sixth distance is a shortest distance from the third top side to the sixth bottom side. A seventh distance between the third reference point and the seventh end point;
An eighth distance between the third reference point and the eighth end point;
The semiconductor device according to claim 9, wherein the seventh distance and the eighth distance are the same. A ninth distance between the fourth reference point and the ninth end point;
A tenth distance between the fourth reference point and the tenth end point;
The semiconductor device according to claim 10, wherein the ninth distance and the tenth distance are the same.   The semiconductor device according to claim 9, wherein the third connecting wall is a flat surface or an arc surface.   The semiconductor device according to claim 10, wherein the fourth connecting wall is a flat surface or an arc surface.

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