TW201507148A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure has a first corner anda second corner. The semiconductor structure comprises a carrier, a first passivation layer, a second passivationlayer and a third passivation layer. The carrier has a carrier surface having a passivation layer disposing zone. The first passivation layer is disposed on the passivation layer disposing zone. The first passivation layer has a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone. The second passivation layer having a second surface is disposed on the first disposing zone, and the second surface has a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the seconddisposing zone. The third passivation layer is disposed on the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner and a area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure that avoids stress concentration at the corners.

Referring to FIG. 7 , a conventional semiconductor structure 200 has a carrier 210 , a first protective layer 220 , a second protective layer 230 , and a third protective layer 240 . The carrier has a surface 211 . The first protective layer 220 is disposed on the surface 211, and the first protective layer 220 has a first sidewall 221 and a second sidewall 222 connected to the first sidewall 221. The second protective layer 230 is disposed on the first sidewall 221 The second protective layer 230 has a third sidewall 231 and a fourth sidewall 232 connected to the third sidewall 231. The third protective layer 240 is disposed on the second protective layer. The third protective layer 240 has a fifth sidewall 241 and a sixth sidewall 242 connected to the fifth sidewall 241, due to the first protective layer 220, the second protective layer 230, and the third The size of the protective layer 240 is different, and the third side wall 231 and the fourth side wall 232 of the second protective layer 230 are at right angles, the fifth side wall 241 of the third protective layer 240 and the sixth The junction of the side wall 242 is also a right angle. Therefore, when the first protection layer 220, the second protection layer 230 and the third protection layer 240 are layered on the carrier On the surface 211 of the body 210, the stress is easily concentrated on the junction of the third sidewall 231 and the fourth sidewall 232 of the second protective layer 230, such that the third sidewall 231 and the fourth sidewall 232 The joint is broken or broken, thereby affecting the yield of the semiconductor structure 200.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor structure in which the surface of each protective layer has a stress-resistant region so that stress does not concentrate on the corners of the respective protective layers, and the semiconductor structure can be prevented from being broken or broken by the corners.

A semiconductor structure of the present invention has a first corner and a second corner, the semiconductor structure comprising a carrier, a first protective layer, a second protective layer and a third protective layer, the carrier having a a surface of the carrier having a protective layer disposed region and a protective layer exposed region outside the protective layer disposed region, the first protective layer disposed in the protective layer disposed region, the first protective layer having a first surface The first surface has a first set region, at least one first stress resistant region, and a first exposed region located outside the first set region and the first stress resistant region, wherein the first stress resistant region is located at the first a second protection layer is disposed in the first installation area, and the second protection layer exposes the first anti-stress zone and the first exposure zone, the second protection layer has a second surface The second surface has a second set area, at least one second stress resistant area, and a second exposed area outside the second set area and the second stress resistant area, the second stress resistant area is located at the second The second corner of the setting area, the first a protective layer is disposed in the second set region, and the third protective layer exposes the second stress resistant region and the second exposed region, wherein the first stress resistant region and the second stress resistant region are located at the first corner And the area of the first stress resistant zone is not less than the area of the second stress resistant zone. Since the first protective layer of the present invention has the first stress resistant region, the second protective layer has the second stress resistant region, so that the stress of the semiconductor structure is not concentrated on the first corner, and the semiconductor can be avoided. The structure is broken or broken by the first corner, resulting in a decrease in the yield of the semiconductor structure.

Referring to FIGS. 1 and 2, which are a first preferred embodiment of the present invention, a semiconductor structure 100 has a first corner 100a and a second corner 100b. The semiconductor structure 100 includes a carrier 110 and a a first protective layer 120, a second protective layer 130, and a third protective layer 140. The carrier 110 has a carrier surface 111 having a protective layer disposed region 111a and a laterally disposed outside the protective layer disposed region 111a. The first protective layer 120 has a first surface 121 having a first disposed area 121a, at least one of the first protective layer 120. The first protective layer 120 has a first surface 121. a first anti-stress region 121b and a first exposed region 121c outside the first set-up region 121a and the first anti-stress region 121b, the first anti-stress region 121b is located at a corner 该 of the first set region 121a, The second protective layer 130 is disposed on the first disposed region 121a, and the second protective layer 130 exposes the first anti-stress region 121b and the first exposed region 121c. The second protective layer 130 has a second surface 131. The second surface 131 has a second setting area 131a, At least one second stress-resistant area 131b and a second exposed area 131c located outside the second set area 131a and the second stress-resistant area 131b, the second stress-resistant area 131b is located at a corner of the second set area 131a .

Referring to FIGS. 2 and 3 , the second protective layer 130 has a first sidewall 132 , a second sidewall 133 , and a first guiding wall connecting the first sidewall 132 and the second sidewall 133 . 134, the first side wall 132 has a first bottom edge 132a and the first bottom edge 132a has a first end point P1, the second side wall 133 has a second bottom edge 133a and the second bottom edge 133a Having a second end point P2, a first extension line L1 extending from the first end point P1 of the first bottom edge 132a and a second end point P2 extending from the second bottom side 133a The second extension line L2 intersects to form a first base point A1, and the area formed by the first base point A1, the first end point P1 and the second end point P2 is the first anti-stress area 121b. In an embodiment, the first conductive wall 134 is a flat surface.

Referring to FIGS. 1 , 2 and 3 , the third protection layer 140 is disposed in the second installation area 131 a , and the third protection layer 140 exposes the second anti-stress area 131 b and the second exposure area 131 c. The first stress-resistant region 121b and the second stress-resistant region 131b are located at the first corner 100a, and the area of the first stress-resistant region 121b is not less than the area of the second stress-resistant region 131b. In this embodiment, The third protective layer 140 has a third sidewall 141, a fourth sidewall 142, and a second guiding wall 143 connecting the third sidewall 141 and the fourth sidewall 142. The third sidewall 141 There is a third bottom edge 141a, and the third bottom edge 141a has a third end point P3, the fourth side wall 142 has a fourth bottom edge 142a and the fourth bottom edge 142a has a fourth end point P4. A third extension line L3 extending from the third end point P3 of the third bottom edge 141a intersects with a fourth extension line L4 formed by the fourth end point P4 of the fourth bottom edge 142a. a second base point A2, and a region formed by connecting the second base point A2, the third end point P3, and the fourth end point P4 is the second stress resistant area 131b, the second guide The wall 143 is a plane, and the second base point A2 and the third end point P3 have a first distance D1, and the second base point A2 and the fourth end point P4 have a second distance D2, the first distance D1 Equal to the second distance D2.

Referring to FIGS. 2 and 3 again, in the embodiment, the first sidewall 132 of the second protective layer 130 further has a first top edge 132b and the first top edge 132b has a fifth end point P5. The second side wall 133 has a second top edge 133b and the second top edge 133b has a sixth end point P6. The fifth end point P5 has a third distance D3 between the third end point P5 and the third end point P3. The third distance D3 is the shortest distance from the first top edge 132b to the third bottom edge 141a, and the fourth end point P6 to the fourth end point P4 has a fourth distance D4, the fourth distance D4 is the shortest distance from the second top edge 133b to the fourth bottom edge 142a.

Referring to FIGS. 1 and 4, the first surface 121 of the first protective layer 120 further has at least one third stress-resistant region 121d, and the third stress-resistant region 121d is located at a corner of the first disposed region 121a. The second protective layer 130 exposes the third anti-stress region 121d. The second surface 131 of the second protective layer 130 has at least one fourth anti-stress region 131d. The fourth anti-stress region 131d is located in the second set region. a corner of the 131a, and the third protective layer 140 exposes the fourth stress-resistant region 131d, the third stress-resistant region 121d and the fourth stress-resistant region 131d are located at the second corner 100b, and the third stress-resistant layer The area of the region 121d is not less than the area of the fourth stress-resistant region 131d. Referring to FIGS. 3 and 4, the second protective layer 130 further has a fifth sidewall 135 and a connecting the first sidewall 132 and the first The third guiding wall 136 of the five side wall 135, the first bottom edge 132a of the first side wall 132 has a seventh end point P7, the fifth side wall 135 has a fifth bottom edge 135a and the fifth The bottom edge 135a has an eighth end point P8. The third conductive wall 136 is a flat surface, and the seventh end point P7 of the first bottom edge 132a extends. The extension line L5 intersects with a sixth extension line L6 formed by the eighth end point P8 of the fifth bottom edge 135a to form a third base point A3, and connects the third base point A3, the seventh end point P7 and The region formed by the eighth end point P8 is the third stress resistant region 121d.

Referring to FIGS. 3 and 4 , the third protective layer 140 further has a sixth side wall 144 and a fourth guiding wall 145 connecting the third side wall 141 and the sixth side wall 144 . The third bottom edge 141a of the side wall 141 has a ninth end point P9, the sixth side wall 144 has a sixth bottom edge 144a and the sixth bottom edge 144a has a tenth end point P10, the fourth guide The wall 145 is a flat surface, a seventh extension line L7 extending from the ninth end point P9 of the third bottom side 141a and an eighth extension formed by the tenth end point P10 of the sixth bottom side 144a. The extension line L8 intersects to form a fourth base point A4, and the region formed by the fourth base point A4, the ninth end point P9 and the tenth end point P10 is the fourth stress-resistant area 131d.

Referring to FIGS. 3 and 4, the first top edge 132b of the first sidewall 132 of the second protective layer 130 has an eleventh end point P11, and the fifth sidewall 135 has a third top edge. 135b and the third top edge 135b has a twelfth end point P12, the eleventh end point P11 to the ninth end point P9 has a fifth distance D5, the fifth distance D5 is the first top a shortest distance from the edge 132b to the third bottom edge 141a, a sixth distance D6 between the twelfth end point P12 and the tenth end point P10, the sixth distance D6 being the third top edge 135b to the The shortest distance of the sixth bottom edge 144a. In addition, in the embodiment, the third base point A3 and the seventh end point P7 have a seventh distance D7, and the third base point A3 and the eighth end point P8 have An eighth distance D8, the seventh distance D7 is equal to the eighth distance D8, and the fourth base point A4 and the ninth end point P9 have a ninth distance D9, the fourth base point A4 and the tenth end point P10 There is a tenth distance D10 equal to the tenth distance D10.

Since the first stress-resistant region 121b and the second stress-resistant region 131b of the present invention are located at the first corner 隅100a, the third stress-resistant region 121d and the fourth stress-resistant region 131d are located at the second corner 隅100b, Therefore, the stress is concentrated on the first corner 100a and the second corner 100b, and the first conductive wall 134 and the third conductive wall 136 of the second protective layer 130 and the third protective layer 140 The second conductive wall 143 and the fourth conductive wall 145 also have the effect of preventing stress from being concentrated on the corners, so that the semiconductor structure 100 can be prevented from being broken by the first corner 100a or the second corner 100b. The situation in which the semiconductor structure 100 is inferior in yield due to rupture or cracking.

Please refer to FIGS. 5 and 6 , which are a second preferred embodiment of the present invention, which differs from the first preferred embodiment in that the first guiding wall 134 , the second guiding wall 143 , the first The third conductive wall 136 and the fourth conductive wall 145 are curved surfaces. When the first conductive wall 134, the second conductive wall 143, the third conductive wall 136, and the fourth conductive wall 145 are In the case of the curved surface, the stress of the semiconductor structure 100 can be prevented from being concentrated on the intersection of the first sidewall 132 and the second sidewall 133 of the second protective layer 130 (adjacent to the first corner 100a), thereby preventing The semiconductor structure 100 is broken or broken by the intersection of the first sidewall 132 and the second sidewall 133.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Semiconductor structure
100a‧‧‧First Corner
100b‧‧‧Second Corner
110‧‧‧ Carrier
111‧‧‧ Carrier surface
111a‧‧‧Protective setting area
111b‧‧‧Protected area
120‧‧‧First protective layer
121‧‧‧ first surface
121a‧‧‧First setting area
121b‧‧‧First stress resistant zone
121c‧‧‧First exposed area
121d‧‧‧ third stress-resistant zone
130‧‧‧Second protective layer
131‧‧‧second surface
131a‧‧‧Second setting area
131b‧‧‧second stress-resistant zone
131c‧‧‧Second exposure area
131d‧‧‧fourth stress-resistant zone
132‧‧‧First side wall
132a‧‧‧ first bottom
132b‧‧‧ first top side
133‧‧‧Second side wall
133a‧‧‧second bottom
133b‧‧‧second top side
134‧‧‧First guide wall
135‧‧‧ fifth side wall
135a‧‧‧ fifth bottom
135b‧‧‧ third top side
136‧‧‧The third guide wall
140‧‧‧ third protective layer
141‧‧‧ third side wall
141a‧‧‧ third bottom
142‧‧‧fourth side wall
142a‧‧‧ fourth bottom
143‧‧‧Second guiding wall
144‧‧‧ Sixth Side Wall
144a‧‧‧ sixth bottom
145‧‧‧fourth guide wall
A1‧‧‧ first base point
A2‧‧‧ second base point
A3‧‧‧ third base point
A4‧‧‧ fourth base point
D1‧‧‧First distance
D2‧‧‧Second distance
D3‧‧‧ third distance
D4‧‧‧ fourth distance
D5‧‧‧ fifth distance
D6‧‧‧ sixth distance
D7‧‧‧ seventh distance
D8‧‧‧ eighth distance
D9‧‧‧ ninth distance
D10‧‧‧10th distance
L1‧‧‧ first extension line
L2‧‧‧ second extension line
L3‧‧‧ third extension line
L4‧‧‧ fourth extension line
L5‧‧‧ fifth extension line
L6‧‧‧ sixth extension line
L7‧‧‧ seventh extension line
L8‧‧‧ eighth extension line
P1‧‧‧ first endpoint
P2‧‧‧ second endpoint
P3‧‧‧ third endpoint
P4‧‧‧ fourth endpoint
P5‧‧‧ fifth endpoint
P6‧‧‧ sixth endpoint
P7‧‧‧ seventh endpoint
P8‧‧‧ eighth endpoint
P9‧‧‧ ninth endpoint
P10‧‧‧ tenth endpoint
P11‧‧‧ eleventh endpoint
P12‧‧‧ twelfth endpoint
200‧‧‧Semiconductor structure
210‧‧‧ Carrier
211‧‧‧ surface
220‧‧‧First protective layer
221‧‧‧First side wall
222‧‧‧Second side wall
230‧‧‧Second protective layer
231‧‧‧ Third Side Wall
232‧‧‧fourth side wall
240‧‧‧ third protective layer
241‧‧‧ Fifth side wall
242‧‧‧ Sixth Side Wall

Figure 1 is a perspective exploded view of a semiconductor structure in accordance with a first preferred embodiment of the present invention. Figure 2 is a perspective view of the semiconductor structure in accordance with a first preferred embodiment of the present invention. Figure 3: A top view of the semiconductor structure in accordance with a first preferred embodiment of the present invention. Figure 4 is another perspective view of the semiconductor structure in accordance with a first preferred embodiment of the present invention. Figure 5 is a perspective view of a semiconductor structure in accordance with a second preferred embodiment of the present invention. Figure 6 is a top plan view of the semiconductor structure in accordance with a second preferred embodiment of the present invention. Figure 7: A perspective view of a conventional semiconductor structure.

100‧‧‧Semiconductor structure

100a‧‧‧First Corner

100b‧‧‧Second Corner

110‧‧‧ Carrier

120‧‧‧First protective layer

121c‧‧‧First exposed area

121b‧‧‧First stress resistant zone

130‧‧‧Second protective layer

131c‧‧‧Second exposure area

131b‧‧‧second stress-resistant zone

132‧‧‧First side wall

132a‧‧‧ first bottom

132b‧‧‧ first top side

133‧‧‧Second side wall

133a‧‧‧second bottom

133b‧‧‧second top side

134‧‧‧First guide wall

140‧‧‧ third protective layer

141‧‧‧ third side wall

141a‧‧‧ third bottom

142‧‧‧fourth side wall

142a‧‧‧ fourth bottom

143‧‧‧Second guiding wall

A1‧‧‧ first base point

A2‧‧‧ second base point

L1‧‧‧ first extension line

L2‧‧‧ second extension line

L3‧‧‧ third extension line

L4‧‧‧ fourth extension line

P1‧‧‧ first endpoint

P2‧‧‧ second endpoint

P3‧‧‧ third endpoint

P4‧‧‧ fourth endpoint

P5‧‧‧ fifth endpoint

P6‧‧‧ sixth endpoint

Claims (15)

A semiconductor structure having a first corner 隅 and a second corner 隅, the semiconductor structure comprising: a carrier having a carrier surface, the carrier surface having a protective layer disposed region and a laterally disposed outside the protective layer disposed region a protective layer exposed region; a first protective layer disposed in the protective layer disposed region, the first protective layer having a first surface, the first surface having a first disposed region, at least one first stress resistant region And a first exposed area located outside the first setting area and the first anti-stress area, the first anti-stress area is located at an angle 该 of the first setting area; a second protective layer is disposed at the first a second protective layer having a second surface, the second protective layer having a second surface, the second surface having at least one second anti-corrosion region and the first anti-stress region a stress region and a second exposed region outside the second set region and the second stress resistant region, the second stress resistant region is located at a corner of the second set region; and a third protective layer disposed on the The second setting And the third protection layer exposes the second stress resistant area and the second exposed area, the first stress resistant area and the second stress resistant area are located at the first corner, and the area of the first stress resistant area Not less than the area of the second stress resistant zone. The semiconductor structure of claim 1, wherein the second protective layer has a first sidewall, a second sidewall, and a first connection connecting the first sidewall and the second sidewall a wall, the first side wall has a first bottom edge and the first bottom edge has a first end point, the second side wall has a second bottom edge and the second bottom edge has a second end point, a first extension line extending from the first end point of the first bottom edge intersects with a second extension line formed by the second end point of the second bottom edge to form a first base point, and is connected The first base point, the area formed by the first end point and the second end point is the first stress resistant area. The semiconductor structure of claim 1, wherein the third protective layer has a third side wall, a fourth side wall, and a second guiding connection connecting the third side wall and the fourth side wall. a wall, the third side wall has a third bottom edge and the third bottom edge has a third end point, the fourth side wall has a fourth bottom edge and the fourth bottom edge has a fourth end point, a third extension line formed by extending the third end point of the third bottom edge intersects with a fourth extension line formed by the fourth end point of the fourth bottom edge to form a second base point, and is connected The second base point, the area formed by the third end point and the fourth end point are the second stress resistant area. The semiconductor structure of claim 3, wherein the second base point and the third end point have a first distance, the second base point and the fourth end point have a second distance, the first The distance is equal to the second distance. The semiconductor structure of claim 3, wherein the second protective layer has a first sidewall, a second sidewall, and a first connection connecting the first sidewall and the second sidewall a wall, the first side wall has a first top edge and the first top edge has a fifth end point, the second side wall has a second top edge and the second top edge has a sixth end point, a third distance from the fifth end point to the third end point, the third distance being a shortest distance from the first top edge to the third bottom edge, the sixth end point to the fourth end point There is a fourth distance between them, and the fourth distance is the shortest distance from the second top edge to the fourth bottom edge. The semiconductor structure of claim 2, wherein the first conductive wall is a flat surface or a curved surface. The semiconductor structure of claim 3, wherein the second conductive wall is a flat surface or a curved surface. The semiconductor structure of claim 1, wherein the first surface of the first protective layer has at least one third stress resistant region, and the third stress resistant region is located at a corner of the first set region, The second protective layer exposes the third stress resistant region, the second surface of the second protective layer has at least one fourth stress resistant region, and the fourth stress resistant region is located at a corner of the second set region, and the The third protective layer exposes the fourth anti-stress zone, the third anti-stress zone and the fourth anti-stress zone are located at the second corner, and the area of the third anti-stress zone is not less than the fourth anti-stress zone area. The semiconductor structure of claim 8, wherein the second protective layer has a first side wall, a fifth side wall, and a third connection connecting the first side wall and the fifth side wall. a wall, the first side wall has a first bottom edge and the first bottom edge has a seventh end point, the fifth side wall has a fifth bottom edge and the fifth bottom edge has an eighth end point, a fifth extension line extending from the seventh end point of the first bottom edge intersects with a sixth extension line formed by the eighth end point of the fifth bottom edge to form a third base point, and is connected The third base point, the area formed by the seventh end point and the eighth end point are the third stress resistant area. The semiconductor structure of claim 8, wherein the third protective layer has a third side wall, a sixth side wall, and a fourth guiding connection connecting the third side wall and the sixth side wall. a wall, the third side wall has a third bottom edge and the third bottom edge has a ninth end point, the sixth side wall has a sixth bottom edge and the sixth bottom edge has a tenth end point, a seventh extension line formed by extending the ninth end point of the third bottom edge intersects with an eighth extension line formed by the tenth end point of the sixth bottom edge to form a fourth base point, and is connected The fourth base point, the area formed by the ninth end point and the tenth end point are the fourth stress resistant area. The semiconductor structure of claim 10, wherein the second protective layer has a first sidewall, a fifth sidewall, and a third junction connecting the first sidewall and the fifth sidewall a wall, the first side wall has a first top edge and the first top edge has an eleventh end point, the fifth side wall has a third top edge and the third top edge has a twelfth end a fifth distance from the eleventh end point to the ninth end point, the fifth distance being a shortest distance from the first top edge to the third bottom edge, the twelfth end point to the There is a sixth distance between the tenth end points, and the sixth distance is the shortest distance from the third top edge to the sixth bottom edge. The semiconductor structure of claim 9, wherein the third base point and the seventh end point have a seventh distance, the third base point and the eighth end point have an eighth distance, the seventh The distance is equal to the eighth distance. The semiconductor structure of claim 10, wherein the fourth base point and the ninth end point have a ninth distance, the fourth base point and the tenth end point have a tenth distance, the ninth The distance is equal to the tenth distance. The semiconductor structure of claim 9, wherein the third conductive wall is a flat surface or a curved surface. The semiconductor structure of claim 10, wherein the fourth conductive wall is a flat surface or a curved surface.