KR20150016110A - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
KR20150016110A
KR20150016110A KR1020140096432A KR20140096432A KR20150016110A KR 20150016110 A KR20150016110 A KR 20150016110A KR 1020140096432 A KR1020140096432 A KR 1020140096432A KR 20140096432 A KR20140096432 A KR 20140096432A KR 20150016110 A KR20150016110 A KR 20150016110A
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South Korea
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end point
base
region
distance
point
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KR1020140096432A
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Korean (ko)
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KR101613190B1 (en
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진-탕 셰
시-런 궈
유-밍 쉬
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칩본드 테크놀러지 코포레이션
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Pressure Sensors (AREA)

Abstract

A semiconductor structure having a first corner, the semiconductor structure comprising a carrier, a first passivation layer, a second passivation layer and a third passivation layer, the carrier having a carrier surface, Wherein the first protective layer is provided on the protective layer mounting region, the first protective layer has a first surface, and the first surface includes a first mounting region, a first anti-stress region, Stress area is located at a corner of the first installation area, the second protection layer is installed in the first installation area, and the second protection layer has a second surface Wherein the second surface includes a second mounting region, a second anti-stress region, and a second exposed region, the second anti-stress region is located at a corner of the second mounting region, Is installed in the second installation area, and the first anti-stress Station and the second anti-stress zone is located in the first corner, the first area of the first region, wherein the stress is not less than the area of the second anti-stress areas.

Description

Semiconductor structure [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure capable of preventing stress from concentrating on a corner.

7 illustrates a conventional semiconductor structure 200 that includes a carrier 210, a first passivation layer 220, a second passivation layer 230, and a third passivation layer 240. Wherein the carrier has a surface 211 and the first passivation layer 220 is disposed on the surface 211 and the first passivation layer 220 includes a first sidewall 221, And a second side wall 222 connected to the first side wall 221. The second passivation layer 230 is provided on the first passivation layer 220 and the second passivation layer 230 is formed on the third side wall 231 and the fourth side wall 231 connected to the third side wall 231. [ (232). The third passivation layer 240 may be disposed on the second passivation layer 230 and the third passivation layer 240 may include a fifth side wall 241 and a sixth side wall 241 connected to the fifth side wall 241. [ (242). The first protective layer 220, the second protective layer 230 and the third protective layer 240 are different in size from each other and the third side wall 231 of the second protective layer 230, Since the connecting portions of the fourth sidewall 232 are at right angles and the connecting portions of the fifth sidewall 241 and the sixth sidewall 242 of the third passivation layer 240 are also at right angles, When the protective layer 220, the second protective layer 230 and the third protective layer 240 are laminated on the surface 211 of the carrier 210, The connecting portions of the third and fourth sidewalls 231 and 232 are easily ruptured or cut at the connecting portion between the third sidewall 231 and the fourth sidewall 232 of the first and second sidewalls 230 and 230, Which affects the yield of the semiconductor structure 200.

A main object of the present invention is to provide a semiconductor structure capable of preventing a semiconductor structure from being ruptured or cut at a corner by preventing the stress from concentrating on the corner of each protective layer, .

A semiconductor structure including a first corner and a second corner according to the present invention comprises a carrier, a first protective layer, a second protective layer and a third protective layer, the carrier having a carrier surface, And a protective layer exposed region located outside the protective layer mounting region. Wherein the first protective layer is provided in the protective layer mounting region and the first protective layer has a first surface, the first surface includes a first mounting region, at least one first anti-stress region, 1 installation area and a first exposure area located outside the first anti-stress area, wherein the first anti-stress area is located at the corner of the first installation area. Wherein the second protective layer is disposed in the first mounting region and the second protective layer exposes the first anti-stress region and the first exposed region, and the second protective layer has a second surface, Wherein the second surface comprises a second installation area, at least one second anti-stress area, and a second exposure area located outside the second installation area and the second anti-stress area, the second anti- And is located at a corner of the second installation area. Wherein the third protective layer is disposed in the second mounting region and the third protective layer exposes the second anti-stress region and the second exposed region, and wherein the first anti-stress region and the second anti- Is located at a first corner, and the area of the first anti-stress region is not smaller than the area of the second anti-stress region. Stress of the semiconductor structure is not concentrated in the first corner because the first protective layer of the present invention has the first anti-stress region and the second protective layer has the second anti-stress region, It is possible to prevent the semiconductor structure from being ruptured or cut at the first corner to lower the yield of the semiconductor structure.

According to the present invention, since the first protective layer has the first anti-stress region and the second protective layer has the second anti-stress region, the stress of the semiconductor structure is not concentrated at the first corner, It is possible to prevent the yield of the semiconductor structure from deteriorating due to rupture or cutting at one corner.

1 is a perspective view of a semiconductor structure according to a first preferred embodiment of the present invention.
2 is a perspective view of the semiconductor structure according to the first preferred embodiment of the present invention.
3 is a plan view of the semiconductor structure according to a first preferred embodiment of the present invention.
4 is another perspective view of the semiconductor structure according to the first preferred embodiment of the present invention.
5 is a perspective view of a semiconductor structure according to a second preferred embodiment of the present invention.
6 is a plan view of the semiconductor structure according to a second preferred embodiment of the present invention.
7 is a perspective view of a conventional semiconductor structure.

1 and 2 illustrate a semiconductor structure 100 having a first corner 100a and a second corner 100b according to a first preferred embodiment of the present invention, A first passivation layer 120, a second passivation layer 130, and a third passivation layer 140. The carrier 110 has a carrier surface 111. The carrier surface 111 has a protective layer mounting region 111a and a protective layer exposed region 111b located outside the protective layer mounting region 111a Wherein the first protective layer 120 is provided in the protective layer mounting region 111a and the first protective layer 120 has a first surface 121 and the first surface 121, Stressed region 121b and a first exposure region 121c located outside the first installation region 121a and the first anti-stress region 121b. The first installation region 121a, the at least one first anti-stress region 121b, Wherein the first anti-stress region 121b is located at a corner of the first mounting region 121a, the second protective layer 130 is located at the first mounting region 121a, 2 protective layer 130 exposes the first stress region 121b and the first exposed region 121c and the second passivation layer 120 has a second surface 131, 2 votes The surface 131 has a second mounting area 131a, at least one second unstressed area 131b and a second mounting area 131a and a second untwisted area 131b located outside the second unstressed area 131b. And an exposed region 131c, and the second anti-stress region 131b is located at a corner of the second installation region 131a.

2 and 3, the second passivation layer 130 may include a first sidewall 132, a second sidewall 133, and a second sidewall 133 connecting the first sidewall 132 and the second sidewall 133 And a first guide connecting wall 134 for connecting the first guide connecting wall 134 and the first guide connecting wall 134. The first sidewall 132 has a first base 132a having a first end point P1 and the second sidewall 133 has a second base 133a having a second endpoint P2. And a second extension line L1 extending from the first end point P1 of the first base line 132a and a second extension line L1 extending from the second end point P2 of the second base line 133a, The extension line L2 intersects each other to form a first base point A1 and the first base point A1 is formed by connecting the first end point P1 and the second end point P2, Stress region 121b. In this embodiment, the first guide connecting wall 134 is a flat surface.

Referring to FIGS. 1, 2 and 3, the third protective layer 140 is installed in the second mounting region 131a, and the second anti-stress region 131b and the second exposure region Stress region 121b and the second anti-stress region 131b are located at the first corner 100a and the area of the first anti-stress region 121b is exposed at the first corner 100a, Is not smaller than the area of the two-stress region 131b. The third protective layer 140 includes a third side wall 141 and a fourth side wall 142 and a second guide connecting wall 142 connecting the third side wall 141 and the fourth side wall 142. [ Wherein the third side wall 141 has a third base 141a having a third end point P3 and the fourth side wall 142 has a fourth end point P4 A third extension line L3 extending from the third end point P3 of the third base line 141a and a third extension line L3 extending from the fourth end point 142a of the fourth base line 142a, And the fourth extension line L4 extending from the second base point P4 intersect with each other to form a second base point A2. The area formed by connecting the second base point A2, the third end point P3 and the fourth end point P4 is the second anti-stress area 131b, and the second guide connection wall 143 are planar and a first distance D1 is between the second base point A2 and the third end point P3 and the second base point A2 and the fourth end point P4 , And the first distance D1 and the second distance D2 are equal to each other.

2 and 3, the first sidewall 132 of the second passivation layer 130 in the present embodiment further includes a first upper side 132b having a fifth end point P5 And the second side wall 133 has a second upper side 133b having a sixth end point P6 and a third distance 133b between the fifth end point P5 and the third end point P3, And the third distance D3 is the shortest distance from the first upper side 132b to the third base side 141a and the sixth end point P6 and the fourth end point P4 and the fourth distance D4 is the shortest distance from the second upper side 133b to the fourth lower side 142a.

1 and 4, the first surface 121 of the first passivation layer 120 further includes at least one third anti-stress region 121d, and the third anti-stress region 121d Is exposed at the corner of the first mounting region 121a and the second protective layer 130 exposes the third anti-stress region 121d and the second protective layer 130 is exposed at the second surface (131) has at least one fourth anti-stress region (131d). The fourth anti-stress region 131d is located at a corner of the second mounting region 131a, the third protective layer 140 exposes the fourth anti-stress region 131d, The area 121d and the fourth anti-stress area 131d are located at the second corner 100b and the area of the third anti-stress area 121d is smaller than the area of the fourth anti-stress area 131d not.

3 and 4, the second passivation layer 130 includes a fifth sidewall 135 and a third guide connection wall 136 connecting the first sidewall 132 and the fifth sidewall 135 Wherein the first base line 132a of the first sidewall 132 has a seventh end point P7 and the fifth sidewall 135 has an eighth end point P8, And the third guide connecting wall 136 is flat and has a fifth extension line L5 extending from the seventh end point P7 of the first base line 132a and a fifth extension line L5 extending from the seventh end point P7 of the first base line 132a, The sixth extension line L6 extending from the eighth end point P8 of the base line 135a intersects the third base point A3 to form the third base point A3, An area formed by connecting the end point P7 and the eighth end point P8 is a third-stress region 121d.

3 and 4, the third passivation layer 140 includes a sixth sidewall 144 and a fourth guide connecting wall 144 connecting the third sidewall 141 and the sixth sidewall 144 Wherein the third base 141a of the third sidewall 141 has a ninth end point P9 and the sixth sidewall 144 has a tenth end point P10 And a sixth base 144a. The fourth guide connecting wall 145 is flat and has a seventh extension L7 extending from the ninth end point P9 of the third base 141a and a seventh extension L7 extending from the tenth The eighth extension line L8 extending from the end point P10 intersects to form a fourth base point A4 and the fourth base point A4, the ninth end point P9, And the region formed by connecting the end point P10 is the fourth anti-stress region 131d.

3 and 4, the first upper side 132b of the first side wall 132 of the second passivation layer 130 has an eleventh end point P11, 135 has a third upper side 135b with a twelfth end point P12 and a fifth distance D5 between the eleventh end point P11 and the ninth end point P9, The fifth distance D5 is the shortest distance from the first upper side 132b to the third lower side 141a. A sixth distance D6 is present between the twelfth end point P12 and the tenth end point P10 and the sixth distance D6 is a distance from the third upper side 135b to the sixth base side 144a ). In addition, in the present embodiment, there is a seventh distance D7 between the third base point A3 and the seventh end point P7, and the seventh distance D7 between the third base point A3 and the eighth end point P7 The seventh distance D7 and the eighth distance D8 are the same between the fourth base point A4 and the ninth end point P9 and the eighth distance D8 is the same between the fourth base point A4 and the ninth end point P9, And a tenth distance D10 between the fourth base point A4 and the tenth end point P10 and the ninth distance D9 and the tenth distance D10 between the fourth base point A4 and the tenth end point P10, (D10) are the same.

The first and second anti-stress regions 121b and 131b of the present invention are located at the first corner 100a and the third and fourth anti-stress regions 121d and 121d, 131d are located at the second corner 100b so that stress can be prevented from concentrating on the first corner 100a and the second corner 100b, The first guide connecting wall 134 and the third guide connecting wall 136 and the second guide connecting wall 143 and the fourth guide connecting wall 145 of the third protecting layer 140 are also stressed The semiconductor structure 100 is prevented from being concentrated at the corner so that the semiconductor structure 100 is cut or ruptured at the first corner 100a or the second corner 100b to deteriorate the yield of the semiconductor structure 100 The situation can be prevented.

Figures 5 and 6 are second preferred embodiments of the present invention. The first guide connecting wall 134, the second guide connecting wall 143, the third guide connecting wall 136, and the fourth guide connecting wall 145 are different from the first preferred embodiment, . When the first guide connection wall 134, the second guide connection wall 143, the third guide connection wall 136 and the fourth guide connection wall 145 are the arc surface, (A portion adjacent to the first corner 100a) of the first sidewall 132 and the second sidewall 133 of the second passivation layer 130, It is possible to prevent the semiconductor structure 100 from being cut or ruptured at the contact portions of the first sidewall 132 and the second sidewall 133.

The scope of the present invention is defined by the appended claims, and all changes and modifications that come within the spirit and scope of the present invention will become apparent to those skilled in the art to which the present invention pertains Belongs.

100: semiconductor structure
110: Carrier
111a: Protective layer mounting area
120: first protective layer
121: first surface
121b: Section 1 stress area
121c: first exposure area
130: second protective layer
131: second surface
131a: Second installation area
131b: 2nd-stress region
131c: second exposure area
140: Third protective layer

Claims (15)

In a semiconductor structure having a first corner and a second corner,
The semiconductor structure may include:
A carrier surface including a protective layer mounting region and a protective layer exposed region located outside the protective layer mounting region;
And a second exposure region provided in the protective layer mounting region and including a first mounting region, at least one first anti-stress region, and a first exposure region located outside the first mounting region and the first anti- Wherein the first anti-stress region is located at a corner of the first mounting region;
Wherein said first installation region and said second installation region are located in said first installation region and expose said first anti-stress region and said first exposure region, and wherein said second installation region, said at least one second anti- And a second surface including a second exposed region located outside the region, wherein the second anti-stress region is located at a corner of the second mounting region; And
Stress zone and the second anti-stress zone are located in the first corner, and the first anti-stress zone and the second anti-stress zone are disposed in the second installation zone, exposing the second anti-stress zone and the second exposure zone, The area of the stress area is not smaller than the area of the second anti-stress area;
≪ / RTI > The method according to claim 1,
Wherein the second protective layer includes a first sidewall, a second sidewall, and a first guide connecting wall connecting the first sidewall and the second sidewall, the first sidewall having a first base wall having a first end point, Wherein the second side wall has a second base end having a second end point and wherein a first extension line extending from the first end point of the first base end and a second extension line extending from the second end point of the second base end, Wherein the first extension point and the second extension point intersect each other to form a first base point, and an area formed by connecting the first base point, the first end point, and the second end point is the first anti- . The method according to claim 1,
The third protective layer includes a third side wall, a fourth side wall, and a second guide connecting wall connecting the third side wall and the fourth side wall, and the third side wall has a third base wall having a third end point Wherein the fourth sidewall has a fourth base end having a fourth end point and a third extension line extending from the third end point of the third base end and a third extension line extending from the fourth end point of the fourth base end, Wherein the extended fourth extension line intersects each other to form a second base point and an area formed by connecting the second base point and the third end point to the fourth end point is the second anti- . The method of claim 3,
A first distance between the second base point and the third end point, a second distance between the second base point and the fourth end point, and wherein the first distance and the second distance are the same , Semiconductor structure. The method of claim 3,
Wherein the second protective layer comprises a first sidewall, a second sidewall, and a first guide connecting wall connecting the first sidewall and the second sidewall, the first sidewall having a first upper side The second side wall having a second upper side having a sixth end point, a third distance between the fifth end point and the third end point, and the third distance being located at the first upper side A fourth distance between the sixth end point and the fourth point, and the fourth distance being the shortest distance from the second upper side to the fourth base side. 3. The method of claim 2,
Wherein the first guide connecting wall is planar or arcuate. The method of claim 3,
And wherein the second guide connecting wall is planar or curved. The method according to claim 1,
Wherein the first surface of the first protective layer has at least one third anti-stress region, the third anti-stress region is located at a corner of the first mounting region, and the second protective layer comprises the third anti- Wherein the second surface of the second protective layer has at least one fourth anti-stress region, the fourth anti-stress region is located at a corner of the second mounting region, and the third anti- Wherein the protective layer exposes the fourth anti-stress region, the third anti-stress region and the fourth anti-stress region are located at the second corner, and the area of the third anti- The area being smaller than the area. 9. The method of claim 8,
Wherein the second protective layer includes a first sidewall, a fifth sidewall, and a third guide connection wall connecting the first sidewall and the fifth sidewall, the first sidewall having a first base wall having a seventh end point, Wherein the fifth sidewall has a fifth base having an eighth end point and a fifth extension extending from the seventh end point of the first base and a fourth extension extending from the eighth end point of the fifth base, Wherein the extended sixth extension line intersects each other to form a third base point and an area formed by connecting the third base point and the seventh end point to the eighth end point is the third anti- . 9. The method of claim 8,
The third protective layer includes a third side wall, a sixth side wall, and a fourth guide connecting wall connecting the third side wall and the sixth side wall, and the third side wall has a third base wall having a ninth end point Wherein the sixth side wall has a sixth base having a tenth end point, and wherein the seventh extension extending from the ninth end point of the third base and the seventh extension extending from the tenth end point of the sixth base, Wherein the extended eighth extension lines intersect to form a fourth base point and an area formed by connecting the fourth base point, the ninth end point, and the tenth end point is a fourth anti-stress region. 11. The method of claim 10,
Wherein the second protective layer includes a first side wall, a fifth side wall, and a third guide connecting wall connecting the first side wall and the fifth side wall, the first side wall having a first upper side having an eleventh end point Wherein the fifth side wall has a third upper side having a twelfth end point, a fifth distance between the eleventh end point and the ninth end point, and the fifth distance is a distance from the first upper side to the third upper side having the twelfth end point, A sixth distance between the twelfth end point and the tenth end point, and the sixth distance is the shortest distance from the third upper side to the sixth upper side. 10. The method of claim 9,
There is a seventh distance between the third base point and the seventh end point, an eighth distance between the third base point and the eighth end point, and the seventh distance and the eighth distance are equal to each other , Semiconductor structure. 11. The method of claim 10,
There is a ninth distance between the fourth base point and the ninth end point, a tenth distance between the fourth base point and the tenth end point, and the ninth distance and the tenth distance are equal to each other , Semiconductor structure. 10. The method of claim 9,
And said third guide connecting wall is planar or arc-shaped. 11. The method of claim 10,
And the fourth guide connecting wall is a flat surface or a curved surface.
KR1020140096432A 2013-08-02 2014-07-29 Semiconductor structure KR101613190B1 (en)

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TW102127697A TWI467757B (en) 2013-08-02 2013-08-02 Semiconductor structure
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JP5933645B2 (en) 2016-06-15
KR101613190B1 (en) 2016-04-18
TW201507148A (en) 2015-02-16
TWI467757B (en) 2015-01-01
CN104347682A (en) 2015-02-11
SG10201404283UA (en) 2015-03-30
JP2015032826A (en) 2015-02-16

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