TWI520288B - Semiconductor structure and package - Google Patents

Semiconductor structure and package Download PDF

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Publication number
TWI520288B
TWI520288B TW100135984A TW100135984A TWI520288B TW I520288 B TWI520288 B TW I520288B TW 100135984 A TW100135984 A TW 100135984A TW 100135984 A TW100135984 A TW 100135984A TW I520288 B TWI520288 B TW I520288B
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barrier layer
organic barrier
copper
semiconductor package
layer
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TW100135984A
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Chinese (zh)
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TW201316470A (en
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施政宏
林淑真
謝永偉
葉潤宇
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頎邦科技股份有限公司
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Priority to TW100135984A priority Critical patent/TWI520288B/en
Priority to JP2012138131A priority patent/JP2013080899A/en
Priority to KR1020120083793A priority patent/KR101350289B1/en
Priority to SG2012069571A priority patent/SG189617A1/en
Publication of TW201316470A publication Critical patent/TW201316470A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體結構及其封裝構造 Semiconductor structure and its package structure

本發明係有關於一種半導體結構，特別係有關於一種具有有機阻障層之半導體結構。 The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having an organic barrier layer.

由於電子產品之外觀已逐漸趨向輕、薄、短、小發展，因此凸塊或引腳等電性連接元件必然朝向微細間距發展，然當凸塊或引腳等電性連接元件若含有銅時，容易因為銅離子游離而導致電性短路，進而造成產品不良之情形。 Since the appearance of electronic products has gradually become light, thin, short, and small, the electrical connection elements such as bumps or pins must be developed toward fine pitches, but when the bumps or pins and other electrical connecting elements contain copper, It is easy to cause an electrical short circuit due to the release of copper ions, which may cause a bad product.

本發明之主要目的係在於提供一種半導體結構，其包含一載體、複數個凸塊下金屬層、複數個含銅凸塊以及至少一有機阻障層，該載體係具有一表面、一形成於該表面之保護層及複數個形成於該表面之導接墊，該保護層係具有複數個開口且該些開口係顯露該些導接墊，該些凸塊下金屬層係形成於該些導接墊，該些含銅凸塊係形成於該些凸塊下金屬層，各該含銅凸塊係具有一頂面及一連接該頂面之環壁，該有機阻障層係具有一凸塊覆蓋部，該凸塊覆蓋部係覆蓋各該含銅凸塊之該頂面及該環壁。由於該半導體結構係包含有該有機阻障層，因此可防止該些含銅凸塊於微細間距時因銅離子游離而導致電性短路之情形。 The main object of the present invention is to provide a semiconductor structure comprising a carrier, a plurality of under bump metal layers, a plurality of copper bumps, and at least one organic barrier layer, the carrier having a surface formed thereon a protective layer of the surface and a plurality of conductive pads formed on the surface, the protective layer has a plurality of openings and the openings expose the conductive pads, and the under bump metal layers are formed on the conductive pads a pad, the copper-containing bumps are formed on the under-metal layers of the bumps, each of the copper-containing bumps has a top surface and a ring wall connecting the top surface, the organic barrier layer having a bump a cover portion covering the top surface of each of the copper-containing bumps and the ring wall. Since the semiconductor structure includes the organic barrier layer, it is possible to prevent the copper-containing bumps from being electrically short-circuited due to the release of copper ions at fine pitches.

請參閱第1圖，其係本發明之第一較佳實施例，一種 半導體結構100係包含一載體110、複數個凸塊下金屬層120、複數個含銅凸塊130以及至少一有機阻障層140，該載體110係具有一表面111、一形成於該表面111之保護層112及複數個形成於該表面111之導接墊113，該保護層112係具有複數個開口112a且該些開口112a係顯露該些導接墊113，該載體110係可選自於矽基板、玻璃基板、陶瓷基板或銅箔基板其中之一，在本實施例中，該載體110係可為矽基板，該些凸塊下金屬層120係形成於該些導接墊113，該些含銅凸塊130係形成於該些凸塊下金屬層120，各該含銅凸塊130係具有一頂面131及一連接該頂面131之環壁132，該有機阻障層140係具有一凸塊覆蓋部141，該凸塊覆蓋部141係覆蓋各該含銅凸塊130之該頂面131及該環壁132。較佳地，各該凸塊下金屬層120係具有一環牆121，該凸塊覆蓋部141係覆蓋各該凸塊下金屬層120之該環牆121，在本實施例中，該有機阻障層140之厚度係小於10um，該有機阻障層140之材質係選自於有機高分子材料，該有機阻障層140係選自於苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑其中之一，其結構式如下： Referring to FIG. 1 , a first preferred embodiment of the present invention, a semiconductor structure 100 includes a carrier 110 , a plurality of under bump metal layers 120 , a plurality of copper bumps 130 , and at least one organic barrier The layer 140 has a surface 111, a protective layer 112 formed on the surface 111, and a plurality of via pads 113 formed on the surface 111. The protective layer 112 has a plurality of openings 112a and the openings The conductive pads 113 are exposed to 112a, and the carrier 110 may be selected from one of a germanium substrate, a glass substrate, a ceramic substrate or a copper foil substrate. In the embodiment, the carrier 110 may be a germanium substrate. The under bump metal layer 120 is formed on the conductive pads 113, and the copper bumps 130 are formed on the under bump metal layers 120. Each of the copper bumps 130 has a top surface 131 and A ring-shaped wall 132 is connected to the top surface 131. The organic barrier layer 140 has a bump covering portion 141. The bump covering portion 141 covers the top surface 131 of each of the copper-containing bumps 130 and the ring wall. 132. Preferably, each of the under bump metal layers 120 has a ring wall 121 covering the ring wall 121 of each of the under bump metal layers 120. In this embodiment, the organic barrier is The thickness of the layer 140 is less than 10 um, and the material of the organic barrier layer 140 is selected from an organic polymer material, and the organic barrier layer 140 is selected from the group consisting of phenyl bis-triazole, phenylimidazole, and an alternative phenyl group. One of imidazole or aromatic hydroxyimidazole, the structural formula is as follows:

該有機阻障層140係由苯駢咪唑化合物、甲酸、氨水、醋酸及水所組成，且該有機阻障層混合物之黏度範圍係為1-1.2cp。由於該半導體結構100係包含有該有機阻障層140，因此可防止該些含銅凸塊130於微細間距時因銅離子游離而導致電性短路之情形。 The organic barrier layer 140 is composed of a benzoimidazole compound, formic acid, aqueous ammonia, acetic acid, and water, and the organic barrier layer mixture has a viscosity ranging from 1 to 1.2 cp. Since the semiconductor structure 100 includes the organic barrier layer 140, it is possible to prevent the copper-containing bumps 130 from being electrically short-circuited due to the release of copper ions at fine pitches.

或者，請參閱第2圖，其係本發明之第二較佳實施例，在本實施例中，該有機阻障層140係另具有一保護層覆蓋部142，該保護層覆蓋部142係覆蓋該保護層112。另，請參閱第3圖，其係本發明之第三較佳實施例，一種半導體結構200至少包含有一載體210、複數個含銅凸塊220以及至少一有機阻障層230，該載體210係具有一表面211、一形成於該表面211之保護層212及複數個形成於該表面211之導接墊213，該保護層212係具有複數個開口212a且該些開口212a係顯露該些導接墊213，該載體210係可選自於矽基板、玻璃基板、陶瓷基板或銅箔基板其中之一，在本實施例中，該載體210係可為矽基板，該些含銅凸塊220係形成於該些導接墊213，各該含銅凸塊220係具有一頂面221及一連接該頂面221之環壁222，該有機阻障層230係具有一凸塊覆蓋部231，該凸塊覆蓋部231係覆蓋各該含銅凸塊220之該頂面221及該環壁222 ，該有機阻障層230之厚度係小於10um，該有機阻障層230之材質係選自於有機高分子材料，該有機阻障層230係選自於苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑其中之一，且該有機阻障層230係由苯駢咪唑化合物、甲酸、氨水、醋酸及水所組成，且該有機阻障層混合物之黏度範圍係為1-1.2cp。 Or, referring to FIG. 2, which is a second preferred embodiment of the present invention, in the embodiment, the organic barrier layer 140 further has a protective layer covering portion 142, and the protective layer covering portion 142 is covered. The protective layer 112. In addition, referring to FIG. 3, which is a third preferred embodiment of the present invention, a semiconductor structure 200 includes at least one carrier 210, a plurality of copper-containing bumps 220, and at least one organic barrier layer 230. The protective layer 212 has a plurality of openings 212a and the openings 212a expose the conductive layers 212. Pad 213, the carrier 210 may be selected from one of a ruthenium substrate, a glass substrate, a ceramic substrate or a copper foil substrate. In this embodiment, the carrier 210 may be a ruthenium substrate, and the copper-containing bumps 220 are Each of the copper-containing bumps 220 has a top surface 221 and a ring wall 222 connecting the top surface 221. The organic barrier layer 230 has a bump covering portion 231. The bump cover portion 231 covers the top surface 221 of each of the copper-containing bumps 220 and the ring wall 222 The thickness of the organic barrier layer 230 is less than 10 um, and the material of the organic barrier layer 230 is selected from an organic polymer material, and the organic barrier layer 230 is selected from the group consisting of phenyl bis-triazole and phenylimidazole. One of an alternative phenylimidazole or an aromatic hydroxyimidazole, and the organic barrier layer 230 is composed of a benzoimidazole compound, formic acid, aqueous ammonia, acetic acid, and water, and the viscosity range of the organic barrier layer mixture is It is 1-1.2cp.

接著，請參閱第4A至4G圖，其係本發明之第一較佳實施例之半導體結構製程，其至少包含下列步驟：首先，請參閱第4A圖，提供一載體110，該載體110係具有一表面111、一形成於該表面111之保護層112及複數個形成於該表面111之導接墊113，該保護層112係具有複數個開口112a且該些開口112a係顯露該些導接墊113，該載體110係可選自於矽基板、玻璃基板、陶瓷基板或銅箔基板其中之一，在本實施例中，該載體110係可為矽基板；接著，請參閱第4B圖，形成複數個凸塊下金屬層120於該些導接墊113，該些凸塊下金屬層120係延伸形成於該保護層112且各該凸塊下金屬層120係具有一環牆121；之後，請參閱第4C圖，形成一光阻層P於該保護層112及該些凸塊下金屬層120；接著，請參閱第4D圖，圖案化該光阻層P以形成複數個凸塊開口P1，該些凸塊開口P1係顯露該些凸塊下金屬層120；之後，請參閱第4E圖，形成一含銅金屬層M於該些凸塊下金屬層120上，以使該含銅金屬層M形成複數個含銅凸塊130；接著，請參閱第4F圖，移除該光阻層P以顯露出該些含銅凸塊130，各該含銅凸塊130係具有一頂面131及一連接該頂面131之環壁132；最後，請參閱第4G圖，形成一有機阻障層140於該些含銅 凸塊130，且該有機阻障層140係具有一凸塊覆蓋部141，該凸塊覆蓋部141係覆蓋各該含銅凸塊130之該頂面131、該環壁132及各該凸塊下金屬層120之該環牆121，在本實施例中，該有機阻障層140之厚度係小於10um，該有機阻障層140之材質係選自於有機高分子材料，該有機阻障層140係選自於苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑其中之一，其結構式如下： Next, please refer to FIGS. 4A to 4G, which are semiconductor structure processes of the first preferred embodiment of the present invention, which at least comprise the following steps: First, referring to FIG. 4A, a carrier 110 is provided, the carrier 110 having a surface 111, a protective layer 112 formed on the surface 111, and a plurality of via pads 113 formed on the surface 111. The protective layer 112 has a plurality of openings 112a and the openings 112a expose the conductive pads 113, the carrier 110 may be selected from one of a germanium substrate, a glass substrate, a ceramic substrate or a copper foil substrate. In the embodiment, the carrier 110 may be a germanium substrate; then, refer to FIG. 4B to form A plurality of under bump metal layers 120 are formed on the conductive pads 113. The under bump metal layers 120 are formed on the protective layer 112 and each of the under bump metal layers 120 has a ring wall 121. Referring to FIG. 4C, a photoresist layer P is formed on the protective layer 112 and the under bump metal layers 120. Next, referring to FIG. 4D, the photoresist layer P is patterned to form a plurality of bump openings P1. The bump openings P1 expose the under bump metal layers 120; Referring to FIG. 4E, a copper-containing metal layer M is formed on the under bump metal layer 120 to form the copper-containing metal layer M to form a plurality of copper-containing bumps 130; then, refer to FIG. 4F. The photoresist layer P is removed to expose the copper-containing bumps 130. Each of the copper-containing bumps 130 has a top surface 131 and a ring wall 132 connecting the top surface 131. Finally, please refer to FIG. 4G. An organic barrier layer 140 is formed on the copper-containing bumps 130, and the organic barrier layer 140 has a bump covering portion 141. The bump covering portion 141 covers the copper-containing bumps 130. In the embodiment, the thickness of the organic barrier layer 140 is less than 10 um, and the material of the organic barrier layer 140 is less than 10 um. The organic barrier material layer 140 is selected from the group consisting of phenyl bis-triazole, phenylimidazole, substituted phenylimidazole or aromatic hydroxy imidazole, and has the following structural formula:

該有機阻障層140係由苯駢咪唑化合物、甲酸、氨水、醋酸及水所組成，且該有機阻障層混合物之黏度範圍係為1-1.2cp。 The organic barrier layer 140 is composed of a benzoimidazole compound, formic acid, aqueous ammonia, acetic acid, and water, and the organic barrier layer mixture has a viscosity ranging from 1 to 1.2 cp.

此外，請參閱第5圖，其係應用本發明之第一較佳實施例之該半導體結構100所形成之半導體封裝構造10，其至少包含一半導體結構100以及一基板300，該半導體結構100係包含一載體110、複數個凸塊下金屬層120、複數個含銅凸塊130以及至少一有機阻障層140，該載體 110係具有一表面111、一形成於該表面111之保護層112及複數個形成於該表面111之導接墊113，該保護層112係具有複數個開口112a且該些開口112a係顯露該些導接墊113，該載體110係可選自於矽基板、玻璃基板、陶瓷基板或銅箔基板其中之一，在本實施例中，該載體110係可為矽基板，該些凸塊下金屬層120係形成於該些導接墊113，且各該凸塊下金屬層120係具有一環牆121，該些含銅凸塊130係形成於該些凸塊下金屬層120，各該含銅凸塊130係具有一頂面131及一連接該頂面131之環壁132，該有機阻障層140係具有一凸塊覆蓋部141，該凸塊覆蓋部141係覆蓋各該含銅凸塊130之該環壁132及各該凸塊下金屬層120之該環牆121，該有機阻障層140之厚度係小於10um，該有機阻障層140之材質係選自於有機高分子材料，該有機阻障層140係選自於苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑其中之一，且該有機阻障層140係由苯駢咪唑化合物、甲酸、氨水、醋酸及水所組成，且該有機阻障層混合物之黏度範圍係為1-1.2cp，該基板300係具有複數個連接墊310及一防銲層320，該防銲層320係具有複數個開槽321以顯露該些連接墊310，該些連接墊310係結合於該些含銅凸塊130且該有機阻障層140之該凸塊覆蓋部141係覆蓋該防銲層320。 In addition, referring to FIG. 5, a semiconductor package structure 10 formed by using the semiconductor structure 100 of the first preferred embodiment of the present invention includes at least a semiconductor structure 100 and a substrate 300, the semiconductor structure 100 a carrier 110, a plurality of under bump metal layers 120, a plurality of copper bumps 130, and at least one organic barrier layer 140, the carrier The 110 series has a surface 111, a protective layer 112 formed on the surface 111, and a plurality of via pads 113 formed on the surface 111. The protective layer 112 has a plurality of openings 112a and the openings 112a reveal the The conductive pad 113 may be selected from one of a germanium substrate, a glass substrate, a ceramic substrate or a copper foil substrate. In the embodiment, the carrier 110 may be a germanium substrate, and the bumps are under metal. The layer 120 is formed on the conductive pads 113, and each of the under bump metal layers 120 has a ring wall 121. The copper bumps 130 are formed on the under bump metal layers 120, each of which contains copper. The bump 130 has a top surface 131 and a ring wall 132 connecting the top surface 131. The organic barrier layer 140 has a bump covering portion 141 covering the copper-containing bumps. The ring wall 132 of the 130 and the ring wall 121 of each of the under bump metal layers 120 have a thickness of less than 10 um, and the material of the organic barrier layer 140 is selected from an organic polymer material. The organic barrier layer 140 is selected from the group consisting of phenyl bis-triazole, phenylimidazole, substituted phenylimidazole or aromatic One of the imidazoles, and the organic barrier layer 140 is composed of a benzoimidazole compound, formic acid, aqueous ammonia, acetic acid, and water, and the organic barrier layer mixture has a viscosity ranging from 1 to 1.2 cp, and the substrate 300 The soldering layer 320 has a plurality of slots 321 for exposing the connecting pads 310, and the connecting pads 310 are coupled to the copper-containing bumps 130. The bump covering portion 141 of the organic barrier layer 140 covers the solder resist layer 320.

本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。 The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

10‧‧‧半導體封裝構造 10‧‧‧Semiconductor package construction

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

110‧‧‧載體 110‧‧‧ Carrier

111‧‧‧表面 111‧‧‧ surface

112‧‧‧保護層 112‧‧‧Protective layer

112a‧‧‧開口 112a‧‧‧ Opening

113‧‧‧導接墊 113‧‧‧ Guide pads

120‧‧‧凸塊下金屬層 120‧‧‧Under bump metal layer

121‧‧‧環牆 121‧‧‧Circle wall

130‧‧‧含銅凸塊 130‧‧‧Bronze bumps

131‧‧‧頂面 131‧‧‧ top surface

132‧‧‧環壁 132‧‧‧Circle

140‧‧‧有機阻障層 140‧‧‧Organic barrier

141‧‧‧凸塊覆蓋部 141‧‧ ‧Bump covering

142‧‧‧保護層覆蓋部 142‧‧‧Protective Coverage

200‧‧‧半導體結構 200‧‧‧Semiconductor structure

210‧‧‧載體 210‧‧‧ Carrier

211‧‧‧表面 211‧‧‧ surface

212‧‧‧保護層 212‧‧‧Protective layer

212a‧‧‧開口 212a‧‧‧ openings

213‧‧‧導接墊 213‧‧‧ lead pad

220‧‧‧含銅凸塊 220‧‧‧ copper bumps

221‧‧‧頂面 221‧‧‧ top surface

222‧‧‧環壁 222‧‧‧

230‧‧‧有機阻障層 230‧‧‧Organic barrier layer

231‧‧‧凸塊覆蓋部 231‧‧‧Bump covering

300‧‧‧基板 300‧‧‧Substrate

310‧‧‧連接墊 310‧‧‧Connecting mat

320‧‧‧防銲層 320‧‧‧ solder mask

321‧‧‧開槽 321‧‧‧ slotting

M‧‧‧含銅金屬層 M‧‧‧ copper-containing metal layer

P‧‧‧光阻層 P‧‧‧ photoresist layer

P1‧‧‧凸塊開口 P1‧‧‧Bump opening

第1圖：依據本發明之第一較佳實施例，一種半導體結構之截面示意圖。 Figure 1 is a cross-sectional view showing a semiconductor structure in accordance with a first preferred embodiment of the present invention.

第2圖：依據本發明之第二較佳實施例，另一種半導體結構之截面示意圖。 Figure 2 is a schematic cross-sectional view showing another semiconductor structure in accordance with a second preferred embodiment of the present invention.

第3圖：依據本發明之第三較佳實施例，又一種半導體結構之截面示意圖。 Figure 3 is a cross-sectional view showing still another semiconductor structure in accordance with a third preferred embodiment of the present invention.

第4A至4G圖：依據本發明之第一較佳實施例，該半導體結構製程之截面示意圖。 4A to 4G are schematic cross-sectional views showing the process of the semiconductor structure in accordance with a first preferred embodiment of the present invention.

第5圖：依據本發明之第一較佳實施例，應用該半導體結構所形成之半導體封裝構造。 Figure 5: A semiconductor package structure formed using the semiconductor structure in accordance with a first preferred embodiment of the present invention.

100‧‧‧半導體結構 100‧‧‧Semiconductor structure

110‧‧‧載體 110‧‧‧ Carrier

111‧‧‧表面 111‧‧‧ surface

112‧‧‧保護層 112‧‧‧Protective layer

112a‧‧‧開口 112a‧‧‧ Opening

113‧‧‧導接墊 113‧‧‧ Guide pads

120‧‧‧凸塊下金屬層 120‧‧‧Under bump metal layer

121‧‧‧環牆 121‧‧‧Circle wall

130‧‧‧含銅凸塊 130‧‧‧Bronze bumps

131‧‧‧頂面 131‧‧‧ top surface

132‧‧‧環壁 132‧‧‧Circle

140‧‧‧有機阻障層 140‧‧‧Organic barrier

141‧‧‧凸塊覆蓋部 141‧‧ ‧Bump covering

Claims (9)

一種半導體封裝構造，其至少包含：一半導體結構，其包含：一載體，其係具有一表面、一形成於該表面之保護層及複數個形成於該表面之導接墊，該保護層係具有複數個開口且該些開口係顯露該些導接墊；複數個凸塊下金屬層，其係形成於該些導接墊；複數個含銅凸塊，其係形成於該些凸塊下金屬層，各該含銅凸塊係具有一頂面及一連接該頂面之環壁；以及至少一有機阻障層，其係具有一凸塊覆蓋部，該凸塊覆蓋部係覆蓋各該含銅凸塊之該環壁；以及一基板，其係具有複數個連接墊及一防銲層，該防銲層係具有複數個開槽以顯露該些連接墊，該些連接墊係結合於該些含銅凸塊且該有機阻障層之該凸塊覆蓋部係覆蓋該防銲層。 A semiconductor package structure comprising at least: a semiconductor structure comprising: a carrier having a surface, a protective layer formed on the surface, and a plurality of via pads formed on the surface, the protective layer having a plurality of openings and the openings are used to expose the conductive pads; a plurality of under bump metal layers are formed on the conductive pads; a plurality of copper-containing bumps are formed under the bumps a layer, each of the copper-containing bumps having a top surface and a ring wall connecting the top surface; and at least one organic barrier layer having a bump covering portion covering each of the a ring wall of the copper bump; and a substrate having a plurality of connection pads and a solder resist layer, the solder resist layer having a plurality of slots for exposing the connection pads, the connection pads being bonded to the The copper bumps and the bump covering portion of the organic barrier layer cover the solder resist layer. 如申請專利範圍第1項所述之半導體封裝構造，其中該有機阻障層係另具有一保護層覆蓋部，該保護層覆蓋部係覆蓋該保護層。 The semiconductor package structure of claim 1, wherein the organic barrier layer further has a protective layer covering portion, the protective layer covering portion covering the protective layer. 如申請專利範圍第1項所述之半導體封裝構造，其中該有機阻障層之厚度係小於10um。 The semiconductor package structure of claim 1, wherein the organic barrier layer has a thickness of less than 10 um. 如申請專利範圍第1項所述之半導體封裝構造，其中該有機阻障層之黏度範圍係為1-1.2cp。 The semiconductor package structure of claim 1, wherein the organic barrier layer has a viscosity ranging from 1 to 1.2 cp. 如申請專利範圍第1項所述之半導體封裝構造，其中該有機阻障層之材質係選自於有機高分子材料。 The semiconductor package structure according to claim 1, wherein the material of the organic barrier layer is selected from the group consisting of organic polymer materials. 如申請專利範圍第5項所述之半導體封裝構造，其中該有 機阻障層係選自於苯基聯三連唑、苯基咪唑、替代性苯基咪唑或芳香族羥基咪唑其中之一。 The semiconductor package structure of claim 5, wherein the The barrier layer is selected from one of phenyl bis-triazole, phenylimidazole, substituted phenylimidazole or aromatic hydroxy imidazole. 如申請專利範圍第1項所述之半導體封裝構造，其中該有機阻障層係由苯駢咪唑化合物、甲酸、氨水、醋酸及水所組成。 The semiconductor package structure according to claim 1, wherein the organic barrier layer is composed of a benzoimidazole compound, formic acid, ammonia water, acetic acid, and water. 如申請專利範圍第1項所述之半導體封裝構造，其中該載體係可選自於矽基板、玻璃基板、陶瓷基板或銅箔基板其中之一。 The semiconductor package structure of claim 1, wherein the carrier is selected from one of a germanium substrate, a glass substrate, a ceramic substrate, or a copper foil substrate. 如申請專利範圍第1項所述之半導體封裝構造，其中各該凸塊下金屬層係具有一環牆，該凸塊覆蓋部係覆蓋各該凸塊下金屬層之該環牆。 The semiconductor package structure of claim 1, wherein each of the under bump metal layers has a ring wall covering the ring wall of each of the under bump metal layers.
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