KR20100006104A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to minimize hygroscopic property and effectively block the infiltration of the metal ion. CONSTITUTION: A semiconductor package comprises a semiconductor chip(410), a bonding pad(420), and a metal ion barrier layer(430). A semiconductor chip faces a first surface and a second surface in which a semiconductor device is formed. The bonding pad is formed on the second surface. The metal ion barrier layer is formed on the first surface and prevents the metal from being delivered through the first surface.

Description

Semiconductor Package {Semiconductor package}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of obtaining an excellent semiconductor device by minimizing hygroscopicity and effectively blocking the penetration of metal ions.

In accordance with the trend of miniaturization and miniaturization of electronic products, there is a continuous demand for miniaturization, weight reduction, and thinning of semiconductor packages mounted in electronic products. In order to satisfy such a demand, methods such as a multichip package or a system-in-package in which two or more semiconductor chips are mounted in one package have been proposed. In addition, technical development continues, such as manufacturing the thickness of the individual semiconductor chip mounted in a package to 50 micrometers or less, and also 30 micrometers or less.

On the other hand, such very thin semiconductor chips may be damaged due to the process, the process of attaching to the substrate, or the stress applied in the test process, backlap (backlap) for processing a thin semiconductor chip to prevent this phenomenon ) May include a polishing process to relieve stress. By the way, the roughness of the back surface of the semiconductor chip is greatly reduced during the polishing process, so that the back surface may be obtained with a very smooth surface. If the roughness of the back of the semiconductor chip is high, it has its own gettering effect.If the back roughness of the semiconductor chip is reduced through the polishing process, the ions may penetrate through the back of the semiconductor chip. This may reduce the reliability of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package capable of obtaining an excellent semiconductor device by minimizing hygroscopicity and effectively blocking the penetration of metal ions.

According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor chip having a first surface and a second surface opposite to the first surface and on which a semiconductor element is formed; A bonding pad provided on the second surface; And a metal ion blocking layer provided on the first surface and blocking a metal from being transferred through the first surface.

In particular, the semiconductor package includes a passivation layer on the second surface, the passivation layer exposing the bonding pads; And a solder ball provided on the bonding pad. Optionally, the semiconductor package may be a wafer level package (WLP).

Optionally, the semiconductor package comprises a semiconductor chip mounting portion; And a lead frame electrically connected to the bonding pad, wherein the semiconductor chip may be seated on the semiconductor chip mounting part with the metal ion blocking layer interposed therebetween. In addition, the semiconductor chip mounting portion may be made of copper. In particular, in the semiconductor package, a nickel layer may be formed on a surface of the semiconductor chip mounting part at a portion where the semiconductor chip mounting part contacts the metal ion blocking layer. In particular, the nickel layer may have a thickness of 2 μm to 20 μm. In addition, the metal ion barrier layer may be a polymer resin composition including an amine group. In particular, the polymer resin composition may be an epoxy resin including an amine group (-NH ₂ ). In particular, the epoxy resin constituting the metal ion barrier layer may be an amine group (-NH ₂ ) is bonded to the main chain of the epoxy resin.

In addition, the semiconductor package may further include an adhesive layer between the metal ion blocking layer and the semiconductor chip mounting part. In particular, the adhesive layer may include an acrylic resin.

The semiconductor package of the present invention has the effect of minimizing hygroscopicity and effectively blocking the penetration of metal ions to obtain an excellent semiconductor device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the invention are preferably interpreted to be provided to more completely explain the present invention to those skilled in the art. Like numbers refer to like elements all the time. Furthermore, various elements and regions in the drawings are schematically drawn. Accordingly, the present invention is not limited by the relative size or spacing drawn in the accompanying drawings. When a layer is described as being "on" another layer or semiconductor chip, the layer may be in direct contact with the other layer or semiconductor semiconductor chip, or a third layer may be interposed therebetween. It may be.

An embodiment of the present invention includes a semiconductor chip having a first surface and a second surface facing the first surface and on which a semiconductor element is formed; A bonding pad provided on the second surface; A semiconductor package is provided on the first surface, and includes a metal ion blocking layer capable of blocking the transfer of metal through the first surface.

In an embodiment, the semiconductor package may include a passivation layer exposing the bonding pads; And a solder ball provided on the bonding pad. In particular, the passivation layer may be provided on the second surface.

1 is a side cross-sectional view illustrating a semiconductor package 100 according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor chip 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a. For example, semiconductor elements (not shown) such as transistors may be formed on the second surface 110b, and a bonding pad 120 may be provided. In addition, the semiconductor devices on the second surface 110b may be connected to the bonding pads 120 through redistribution. As shown in FIG. 1, the semiconductor package 100 may be a wafer level package (WLP).

Optionally, a passivation layer 150 may be formed on the second surface 110b to cover the second surface 110b while exposing at least a portion of the bonding pads 120. The passivation layer 150 may be, for example, silicon oxide and / or silicon nitride formed by high density plasma chemical vapor deposition.

The metal ion blocking layer 130 may be formed on the first surface 110a of the semiconductor chip 110. The metal ion blocking layer 130 may include an ion blocking material. The ion blocking material may be magnesium (Mg) oxide, aluminum (Al) oxide, titanium (Ti) oxide, zirconium (Zr) oxide, bismuth (Bi) oxide, lanthanum (La) oxide, gadolinium (Gd) oxide, samarium (Sm). ) Oxide, thulium (Tm) oxide, europium (Eu) oxide, neodymium (Nd) oxide, erbium (Er) oxide, terbium (Tb) oxide, dysprosium (Dy) oxide, praseodymium (Pr) oxide, yttrium (Y) oxide , ytterbium (Yb) oxide, holmium (Ho) _{oxide, Mg x Al y (OH)} 2x + 3y + 2z (CO 3) 2 · of mH ₂ O (formula, x, y and z are 0 <y / x, respectively ≤ 1, 0 ≤ z / y <1.5, m is an integer) or Mg _p Al _q (OH) _r CO ₃ nH ₂ O (wherein 0.15 ≤ (q / p + q) ≤ 0.35, Hydrotalcite compound having the formula 1.8 ≦ (r / p + q) ≦ 2.5 and 0 ≦ n ≦ ₅ , Mg _4.5 Al ₂ (OH) ₁₃ CO ₃ · 3.5H ₂ O, Mg _4.5 Al ₂ (OH ) ₁₃ CO ₃ , Mg ₅ Al _1.5 (OH) ₁₃ CO ₃ · 3.5H ₂ O, Mg ₅ Al _1.5 (OH) ₁₃ CO ₃ , Mg ₆ Al ₂ (OH) ₁₆ CO ₃ · 4H ₂ O, Mg ₆ Al ₂ (OH) ₁₈ CO _3, In _{Mg 4.3 Al (OH) 12.6 CO} 3 · hydrotalcite-based plastic water, EDTA (ethylenediaminetetraacetic acid), PAR (4- (2-pyridylazo) resorcinol) having the formula _{nH 2 O, PDCA (pyridine-} 2,6- dicarboxylic acid), oxalic acid, ammonium acetate, ammonium nitrate, bismuth hydroxide, bisphenol A compound, triazine compound with hydroxy or vinyl groups, inorganic particles including magnesium and aluminum, inorganic particles including bismuth, antimony and bismuth It may be an inorganic particle or a combination thereof, but is not limited thereto.

The ion blocking material may be included in the metal ion blocking layer 130 in a mixed state with a matrix component. The matrix component may be, for example, a polymer compound or an inorganic compound having electrical insulation, but is not limited thereto. The electrically insulating polymer compound may be, for example, a compound such as epoxy resin, polyethylene, polypropylene, polystyrene, polybutylene, or the like. It may be a metal oxide such as the inorganic compound, silica, alumina, zirconia, titania, ceria and the like. In particular, when using the inorganic compound may further include a binder material having a bonding property such as epoxy resin.

The content of the ion blocking material may be 0.1 wt% to 20 wt% with respect to the weight of the metal ion blocking layer 130. When the content of the ion barrier material is too small, it is difficult to effectively block impurities such as ions penetrating from the outside. If the content of the ion barrier material is too high, difficulty in forming the metal ion barrier layer 130 may occur.

In particular, the distribution density of the ion blocking material may be 0.1 μg / cm ² to 100 μg / cm ² with respect to the surface of the first surface 110a on which the metal ion blocking layer 130 is formed. If the distribution density of the ion barrier material is too low, it is difficult to effectively block impurities such as ions penetrating from the outside. Too high a distribution density of the ion barrier material may cause difficulty in forming the protective layer.

The solder ball 140 may be provided on the bonding pad 120 for electrical connection with an external circuit.

In the semiconductor package 100 according to the present exemplary embodiment, since impurities such as ions penetrating from the first surface 110a are effectively blocked by the ion blocking material included in the metal ion blocking layer 130, the stability and reliability of the device may be reduced. Is high.

Hereinafter, a method of manufacturing the semiconductor package 100 described above will be described.

According to one or more exemplary embodiments, a method of manufacturing the semiconductor package 100 may include: providing a semiconductor chip having a first surface and a second surface opposite to the first surface and on which a semiconductor element is formed; Providing a bonding pad on the second side; And forming a metal ion blocking layer including an ion blocking material on the first surface.

2A through 2C are side cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 2A, a semiconductor chip 110 ′ is first provided having a first surface 110a and a second surface 110b facing the first surface 110a and having a semiconductor element formed thereon. In order to provide the semiconductor chip 110 ', the semiconductor chip 110' is obtained by first forming semiconductor elements on a wafer (not shown), dicing and individualizing them according to a known method.

Alternatively, the bonding pads 120 may be formed at appropriate positions through redistribution to obtain the semiconductor chip 110 ′, and the passivation layer 150 may be formed to expose at least a portion of the bonding pads 120. have. The passivation layer 150 may be obtained by forming a layer of silicon oxide and / or silicon nitride by high density plasma chemical vapor deposition as described above. The bonding pad 120 may be formed of metal, for example, aluminum or copper. However, it is not limited to these materials.

In addition, the semiconductor chip 110 'may be thinned by backlaping the back surface of the semiconductor chip 110'. In addition, the backlap may include a polishing step that not only reduces the thickness but also reduces the roughness of the back surface of the semiconductor chip 110 ′.

Referring to FIG. 2B, a metal ion blocking layer 130 may be formed on the first surface 110a. The metal ion barrier layer 130 may be formed by preparing a metal ion barrier layer composition in a liquid or slurry state, and then applying the metal ion barrier layer composition on the first surface 110a and curing the metal ion barrier layer composition. It may be formed by preparing an ion barrier layer tape in advance and then attaching the ion barrier layer tape on the first surface 110a.

Hereinafter, each case will be described in detail.

Method of using a metal ion barrier layer composition

The metal ion barrier layer composition may comprise a matrix and an ion barrier material. Since the ion barrier material is as described above, the type thereof is not described herein again. The matrix may be, for example, a polymer compound or an inorganic compound having electrical insulation, but is not limited thereto. The electrically insulating polymer compound may be, for example, a compound such as epoxy resin, polyethylene, polypropylene, polystyrene, polybutylene, or the like. The inorganic compound may be a metal oxide such as silica (SiO ₂ ), alumina (Al ₂ O ₃ ), zirconia (ZrO ₂ ), titania (TiO ₂ ), ceria (CeO ₂ ), or the like. In particular, when using the inorganic compound may further include a binder material having a bonding property such as epoxy resin.

Although the mixing ratio of the matrix and the ion barrier material is not particularly limited, as will be described later, the content of the ion barrier material may be adjusted to be 0.1 wt% to 20 wt% with respect to the weight of the metal ion barrier layer 130. Can be.

When an epoxy resin is used as the matrix, that is, an electrically insulating polymer compound, the epoxy resin is not particularly limited in molecular weight or molecular structure. For example, bisphenol A type epoxy resin, ortho- Cresol novolak type epoxy resin, naphthol novolak type epoxy resin, phenol aralkyl type epoxy resin, dicyclopentadiene modified phenol type epoxy resin, bi-phenyl type epoxy resin, stilbene type epoxy resin or mixtures thereof have. However, in consideration of moisture resistance and device reliability due to ions, Na ions or Cl ions are preferably minimized. For example, the epoxy equivalent is preferably 100 g / eq to 500 g / eq.

The metal ion barrier layer composition may be further blended with various additives as necessary. For example, curing catalysts such as imidazole compounds, tertiary amine compounds and phosphorus compounds, zinc molybdate-supported zinc oxide, zinc molybdate-supported talc, phosphazene compounds, flame retardants such as magnesium hydroxide and aluminum hydroxide, and thermoplastic elastomers are added. It can mix.

Also, optionally, the metal ion barrier layer composition may include a curing agent such as a phenol resin, and a curing accelerator may be used to promote the curing reaction of the curing agent. It is preferable that the said phenol resin has at least 1 or more naphthalene ring substituted or unsubstituted in 1 molecule, and the said hardening accelerator is a triphenyl phosphine, a tributyl phosphine, a tri (p-methylphenyl) phos, for example. Pin, tri (nonylphenyl) phosphine, triphenylborane, tetraphenylphosphine, tetraphenylborate, triethylamine, benzyldimethylamine, α-methylbenzyldimethylamine, 2-methylimidazole, 2-phenylimida Sol, 2-phenyl-4-methylimidazole, and the like.

The method of forming the metal ion barrier layer composition on the first surface 110a may use a known method, for example, a method such as a doctor blade.

How to use metal ion barrier layer tape

The metal ion barrier layer tape may be prepared by sequentially forming the metal ion barrier layer composition and the adhesive layer described above on a tape substrate, and forming a release agent thereon and forming a protective tape thereon. That is, when the metal ion barrier layer 130 is to be formed, the protective tape is first removed. At this time, the release agent is removed together with the protective tape. Thereafter, the metal ion barrier layer 130 may be formed by attaching the exposed adhesive layer to the first surface 110a.

As said tape base material, well-known polymer films, such as polyethylene and a polypropylene, can be used. As a mold release agent, a well-known well-known thing can be used, For example, a higher fatty acid, a higher fatty metal salt, ester type expansion, a polyethylene wax, etc. are mentioned, These may be used individually by 1 type, and may use 2 or more types together You may.

The content of the ion blocking material may be adjusted to be 0.1 wt% to 20 wt% with respect to the weight of the metal ion blocking layer 130. When the content of the ion barrier material is too small, it is difficult to effectively block impurities such as ions penetrating from the outside. Too much content of the ion barrier material may cause difficulty in forming the metal ion barrier layer.

In particular, the distribution density of the ion barrier material may be adjusted to be 0.1 μg / cm ² to 100 μg / cm ² with respect to the surface of the first surface 110a on which the metal ion barrier layer is formed. If the distribution density of the ion barrier material is too low, it is difficult to effectively block impurities such as ions penetrating from the outside. If the distribution density of the ion barrier material is too high, difficulty in forming the metal ion barrier layer may occur.

Referring to FIG. 2C, after forming the metal ion blocking layer 130, the solder ball 140 may be formed on the bonding pad 120 by a known method. The bonding pad 120 may be made of aluminum or copper as described above. Optionally, the solder ball 140 may be easily adhered to the bonding pad 120, and a component of the solder ball 140 may be bonded to the bonding pad 120. An under bump metallization (UBM) layer may be further provided on the bonding pad 120 to prevent diffusion to the 120.

The semiconductor package according to the exemplary embodiment of the present invention may be manufactured by the method described above.

Another embodiment of the present invention provides a semiconductor package module including the semiconductor package. 3A is a side cross-sectional view of a semiconductor package module 200 according to another embodiment of the present invention.

Referring to FIG. 3A, a first semiconductor package 100 having a first size is mounted on a substrate 210 having a connection terminal 220. The first semiconductor package 100 may be the semiconductor package described above, and the substrate 210 may be, for example, a printed circuit board. Optionally, the substrate 210 may be a system-in-package (SIP) frame. The first semiconductor package 100 may be connected to the substrate 210 by directly connecting the solder ball 140 to the substrate 210.

3B illustrates a cross-sectional side view of a semiconductor package module 300 in accordance with another embodiment of the present invention.

Referring to FIG. 3B, the semiconductor package module 300 includes a first semiconductor package having a first size on the substrate 210. In addition, the semiconductor package module 300 may include a second semiconductor package having a second size larger than the first size on the first semiconductor package.

The second semiconductor package has a first surface 310a and a second surface 310b facing the first surface 310a and having a semiconductor element formed thereon, the semiconductor chip 310 having a second size and the second surface. While exposing at least a portion of the bonding pad 320 provided on the second surface 310b, the metal ion blocking layer 330 provided on the first surface 310a and including an ion blocking material, and the bonding pad 320. A passivation layer 350 covering the second surface 310b and a solder ball 340 provided on the bonding pad 320 may be included.

By constructing the semiconductor module packages 200 and 300 according to the embodiment of the present invention, it is possible to obtain a semiconductor module package that is robust and reliable against the penetration of impurities such as ions from the outside.

Another embodiment of the present invention is a semiconductor chip comprising a first surface and a second surface opposite to the first surface and on which a semiconductor element is formed; A bonding pad provided on the second surface; A semiconductor package is provided on the first surface, and includes a metal ion blocking layer capable of blocking the transfer of metal through the first surface. The semiconductor package may include a semiconductor chip mounting unit; And a lead frame electrically connected to the bonding pad, wherein the semiconductor chip may be seated on the semiconductor chip mounting part with the metal ion blocking layer interposed therebetween.

4 is a side cross-sectional view of a semiconductor package 400 according to another embodiment of the present invention. Referring to FIG. 4, a semiconductor chip 410 having a first surface 410a and a second surface 410b opposite to the first surface 410a is mounted on the semiconductor chip mounting part 460. Semiconductor devices such as transistors may be formed on the second surface 410b. In particular, a metal ion blocking layer 430 may be located between the semiconductor chip mounting part 460 and the semiconductor chip 410.

The semiconductor package 400 of the embodiment shown in FIG. 4 may be a chip scale package (CSP).

The semiconductor chip mounting part 460 may be an alloy of Fe / Ni or copper. In particular, the semiconductor chip mounting part 460 may be copper. Optionally, a nickel layer may be formed on the surface of the semiconductor chip mounting part 460. The nickel layer may have a thickness of about 2 μm to about 20 μm. The nickel layer has an effect of preventing copper ions from penetrating into the semiconductor chip 410 when the semiconductor chip mounting part 460 is copper. Therefore, when the thickness of the nickel layer is excessively small, the effect of preventing metal ions including copper from penetrating into the semiconductor chip 410 may be insufficient. In addition, when the thickness of the nickel layer is too thick, the metal ion permeation blocking effect due to the nickel layer is saturated, which may be economically disadvantageous.

As the method of forming the nickel layer on the semiconductor chip mounting portion 460, for example, a method such as plating may be used, but is not limited thereto. The nickel layer may be formed on both surfaces of the semiconductor chip mounting part 460. Alternatively, the nickel layer may be formed in contact with the metal ion blocking layer 430 on the surface of the semiconductor chip mounting part 460. It can be formed on the surface. Alternatively, the nickel layer may be formed on at least the surface of the portion where the semiconductor chip mounting part 460 contacts the metal ion blocking layer 430.

In addition, the metal ion blocking layer 430 provided between the semiconductor chip 410 and the semiconductor chip mounting part 460 is a layer of a material capable of blocking or inhibiting the passage of metal ions. It may include a substance. In particular, the metal ion blocking layer 430 may be a polymer resin composition including an amine group (-NH ₂ ). The polymer resin composition may be an epoxy resin. In particular, the amine group may be bonded to the main chain of the epoxy resin.

In addition, an adhesive layer 435 may be further provided between the metal ion blocking layer 430 and the semiconductor chip mounting part 460.

The adhesive layer 435 may be used alone or a combination of a thermoplastic resin and a thermosetting resin.

Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polybutadiene resin, polycarbonate resin, thermoplastic polyimide resin, 6 Polyamide resins such as nylon and 6,6-nylon, phenoxy resins, acrylic resins, saturated polyester resins such as PET and PBT, polyamideimide resins and fluorine resins. These thermoplastic resins may be used alone or in combination of two or more thereof. In particular, the adhesive layer 435 may include an acrylic resin having little ionic impurities, excellent heat resistance, and securing reliability of a semiconductor device as the thermoplastic resin.

The acrylic resin is not particularly limited as long as it is a polymer polymerized from a monomer having a structure of R- (CO) -CH = CH ₂ , but it is (meth) acrylic acid having a straight or branched alkyl group having 30 or less carbon atoms, especially 4 to 18 carbon atoms. It may be a polymer containing one or two or more of the components. For example, the acrylic resin may be an acid such as a carboxyl group-containing monomer such as acrylic acid, methacrylic acid, carboxyethyl acrylate, carboxypentyl acrylate, itaconic acid, maleic acid, fumaric acid or crotonic acid, maleic anhydride or itaconic anhydride. Hydroxy group-containing monomers such as anhydride monomers, 2-hydroxyethyl (meth) acrylic acid, 2-hydroxypropyl (meth) acrylic acid, 4-hydroxybutyl (meth) acrylic acid, and the like, styrene sulfonic acid, allylsulfonic acid, 2- (meth) acrylic acid Sulfonic acid-containing monomers such as amide-2-methylpropanesulfonic acid, (meth) acrylamidepropanesulfonic acid, sulfopropyl (meth) acrylate or (meth) acryloyloxynaphthalenesulfonic acid or the like or 2-hydroxyethylacryloyl phosphate A phosphoric acid group containing monomer is mentioned.

A phenol resin, an amino resin, an unsaturated polyester resin, an epoxy resin, a polyurethane resin, a silicone resin, a thermosetting polyimide resin etc. are mentioned as said thermosetting resin. These resin can be used individually or in combination of 2 or more types. In particular, the thermosetting resin may be a phenol resin.

The semiconductor package 400 may be sealed by a molding resin 470. The molding resin 470 may be any molding material known in the art, and may be, for example, an epoxy molding compound (EMC).

The bonding pad 420 may be electrically connected to the lead 440 exposed to the outside of the molding resin 470 through the wire 442.

5 is a side cross-sectional view of a semiconductor package 500 according to another embodiment of the present invention. Referring to FIG. 5, the first semiconductor chip 510a and the second semiconductor chip 510b are mounted on the upper and lower surfaces of the semiconductor chip mounting unit 560, respectively. Bonding pads 520a and 520b may be formed on surfaces of the first semiconductor chip 510a and the second semiconductor chip 510b, respectively. The first side of the bonding pads 520a and 520b may be formed. Semiconductor devices may be formed on the surfaces of the semiconductor chip 510a and the second semiconductor chip 510b. In addition, metal ion blocking layers 530a and 530b may be formed between the semiconductor chip mounting unit 560, the first semiconductor chip 510a, and the second semiconductor chip 510b, respectively.

The semiconductor package 500 of the embodiment shown in FIG. 5 may be a flat package (FP) or a quad flat package (QFP).

As described above, the semiconductor chip mounting part 560 may be an alloy of Fe / Ni, copper, or the like, and particularly, copper. In addition, nickel layers 564a and 564b may be formed on upper and lower surfaces of the semiconductor chip mounting part 560.

In addition, the metal ion blocking layer 530 provided between the first semiconductor chip 510a and the second semiconductor chip 510b and the semiconductor chip mounting part 560 may be formed of a material capable of inhibiting or blocking the passage of metal ions. As a layer, it is as above-mentioned and detailed description is abbreviate | omitted here.

In addition, an adhesive layer (not shown) may be further provided between the metal ion blocking layers 530a and 530b and the semiconductor chip mounting part 560.

As shown in FIG. 5, the leads 540 of the semiconductor package 500 may include nickel layers 544a and 544b formed on the core leads 542. In particular, the thicknesses of the nickel layers 544a and 544b formed on the core lead 542 may be substantially the same as the thicknesses of the nickel layers 564a and 564b formed on the semiconductor chip mounting part 560.

The semiconductor package 500 may be sealed by a molding resin 570. The molding resin 570 may be any molding material known in the art, and may be, for example, an epoxy molding compound (EMC).

The bonding pads 520a and 520b may be electrically connected to the lead 540 exposed to the outside of the molding resin 570 through a wire 542.

As described above, in the semiconductor package 500, metal ion blocking units 530a and 530b are formed between the semiconductor chips 510a and 510b and the semiconductor chip mounting unit 560, and the semiconductor chip mounting unit 560 is formed. Nickel layers 564a and 564b are formed on the upper surface and the lower surface of the bottom surface) and the metal ions and / or the metal ions due to the unique effects of the metal ion blocking portions 530a and 530b and the nickel layers 564a and 564b. Alternatively, moisture may be effectively blocked from penetrating into the semiconductor chip.

Hereinafter, the configuration and effects of the present invention will be described in more detail with specific experimental examples and comparative examples, but these experimental examples are only intended to more clearly understand the present invention and are not intended to limit the scope of the present invention.

Comparative Example 1

A semiconductor chip was formed on a semiconductor chip mounting part made of copper. At this time, a polymer resin layer polymerized with glycidyl ether was formed between the semiconductor chip mounting portion and the semiconductor chip. Then, the semiconductor package was sealed with EMC to manufacture 96 CSP-type semiconductor packages.

Experimental Example 1

A semiconductor chip was formed on a semiconductor chip mounting portion made of copper having a nickel layer having a thickness of 4 μm on its surface. At this time, an epoxy polymer resin layer having an amine group (—NH ₂ ) bonded to a main chain was formed between the semiconductor chip mounting part and the semiconductor chip. The epoxy polymer resins are commercially available, which will be apparent to those skilled in the art. Then, the semiconductor package was sealed with EMC to manufacture 96 CSP-type semiconductor packages.

For Experimental Example 1 and Comparative Example 1, the experiment was performed on whether the charge was lost and whether the semiconductor chip and the semiconductor chip mounting portion were peeled off, and the results are summarized in Table 1 below. In the experiment, after the data was written to the semiconductor chip, the semiconductor chip was left at 85% relative humidity and 85 ° C. for 24 hours, and then subjected to three IR reflows to determine whether the data was maintained or not. This was done by checking whether it occurred.

TABLE 1

% Charge loss rate Peeling failure rate Experimental Example 1 0 0 Comparative Example 1 96 43

Accordingly, it can be seen that the semiconductor package according to the embodiment of the present invention can greatly reduce the charge loss due to copper ions and the peeling due to moisture absorption.

Although described in detail with respect to preferred embodiments of the present invention as described above, those of ordinary skill in the art, without departing from the spirit and scope of the invention as defined in the appended claims Various modifications may be made to the invention. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

As described above, the present invention is useful in the semiconductor package field in the semiconductor manufacturing industry.

1 is a side cross-sectional view of a semiconductor package according to an embodiment of the present invention.

2A to 2C are side cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

3A and 3B are side cross-sectional views illustrating semiconductor package modules according to embodiments of the present invention, respectively.

4 is a side cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

5 is a side cross-sectional view of a semiconductor package according to still another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 110 ', 310, 410, 510: semiconductor chip

110a, 310a, 410a: first side 110b, 310b, 410b: second side

120, 320, 420, 520a, 520b: bonding pads

130, 330, 430, 530a, 530b: metal ion barrier layer

140, 340: solder balls 150, 350: passivation layer

210: substrate 220, 222: connection terminal

435: adhesive layers 470, 570: sealing material

540: lead 544a, 544b, 564a, 564b: nickel layer

560: semiconductor chip mounting portion

Claims (11)

A semiconductor chip having a first surface and a second surface facing the first surface and on which a semiconductor element is formed; A bonding pad provided on the second surface; And A metal ion blocking layer provided on the first surface and capable of blocking the transfer of metal through the first surface; Semiconductor package comprising a. The method of claim 1, A passivation layer on the second surface, the passivation layer exposing the bonding pads; And A solder ball provided on the bonding pads; The semiconductor package further comprises. The method of claim 2, The semiconductor package is a semiconductor package, characterized in that the wafer level package (WLP: wafer level package). The method of claim 1, A semiconductor chip mounting unit; And A lead frame electrically connected to the bonding pads; And a semiconductor chip mounted on the semiconductor chip mounting part with the metal ion blocking layer interposed therebetween. The method of claim 4, wherein And the semiconductor chip mounting portion is made of copper. The method of claim 5, wherein And a nickel layer is formed on a surface of the semiconductor chip mounting portion at a portion where the semiconductor chip mounting portion contacts the metal ion blocking layer. The method of claim 6, The semiconductor package, characterized in that the metal ion barrier layer is a polymer resin composition containing an amine group. The method of claim 7, wherein The thickness of the nickel layer is a semiconductor package, characterized in that 2 to 20 ㎛. The method according to claim 7 or 8, The polymer resin composition is a semiconductor package comprising an epoxy resin containing an amine group (-NH ₂ ). The method of claim 9, And a bonding layer between the metal ion blocking layer and the semiconductor chip mounting portion. The method of claim 10, The metal ion barrier layer is an amine group (-NH ₂ ) is bonded to the main chain of the epoxy resin, A semiconductor package, characterized in that the adhesive layer comprises an acrylic resin.

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