JPH06151502A - Mounting method for flip chip of semiconductor element - Google Patents

Mounting method for flip chip of semiconductor element

Info

Publication number
JPH06151502A
JPH06151502A JP29719492A JP29719492A JPH06151502A JP H06151502 A JPH06151502 A JP H06151502A JP 29719492 A JP29719492 A JP 29719492A JP 29719492 A JP29719492 A JP 29719492A JP H06151502 A JPH06151502 A JP H06151502A
Authority
JP
Japan
Prior art keywords
semiconductor element
resin
electrode
substrate
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29719492A
Other languages
Japanese (ja)
Inventor
Keiichiro Hayashi
恵一郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP29719492A priority Critical patent/JPH06151502A/en
Publication of JPH06151502A publication Critical patent/JPH06151502A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Abstract

PURPOSE:To put a bump electrode and a base electrode in continuity by a method wherein uncured resin is formed on a bump electrode part of a semiconductor element, the bump electrode is pressed on the base electrode and the resin is melted by heating and then cooled to be cured. CONSTITUTION:An electrode 1a is formed on a semiconductor element 1 by Al evaporation, a passivation film 3 of Si3N4 is formed on a part other than a place at which connection is made with a base 6 and an Au bump electrode 2 is formed on the electrode 1a by a plating method. Thermoplastic resin of epoxy is heated and applied for coating on the bump electrode 2. The bump electrode 2 is aligned in position with a base electrode 7, pressed thereon and heated so that the two electrodes be put in continuity, and the peripheries thereof are covered with cured resin 5a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子のフリップ
チップ実装方法に関するものです。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip mounting method for semiconductor devices.

【0002】[0002]

【従来の技術】従来の半導体素子のフリップチップ実装
方法の工程断面図を図2に示す。まず、図2(a)に示
すように、半導体素子21にはPb−Sn系のはんだバ
ンプ22を形成しておく。また基板23には基板電極2
4を形成し、はんだバンプ22を接続する個所以外に
は、はんだの流れ防止のために、はんだの流れない膜
(例えば、SiO2 、Si3 4 、Cr等)を、はんだ
ダム25として形成し、接続を行う個所には予備はんだ
26を形成しておく。
2. Description of the Related Art FIG. 2 is a sectional view showing steps in a conventional semiconductor chip flip-chip mounting method. First, as shown in FIG. 2A, Pb—Sn based solder bumps 22 are formed on the semiconductor element 21. Further, the substrate electrode 2 is provided on the substrate 23.
4 is formed, and a film (for example, SiO 2 , Si 3 N 4 , Cr, or the like) that does not flow solder is formed as the solder dam 25 in order to prevent the flow of solder, except for the places where the solder bumps 22 are connected. Then, the pre-solder 26 is formed at the connection point.

【0003】そして、これらの半導体素子21を基板2
3が所定の位置となるようにアライメントを行う。次い
で、半導体素子21のはんだバンプ22を基板23の予
備はんだ26に突き合わせ、それらが溶融するように融
点より高い温度(Pb−Sn共晶で210〜230℃)
で加熱を行い、図2(b)に示すように、半導体素子2
1上のはんだバンプ22と基板電極24上の予備はんだ
26を融合させ両者の接続を完了する。
The semiconductor element 21 is mounted on the substrate 2
Alignment is performed so that 3 becomes a predetermined position. Next, the solder bumps 22 of the semiconductor element 21 are butted against the preliminary solder 26 of the substrate 23, and a temperature higher than the melting point (210 to 230 ° C. in Pb—Sn eutectic) so that they are melted.
The semiconductor element 2 is heated as shown in FIG.
The solder bump 22 on 1 and the preliminary solder 26 on the substrate electrode 24 are fused to complete the connection between the two.

【0004】[0004]

【発明が解決しようとする課題】以上述べたように、フ
リップチップ接続は一度で全電極の接続ができ、高密度
接続が可能であるという特徴を有しているが、加熱を必
要とするために、使用する基板材料が耐熱性の点で限定
され、LCDディスプレイ等へ直接チップ実装するのが
困難であるという課題を有していた。
As described above, the flip-chip connection has a feature that all electrodes can be connected at once and high-density connection is possible, but since it requires heating. In addition, there is a problem that the substrate material used is limited in heat resistance and it is difficult to directly mount the chip on an LCD display or the like.

【0005】本発明は、上記課題を除去し、量産性に富
み、耐熱性の低い基板材料へも半導体素子を接続できる
半導体素子のフリップチップ実装方法を提供するもので
ある。
The present invention eliminates the above-mentioned problems and provides a flip chip mounting method of a semiconductor device, which has high mass productivity and can be connected to a substrate material having low heat resistance.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するために、基板へ半導体素子をフリップチップ実装
する半導体素子の実装方法において、半導体素子のバン
プ電極部に選択的に未硬化の樹脂を形成した後、前記半
導体素子を基板上に押圧して前記バンプを基板電極に圧
接した状態で該樹脂を硬化させるようにしたものであ
る。
In order to achieve the above object, the present invention provides a semiconductor element mounting method for flip-chip mounting a semiconductor element on a substrate, wherein a bump electrode portion of the semiconductor element is selectively uncured. After the resin is formed, the semiconductor element is pressed onto the substrate to cure the resin in a state where the bumps are pressed against the substrate electrodes.

【0007】[0007]

【作用】本発明によれば、上記したように半導体素子の
バンプ電極部に選択的に未硬化の樹脂をコーティングさ
せる。その後、前記半導体素子を基板の所定の位置に位
置合わせを行い、低温またはUVで硬化する樹脂を介在
させ、半導体素子を基板に押圧し、樹脂を硬化させ、バ
ンプ電極と基板電極を接続させ導通する。
According to the present invention, the uncured resin is selectively coated on the bump electrode portion of the semiconductor element as described above. After that, the semiconductor element is aligned with a predetermined position of the substrate, a resin that cures at a low temperature or UV is interposed, the semiconductor element is pressed against the substrate, the resin is cured, and the bump electrode and the substrate electrode are connected to each other for conduction. To do.

【0008】[0008]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は、本発明の実施例を示す
半導体素子の実装工程断面図である。まず、図1(a)
に示すように、半導体素子1にはAl蒸着により電極1
aを形成しておき、基板6と接続を行う個所以外にはS
3 4 によるパッシベーション膜3を形成しておき、
メッキ法により電極1a上にAuバンプ電極2を形成し
ておく。図1(a)の工程は図示とは異なるがウェハ状
態にて従来技術で製造する。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a semiconductor element mounting process showing an embodiment of the present invention. First, FIG. 1 (a)
As shown in FIG.
a is formed in advance, and S
The passivation film 3 made of i 3 N 4 is formed in advance,
The Au bump electrode 2 is formed on the electrode 1a by the plating method. Although the process of FIG. 1A is different from that shown in the drawing, it is manufactured by a conventional technique in a wafer state.

【0009】次に、図1(b)に示すように、ウェハ状
態の半導体素子1上のバンプ電極2部が開口しているガ
ラスマスク4を用いて、バンプ電極2の開口部上のみ樹
脂5をコーティングする。本実施例では、エポキシ系熱
可塑性樹脂を180℃程度に加熱し、液状にしてガラス
マスク4上方より吹きつける。または、図示しないがス
クリーン印刷によって、バンプ電極2の高さと同程度の
厚さに塗布し、硬化させる方法でも可能である。つま
り、塗布した熱可塑性樹脂が常温に戻り、硬化した樹脂
5aを形成する。熱可塑性樹脂としては上記以外にもア
クリル樹脂、シリコン系樹脂等の高分子重合体が使用可
能である。
Next, as shown in FIG. 1B, using a glass mask 4 having an opening in the bump electrode 2 portion on the semiconductor element 1 in a wafer state, resin 5 is provided only on the opening portion of the bump electrode 2. Coating. In this embodiment, the epoxy-based thermoplastic resin is heated to about 180 ° C., liquefied, and sprayed from above the glass mask 4. Alternatively, although not shown, it is also possible to apply by screen printing to a thickness approximately equal to the height of the bump electrodes 2 and cure. That is, the applied thermoplastic resin returns to room temperature and forms the cured resin 5a. As the thermoplastic resin, a polymer such as an acrylic resin or a silicone resin can be used in addition to the above.

【0010】次に、図示しないがチップ間のグリッドラ
インに沿って、ダイシングソーを用いて個別の半導体素
子1にチップ化する。次に、図1(c)に示すように、
半導体素子1のバンプ電極2が基板6上の基板電極7と
接続できるように位置合わせを行う。また、基板6には
ガラス基板を用い、基板電極7にはITO(Indiu
m Tin Oxide)を用いた。そして、図1
(d)に示すように半導体素子1を基板6に押圧し、バ
ンプ電極2を基板電極7に押圧した状態で、加熱を行い
樹脂5を溶融する。これにより、バンプ電極2の端面と
基板電極7との間の樹脂5はなくなり、半導体素子1の
バンプ電極2と基板電極7は接続導通する。
Next, although not shown, individual semiconductor elements 1 are made into chips along a grid line between chips by using a dicing saw. Next, as shown in FIG.
The bump electrodes 2 of the semiconductor element 1 are aligned so that they can be connected to the substrate electrodes 7 on the substrate 6. A glass substrate is used for the substrate 6, and ITO (Indium) is used for the substrate electrode 7.
m Tin Oxide) was used. And FIG.
As shown in (d), the semiconductor element 1 is pressed against the substrate 6 and the bump electrode 2 is pressed against the substrate electrode 7, and heating is performed to melt the resin 5. As a result, the resin 5 between the end surface of the bump electrode 2 and the substrate electrode 7 disappears, and the bump electrode 2 of the semiconductor element 1 and the substrate electrode 7 are connected and conducted.

【0011】この状態でエアを吹きつけ、冷却を行い半
導体素子1を基板6上に固着し、硬化した樹脂5aでバ
ンプ電極2と基板電極7の周囲を被覆するよう形成す
る。なお、上記実施例では、エポキシ系熱可塑性樹脂5
を加熱、溶融させ、バンプ電極2に塗布し、硬化させた
が樹脂としては、導電性か、非導電性または異方性導電
性樹脂でもよい。また、主剤と硬化剤が混合されていて
加熱することによって反応する熱硬化性の樹脂を用いて
もい。また、紫外線硬化性樹脂を用いてもよい。また、
バンプ電極2もAuに限定するものではなく、Cu,C
r等導電性がありメッキで形成できる金属であればよ
い。ただし、使用するバンプ電極2は、径の揃っている
ものが望ましく、また接続での導電信頼性を得るために
はバンプ電極2が弾性変形するか、固着する樹脂5に弾
性を有するようにする必要がある。更に、基板6もガラ
スに限定されるものでなく、ガラス基板、金属基板、樹
脂基板など全般に使用可能できる。
In this state, air is blown and cooling is performed to fix the semiconductor element 1 on the substrate 6, and the cured resin 5a is formed so as to cover the bump electrodes 2 and the substrate electrodes 7. In the above example, the epoxy-based thermoplastic resin 5
Was heated and melted, applied to the bump electrode 2 and cured, but the resin may be a conductive, non-conductive or anisotropic conductive resin. Alternatively, a thermosetting resin which is a mixture of a main agent and a curing agent and which reacts when heated may be used. Alternatively, an ultraviolet curable resin may be used. Also,
The bump electrode 2 is not limited to Au, but Cu, C
Any metal having conductivity such as r and capable of being formed by plating may be used. However, it is desirable that the bump electrodes 2 to be used have uniform diameters, and that the bump electrodes 2 are elastically deformed or the resin 5 to which they are adhered has elasticity in order to obtain conductive reliability in connection. There is a need. Further, the substrate 6 is not limited to glass, and can be used for glass substrates, metal substrates, resin substrates and the like.

【0012】[0012]

【発明の効果】以上、詳細に説明したように、本発明に
よれば次のような効果を奏することができる。 半導体素子のバンプ電極部に選択的に未硬化の樹脂を
形成してあるので、カメラによる位置認識が容易にで
き、基板への樹脂塗布工程及び樹脂塗布により搭載位置
が確認しずらくなることによる位置合わせ時間の増大が
削除でき、製造コストを安価にできる。
As described in detail above, according to the present invention, the following effects can be obtained. Since the uncured resin is selectively formed on the bump electrode part of the semiconductor element, the position can be easily recognized by the camera, and it becomes difficult to confirm the mounting position by the resin coating process on the substrate and the resin coating. The increase in the alignment time can be eliminated, and the manufacturing cost can be reduced.

【0013】基板上に接続する際に、低温で硬化する
樹脂を用いて半導体素子の固着及び電極間の接続ができ
るので、耐熱性の低い基板材料上への半導体素子のフリ
ップチップ実装を行うことができる。
Since the semiconductor element can be fixed and the electrodes can be connected to each other by using a resin which is hardened at a low temperature when connecting to the substrate, flip chip mounting of the semiconductor element on the substrate material having low heat resistance is required. You can

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す半導体素子の実装工程断
面図である。
FIG. 1 is a sectional view of a semiconductor element mounting process showing an embodiment of the present invention.

【図2】従来の半導体素子の実装工程断面図である。FIG. 2 is a sectional view of a conventional semiconductor element mounting process.

【符号の説明】[Explanation of symbols]

1、21 半導体素子 2 バンプ電極 3 パッシベーション膜 4 ガラスマスク 5 樹脂 5a 硬化した樹脂 6、23 基板 7、24 基板電極 22 はんだバンプ 25 はんだダム 26 予備はんだ 1, 21 Semiconductor element 2 Bump electrode 3 Passivation film 4 Glass mask 5 Resin 5a Cured resin 6, 23 Substrate 7, 24 Substrate electrode 22 Solder bump 25 Solder dam 26 Pre-solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基板へ半導体素子をフリップチップ実装
する半導体素子の実装方法において、半導体素子のバン
プ電極部に選択的に未硬化の樹脂を形成した後、前記半
導体素子を基板上に押圧して前記バンプ電極を基板電極
に圧接した状態で該樹脂を硬化させることを特徴とする
半導体素子のフリップチップ実装方法。
1. A semiconductor element mounting method for flip-chip mounting a semiconductor element on a substrate, wherein uncured resin is selectively formed on bump electrode portions of the semiconductor element, and then the semiconductor element is pressed onto the substrate. A flip-chip mounting method for a semiconductor device, characterized in that the resin is cured while the bump electrode is pressed against the substrate electrode.
JP29719492A 1992-11-06 1992-11-06 Mounting method for flip chip of semiconductor element Pending JPH06151502A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29719492A JPH06151502A (en) 1992-11-06 1992-11-06 Mounting method for flip chip of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29719492A JPH06151502A (en) 1992-11-06 1992-11-06 Mounting method for flip chip of semiconductor element

Publications (1)

Publication Number Publication Date
JPH06151502A true JPH06151502A (en) 1994-05-31

Family

ID=17843402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29719492A Pending JPH06151502A (en) 1992-11-06 1992-11-06 Mounting method for flip chip of semiconductor element

Country Status (1)

Country Link
JP (1) JPH06151502A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013080899A (en) * 2011-10-04 2013-05-02 ▲き▼邦科技股▲分▼有限公司 Semiconductor device and semiconductor package using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013080899A (en) * 2011-10-04 2013-05-02 ▲き▼邦科技股▲分▼有限公司 Semiconductor device and semiconductor package using the same

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