JP2000260811A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce stress on a solder or a conductive adhesive as connection point in which stress concentrates in flip chip mounting by providing matrix- shaped slits, or slits perpendicular to the long side of a semiconductor chip on the rear surface of the semiconductor chip and following a warp of a printed wiring board. SOLUTION: The thermal expansion coefficient of a semiconductor chip 2 is about 2.42×10-6 and the thermal expansion coefficient of a printed wiring board is about 1.5×10-5. When the semiconductor chip 2 and the printed wiring board are subjected to a temperature cycling test after the semiconductor chip 2 is flip-chip mounted to the printed wiring board and both are electrically and mechanically connected, thermal stress on the semiconductor chip 2 occurs due to a difference between the thermal expansion coefficients, the stress concentrates in a melted solder bump of a connection point between the printed wiring board and the semiconductor chip, and the melted solder bump is easy to produce cracks. By providing matrix shaped slits 24 on the rear surface of the semiconductor chip, the semiconductor chip 2 follows a warp of the printed wiring board, and the stress is dispersed so as to reduce and relax concentration of the stress.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip face-down bonding mounting structure, and more particularly to a structure of a semiconductor chip for preventing peeling of a connection portion due to warpage of a substrate after face-down bonding.

[0002]

2. Description of the Related Art In recent years, with the diversification of high-density mounting of semiconductor chips, the size of semiconductor chips has been increased, or
The dimensional aspect ratio of the chip is diversified. As a typical example, a first conventional technique will be described by way of flip-chip mounting, and a second conventional technique will be described by taking a conventional technique of COG paste mounting as an example.

A first prior art flip chip will be described with reference to FIGS. FIG. 6 shows a structure of a semiconductor chip in which solder bumps are formed on electrodes of the semiconductor chip. The semiconductor chip 2 is covered with an insulating film 6 such as a silicon nitride film except for the electrodes 12, and is electrically insulated from the outside. A common electrode film 14 which is also a barrier metal layer is formed on the electrode 12 of the semiconductor chip 2 by using a vacuum deposition method or a sputtering method, and a protruding electrode 18 such as copper is formed on the common electrode film 14 by a plating method. Thereafter, solder is deposited by using a plating method, a vacuum evaporation method using a mask, or the like, and then heated at a temperature higher than the melting point temperature of the solder of about 220 ° C. to form a spherical copper core solder bump 20.

Thereafter, as shown in FIG. 7, a flux 2 for cleaning an oxide film on the surface of the copper core solder bump 20 is formed on the tip of the copper core solder bump 20 formed on the semiconductor chip 2.
2 is supplied using a transfer method or the like.

On the other hand, a wiring pattern is arranged on the circuit board 10 of FIG. 8, and mounting pads 8 are formed at positions corresponding to the arrangement of the copper core solder bumps 20 formed on the semiconductor chip 2. The semiconductor chip 2 is aligned with the arrangement of the mounting pads 8 formed on the circuit board 10 and aligned.
Is temporarily fixed on the circuit board 10.

Thereafter, as shown in FIG. 9, the melting point temperature of the copper core solder bump 20 is set to 220 ° C. using a heating device such as a reflow furnace.
Heat at a higher temperature to melt the copper core solder bumps 20. The connection between the protruding electrode 18 of the semiconductor chip 2 and the mounting pad 8 of the circuit board 10 is performed by the melted solder bump 20.

Then, a circuit board 10 on which the semiconductor chip 2 is mounted using a solvent or the like to remove a flux residue remaining around the solder bump 20 which has been melt-connected and between the circuit board 10 and the semiconductor chip 2. Is washed, a sealing resin 26 is injected between the semiconductor chip 2 and the circuit board 10 and cured to form a semiconductor device.

[0008] The second prior art is applied to a liquid crystal display device mounting CO.
The G paste mounting will be described with reference to FIGS.

As a conventional technique, a chip-on-glass (COG) paste mounting in which a peripheral portion of a glass substrate constituting a liquid crystal display device is expanded and a plurality of semiconductor chips for driving the liquid crystal display device are mounted in the expanded region. There is.

As shown in FIG. 13, two glass substrates 2
8, a liquid crystal 42 is sealed in the ridge of the glass substrate 2, and the glass substrate 2 of the liquid crystal display 38 made of a sealing material 40 formed by a printing method or the like.
At the same time as forming a pixel pattern with a transparent electrode 46 such as indium tin oxide (hereinafter referred to as ITO) formed on the substrate 8 by using a vacuum evaporation method or a sputtering method, the peripheral portion of the glass substrate 28 is expanded. A transparent electrode 46 made of ITO or the like is routed in the extended area, and a plurality of semiconductor chips 2 for driving the projection electrodes and the liquid crystal display device 38 are mounted on the semiconductor chip 2. As shown in FIG. 10, the semiconductor chip 2 has a silicon nitride film (Si
N) and is electrically insulated from the outside. A common electrode film 14 which is also a barrier metal layer is formed on the electrode 12 of the semiconductor chip 2 by using a vacuum evaporation method or a sputtering method, and a protruding electrode such as copper is formed on the common electrode film 14 by a plating method. And gold are deposited by a plating method to form a mushroom-like or prismatic protruding electrode 4.
To form

As shown in FIG. 11, an epoxy conductive adhesive 44 in which conductive particles such as Ag and Ag / Pd are mixed into the protruding electrodes 4 on the semiconductor chip 2 by using a transfer method or the like.
Apply, then face down bonding,
Make electrical and mechanical connections. Recently, liquid crystal display devices 3
With the narrower frame of 8, the distance from the seal portion 40 to the end of the glass substrate 28 on the semiconductor chip mounting side is becoming very narrow, and the semiconductor chip 2 tends to be elongated.

As shown in FIG. 12, the conductive adhesive 44
Usually uses an epoxy adhesive, so curing is 80
Thermal curing is performed at about 120 ° C. to 120 ° C., and the transparent electrode 46 on the glass substrate 28 and the protruding electrode 4 on the semiconductor chip 2 are bonded and electrically and mechanically connected.

[0013]

As shown in FIG. 9, in the first prior art, the protruding electrode 18 made of copper or the like formed on the electrode 12 of the semiconductor chip 2 has a higher melting point and a better solder wettability. Metal is the core and solder 2 after melting at the time of connection
The electrical connection of 0, the amount of crushing, and the gap between the circuit board and the semiconductor chip are adjusted. However, since the solder is more flexible, the solder bump 20 after melting is less than the bump 18 made of copper or the like.
Stress tends to concentrate on

Here, assuming that the chip size of the semiconductor chip 2 is 15 mm both vertically and horizontally, the coefficient of thermal expansion of the semiconductor chip is about 2.42 × 10 −6 and the coefficient of thermal expansion of the circuit board 10 is 1.5 × since 10 about ^-5, after flip-chip bonding connects the semiconductor chip 2 and the circuit board 10, a temperature cycle test example, when charged into the heat cycle test performed alternately -45 ° C. and 125 ° C., the circuit board 10 is 1.5 × 10 ⁻⁵ × (125 − (− 45))
× (15 ÷ 2) = expansion and contraction of about 19 μm.

Further, the coefficient of thermal expansion of the semiconductor chip 2 is 2.42 × 10−6 × (125 − (− 45)) ×
Since (15 ÷ 2) = expansion / shrinkage of about 3 μm occurs, the maximum stress applied to the circuit board 10 and the semiconductor chip 2 is 19
μm−3 μm = approximately 16 μm. This stress tends to concentrate on the solder bump 20 after melting, which is a connection point between the circuit board 10 and the semiconductor chip 2.

The intrinsic stress generated in the circuit board 10 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the thickness of the semiconductor chip is large, the stress cannot be sufficiently warped. Stress concentrates on the later solder bump 20. If this stress cannot be absorbed by the solder bumps 20 after melting, cracks are likely to occur in the solder bumps 20 after melting, causing a problem in connection reliability.

Also, in the second prior art COG paste mounting, when the conductive adhesive, which is the connection point between the protruding electrode 4 on the semiconductor chip 2 and the glass substrate 28, is thermoset and returned to normal temperature, the semiconductor chip Since the conductive adhesive 44 supports the stress of the thermal contraction between the projecting electrode 4 on the substrate 2 and the transparent electrode 46 on the glass substrate 28, the stress is concentrated on the conductive adhesive 44. The coefficient of thermal expansion of the semiconductor chip 2 is 2.42
About 10-6, and the thermal expansion coefficient of the glass substrate 28 is 3
It is about 10 to 10-6. Here, for example, the expansion and contraction when the conductive adhesive 44 is thermally cured at 110 ° C. and returned to the normal temperature is 10 × 10 −6 × (maximum) in the glass substrate 28 when the semiconductor chip 2 is 15 mm. 110-
25) × (15 ÷ 2) = expansion / shrinkage of about 6.4 μm occurs. In the semiconductor chip 2, 2.42 × 10 −6
× (110-25) × (15 ÷ 2) = expansion / shrinkage of about 1.5 μm occurs. Therefore, in the glass substrate 28 and the semiconductor chip 2, 6.4 μm−1.5 μm = 4.9 μm
A degree of intrinsic stress is generated.

The intrinsic stress generated in the glass substrate 28 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the thickness of the semiconductor chip 2 is large, it cannot be sufficiently warped. Then, stress concentrates on the conductive adhesive 44 which is a connection point between the glass substrate 28 and the protruding electrode on the semiconductor chip 2. If this stress cannot be absorbed by the conductive adhesive 44, cracks are likely to occur in the conductive adhesive, causing a problem in connection reliability.

Also, a description will be given on the assumption that the semiconductor chip 2 is elongated, for example, as the frame of the liquid crystal display device is narrowed, for example, the long side of the semiconductor chip 2 is about 20 mm. The thermal expansion coefficient of the semiconductor chip 2 is 2.4
The thermal expansion coefficient of the glass substrate 28 is about 2 × 10 −6,
It is about 3 to 10 × 10 −6. 1 conductive adhesive 44
After thermosetting at 10 ° C. and returning to normal temperature, the glass substrate 28
In the maximum, 10 × 10-6 × (110-25)
× (20 ÷ 2) = expansion / shrinkage of about 8.5 μm.
In the semiconductor chip 2, 2.42 × 10−6 × (11
(0-25) × (20 ÷ 2) = expansion / contraction occurs about 2 μm. Therefore, in the glass substrate 28 and the semiconductor chip 2, an intrinsic stress corresponding to about 8.5 μm−2 μm = 6.5 μm is generated. This intrinsic stress concentrates on the conductive adhesive 44 which is a connection point between the semiconductor chip 2 and the glass substrate 28.

The intrinsic stress generated in the glass substrate 28 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the thickness of the semiconductor chip 2 is large, the stress cannot be sufficiently warped. Then, stress concentrates on the conductive adhesive 44 which is a connection point between the transparent electrode 46 on the glass substrate 28 and the protruding electrode 4 on the semiconductor chip 2. If this stress cannot be absorbed by the conductive adhesive, cracks are likely to occur in the conductive adhesive, causing a problem in connection reliability.

As can be seen from the above description, the intrinsic stress between the connection point in the longitudinal direction of the semiconductor chip 2 and the glass substrate 28 is further increased via the conductive adhesive 44, so that the warpage of the glass substrate 28 is also increased. As a result, the conductive adhesive 44 separates between the transparent electrode 46 and the conductive adhesive 44, and the connection between the protruding electrode 4 on the semiconductor chip 2 and the transparent electrode 46 on the glass substrate 28 cannot be established. A problem occurs in connection reliability.

The object of the present invention is to solve the above-mentioned problems and to learn the warpage of the circuit board or the glass substrate when connecting the semiconductor chip to the circuit board or the glass substrate face down. More specifically, it is an object of the present invention to provide a semiconductor chip structure in which, after face-down bonding, stress of solder or conductive adhesive, which is a connection point where stress is concentrated, is reduced.

[0023]

In order to achieve the above object, a semiconductor device mounting structure of the present invention employs the following configuration.

In the semiconductor chip structure of the present invention, slits are provided on the back surface of the semiconductor chip in a matrix or in a direction perpendicular to the long side direction.

In the flip chip mounting according to the present invention, after the semiconductor chip and the circuit board are face-down bonded and connected, a temperature cycle test, for example, -4
When put into a thermal cycle test in which 5 ° C. and 125 ° C. are alternately performed, the circuit board becomes 1.5 × 10 ⁻⁵ × (125 − (− 4
5)) × (15 ÷ 2) = expansion and contraction of about 19 μm.

Further, the coefficient of thermal expansion of the semiconductor chip is 2.
42 × 10−6 × (125 − (− 45)) × (15 °
2) Since the expansion and contraction occurs by about 3 μm, the maximum stress applied to the circuit board and the semiconductor chip is 19 μm−3 μm =
It is generated at about 16 μm. This stress tends to concentrate on the solder bump after melting, which is a connection point between the circuit board and the semiconductor chip.

The intrinsic stress generated in the circuit board and the semiconductor chip tends to diverge due to the warpage of both, but if the semiconductor chip is thick, it cannot be sufficiently warped. Stress concentrates on the solder bumps. If this stress cannot be absorbed by the solder bump after melting,
Cracks are likely to occur on the solder bumps after melting, causing problems in connection reliability.However, by providing slits in a matrix on the back surface of the semiconductor chip, the semiconductor chip follows the warpage of the circuit board Is possible,
Stress can be dissipated, and the concentration of stress on the solder bump after melting, which is a connection point between the circuit board and the semiconductor chip, is reduced or alleviated.

Second Embodiment In the COG paste mounting, when the conductive adhesive, which is the connection point between the protruding electrode on the semiconductor chip and the glass substrate, is cured by heat and returned to normal temperature, Since the conductive adhesive supports the heat shrinkage stress of the transparent electrode on the glass substrate, the stress concentrates on the conductive adhesive. The coefficient of thermal expansion of the semiconductor chip is about 2.42 × 10 −6, and the coefficient of thermal expansion of the glass substrate is about 3 to 10 × 10 −6. For example, when the conductive adhesive is thermally cured at 110 ° C. and returned to room temperature, the expansion and contraction when the semiconductor chip is 15 mm is 10 × 10−6 × (110−25) × at the maximum on a glass substrate.
(15 ÷ 2) = approximately 6.4 μm, and for a semiconductor chip, 2.42 × 10−6 × (110−25) × (1
5 ÷ 2) = about 1.5 μm. Therefore, for the glass substrate and the semiconductor chip, 6.4 μm−1.5 μm = 4.9 μm.
A stress of about m is generated.

The intrinsic stress generated in the glass substrate and the semiconductor chip tends to diverge due to the warpage of the two. However, if the thickness of the semiconductor chip cannot be sufficient, the intrinsic stress cannot be sufficiently warped. Stress concentrates on the conductive adhesive, which is the connection point of the protruding electrodes on the semiconductor chip. If this stress cannot be absorbed by the conductive adhesive, cracks are likely to occur in the conductive adhesive, causing a problem in connection reliability. However, slits are provided in a matrix on the back surface of the semiconductor chip. This makes it possible for the semiconductor chip to follow the warpage of the glass substrate, so that the stress can be dissipated, and the stress concentrates on the conductive adhesive, which is the connection point between the glass substrate and the bump electrode on the semiconductor chip. Is reduced and alleviated.

Further, as the frame of the liquid crystal display device becomes narrower, the semiconductor chip tends to be elongated. For example,
When the long side of the semiconductor chip is about 20 mm and the short side is about 1 mm, the coefficient of thermal expansion of the semiconductor chip is 2.42 × 1
About 0-6, the coefficient of thermal expansion of the glass substrate is 3-10 ×
It is about 10-6. When the conductive adhesive is heat-cured at 110 ° C. and then returned to room temperature, a maximum of 10 × 10−6 × (110−25) × (20 ÷ 2) =
About 8.5 μm, and in a semiconductor chip, 2.4 μm.
2 × 10−6 × (110−25) × (20 ÷ 2) = 2μ
About m. Therefore, with glass substrates and semiconductor chips,
A stress corresponding to about 8.5 μm−2 μm = 6.5 μm is generated.

The intrinsic stress generated in the glass substrate and the semiconductor chip tends to diverge due to the warpage of both, but cannot be sufficiently warped if the thickness of the semiconductor chip is large. Stress concentrates on the conductive adhesive, which is the connection point of the protruding electrodes on the semiconductor chip. If this stress cannot be absorbed by the conductive adhesive, the conductive adhesive is liable to cracks and has a problem in connection reliability. By providing the slit, the semiconductor chip can follow the warpage of the glass substrate, so that the stress can be dissipated and the conductive adhesive, which is a connection point between the glass substrate and the protruding electrode on the semiconductor chip, can be formed. Stress concentration is reduced.

[Operation] In the semiconductor chip structure of the present invention,
A slit is provided on the back surface of the semiconductor chip in a matrix or perpendicular to the long side direction.

In the first prior art, after a semiconductor chip and a circuit board are face-down bonded and connected, a temperature cycle test is performed, for example, a heat cycle test in which -45 ° C. and 125 ° C. are alternately performed. ,
1.5 × 10 ⁻⁵ × (125 − (− 45)) × (15 °
2) Expansion and contraction of about 19 μm occurs.

Further, the coefficient of thermal expansion of the semiconductor chip is 2.
42 × 10−6 × (125 − (− 45)) × (15 °
2) Since the expansion and contraction occurs by about 3 μm, the maximum stress applied to the circuit board and the semiconductor chip is 19 μm−3 μm =
It is generated at about 16 μm. This stress tends to concentrate on the solder bump after melting, which is a connection point between the circuit board and the semiconductor chip.

The intrinsic stress generated in the circuit board and the semiconductor chip tends to diverge due to the warpage of both, but cannot be sufficiently warped if the thickness of the semiconductor chip is large. Stress concentrates on the solder bumps. If this stress cannot be absorbed by the solder bumps after melting, cracks are likely to occur in the solder bumps after melting, causing problems in connection reliability. By providing the semiconductor chip,
Since it becomes possible to follow the warpage of the circuit board, the stress can be dissipated, and the stress concentration on the melted solder bump, which is the connection point between the circuit board and the semiconductor chip, is reduced and alleviated.

Second Embodiment In COG paste mounting, when the conductive adhesive, which is the connection point between the protruding electrodes on the semiconductor chip and the glass substrate, is cured by heat and returned to normal temperature, Since the conductive adhesive supports the heat shrinkage stress of the transparent electrode on the glass substrate, the stress concentrates on the conductive adhesive. The coefficient of thermal expansion of the semiconductor chip is about 2.42 × 10 −6, and the coefficient of thermal expansion of the glass substrate is about 3 to 10 × 10 −6. For example, when the conductive adhesive is thermally cured at 110 ° C. and returned to room temperature, the expansion and contraction when the semiconductor chip is 15 mm is 10 × 10−6 × (110−25) × at the maximum on a glass substrate.
(15 ÷ 2) = approximately 6.4 μm, and for a semiconductor chip, 2.42 × 10−6 × (110−25) × (1
5 ÷ 2) = about 1.5 μm. Therefore, for the glass substrate and the semiconductor chip, 6.4 μm−1.5 μm = 4.9 μm.
A stress of about m is generated.

The intrinsic stress generated in the glass substrate and the semiconductor chip tends to diverge due to the warpage of both, but cannot be sufficiently warped if the thickness of the semiconductor chip is large. Stress concentrates on the conductive adhesive, which is the connection point of the protruding electrodes on the semiconductor chip. If this stress cannot be absorbed by the conductive adhesive, cracks are likely to occur in the conductive adhesive, causing a problem in connection reliability. However, slits are provided in a matrix on the back surface of the semiconductor chip. As a result, the semiconductor chip can follow the warpage of the glass substrate, so that the stress can be dissipated, and the stress concentrates on the conductive adhesive, which is the connection point between the glass substrate and the bump electrode on the semiconductor chip. Is reduced and alleviated.

When the semiconductor chip is elongated with the narrowing of the frame of the liquid crystal display device, for example, when the long side of the semiconductor chip is about 20 mm and the short side is about 1 mm, the coefficient of thermal expansion of the semiconductor chip is increased. Is 2.42 × 10 −6
Degree, the thermal expansion coefficient of the glass substrate is 3-10 × 10−
It is about 6. When the conductive adhesive is heat-cured at 110 ° C. and then returned to room temperature, a maximum of 10 ×
10−6 × (110−25) × (20 ＝ 2) = 8.5 μ
m, and in a semiconductor chip, 2.42 × 1
0-6 × (110-25) × (20 （2) = about 2 μm. Therefore, in the case of the glass substrate and the semiconductor chip, 8.
A stress corresponding to about 5 μm−2 μm = 6.5 μm is generated.

The intrinsic stress generated in the glass substrate and the semiconductor chip tends to diverge due to the warpage of the two. However, if the thickness of the semiconductor chip is too large, the intrinsic stress cannot be sufficiently warped. Stress concentrates on the conductive adhesive, which is the connection point of the protruding electrodes on the semiconductor chip. If this stress cannot be absorbed by the conductive adhesive, the conductive adhesive is liable to cracks and has a problem in connection reliability. By providing the slit, the semiconductor chip can follow the warpage of the glass substrate, so that the stress can be dissipated and the conductive adhesive, which is a connection point between the glass substrate and the protruding electrode on the semiconductor chip, can be formed. Stress concentration is reduced.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a semiconductor chip in the best mode for carrying out the present invention will be described with reference to the following drawings. 2 and 3 are plan views showing the configuration of a semiconductor chip according to an embodiment of the present invention. FIG.
It is sectional drawing which shows the cross section in the -A line. FIG. 4 is a sectional view of flip-chip mounting according to the embodiment of the present invention. FIG. 5 is a sectional view of COG paste mounting according to the embodiment of the present invention. Hereinafter, FIGS. 1 to 5 and a method of forming a slit will be described with reference to FIGS.

The structure of flip-chip mounting according to the first embodiment of the present invention will be described with reference to FIG.

As shown in the sectional view of FIG.
And the semiconductor chip 2 are flip-chip mounted. If the external dimensions of the semiconductor chip 2 are, for example, 15 mm square, the slits 24 formed on the back surface of the semiconductor chip 2 are formed in a matrix. In this manner, the stress applied to the solder 20 after melting, which is applied radially from the center of the semiconductor chip 2, is formed by the slits 24 formed in a matrix on the back surface of the semiconductor chip 2. Since the followability of the warp with the substrate is improved, the stress on the solder 20 after melting is reduced.

The coefficient of thermal expansion of the semiconductor chip 2 is 2.42 ×
About 10 ^-6, the coefficient of thermal expansion of the circuit board shown in FIG. 3,
It is about 1.5 × 10 ⁻⁵ .

For example, when a 15 mm square semiconductor chip is used, the semiconductor chip 2 and the circuit board 10 are flip-chip mounted, electrically and mechanically connected, and then subjected to a temperature cycle test, for example, at -45 ° C. and 125 ° C. The circuit board is 1.5 × 10 ^-5
× (125 − (− 45)) × (15 ÷ 2) = expansion and contraction of about 19 μm.

The coefficient of thermal expansion of the semiconductor chip is 2.4.
2 × 10−6, 2.42 × 10−6 × (125 − (−
45)) × (15 ÷ 2) = expansion and contraction of about 3 μm, so that the maximum stress applied to the circuit board 10 and the semiconductor chip 2 is about 19 μm−3 μm = about 16 μm. This stress is a connection point between the circuit board 10 and the semiconductor chip 2.
It is easy to concentrate on the solder bumps 20 after melting.

The intrinsic stress generated in the circuit board 10 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the thickness of the semiconductor chip 2 is large, the stress cannot be sufficiently warped. Stress concentrates on the solder bumps 20 after melting. If this stress cannot be absorbed by the solder bumps 20 after melting, cracks tend to occur in the solder bumps 20 after melting, causing a problem in connection reliability. However, the slits 2 are arranged on the back surface of the semiconductor chip 2 in a matrix.
By providing the semiconductor chip 2, the semiconductor chip 2 can follow the warpage of the circuit board 10, so that the stress can be dissipated, and the solder bump after melting, which is a connection point between the circuit board 10 and the semiconductor chip 2. Stress concentration on 20 is reduced,
Be relaxed.

COG in the embodiment of the present invention
The paste mounting will be described with reference to FIG.

As shown in FIG. 5, when the glass substrate 28 and the semiconductor chip 2 are mounted by COG paste, the transparent electrodes 46 formed on the glass substrate 28 and the projecting electrodes 4 formed on the semiconductor chip 2 are electrically conductive. The connection is made electrically and mechanically via the adhesive 44.

The glass substrate 28 and the semiconductor chip 2 are COG
When the paste is mounted, for example, when the external dimensions of the semiconductor chip 2 are almost the same, the conductive paste, which is the connection point between the glass substrate 28 and the semiconductor chip 2, is thermoset and returned to room temperature. In this case, the same stress occurs vertically and horizontally. In this case, a matrix-shaped slit is formed on the back surface of the semiconductor chip 2. By doing so, the transparent electrode 46 on the glass substrate 28 and the semiconductor chip 2
The stress generated when the conductive adhesive 44 for electrically and mechanically connecting the upper protruding electrodes 4 is cured by heat and returned to normal temperature improves the followability of the semiconductor chip to the warpage of the glass substrate 28. Therefore, stress concentration on the conductive adhesive 44 is reduced.

Recently, the frame of the liquid crystal display substrate has been narrowed, and the aspect ratio of the outer shape of the semiconductor chip has been increased. For example, if it is set to 20 mm × 1 mm, the stress on the conductive adhesive 44 is greatly applied to the long side. In such a case, the slit 24 formed on the back surface of the semiconductor chip 2 is formed in a direction perpendicular to the long side. By doing so, the conductive adhesive 44 for electrically and mechanically connecting the transparent electrode 46 on the glass substrate 28 and the protruding electrode 4 on the semiconductor chip 2 is thermally cured and returned to room temperature. Since the follow-up stress of the semiconductor chip with respect to the warpage of the glass substrate 28 is improved, the stress concentration of the conductive adhesive 44 is reduced.

The thermosetting conductive adhesive 44 that electrically and mechanically connects the protruding electrode 4 on the semiconductor chip 2 and the transparent electrode 46 on the glass substrate 28 becomes a paste at room temperature at the connection target point. When the adhesive is thermally cured at about 110 ° C. and returned to room temperature, the stress of the thermal shrinkage of the projecting electrode 4 on the semiconductor chip 2 and the transparent electrode 46 on the glass substrate 28 is reduced by the semiconductor chip 2 and the glass substrate. Since the conductive adhesive 44, which is a connection point of 28, is to be supported, the conductive adhesive 44
Stress will be concentrated on The coefficient of thermal expansion of the semiconductor chip 2 is about 2.42 × 10 −6, and the coefficient of thermal expansion of the glass substrate 28 is about 3 to 10 × 10 −6. For example, when the conductive adhesive 44 is thermally cured at a temperature of 110 ° C. and returned to room temperature, the expansion and contraction when the semiconductor chip 2 is 15 mm is 10 × 10 −6 in the glass substrate 28 at the maximum.
× (110−25) × (15 ÷ 2) = approximately 6.4 μm. In the semiconductor chip 2, 2.42 × 10 −6
× (110-25) × (15 ÷ 2) = approximately 1.5 μm. Therefore, the glass substrate 28 and the semiconductor chip 2
In this case, an internal stress of about 6.4 μm−1.5 μm = 4.9 μm is generated.

The intrinsic stress generated in the glass substrate 28 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the thickness of the semiconductor chip 2 is large, the stress cannot be sufficiently warped. Glass substrate 28 and semiconductor chip 2
Stress concentrates on the conductive adhesive 44 which is a connection point of the upper protruding electrode 4. If this stress cannot be absorbed by the conductive adhesive 44, cracks are likely to occur in the conductive adhesive 44, causing a problem in connection reliability. Since the semiconductor chip 2 can follow the warpage of the glass substrate 28 by providing the slits 24 in the glass substrate 28, the internal stress can be diverted, and the projection electrodes 4 on the glass substrate 28 and the semiconductor chip 2 can be dissipated.
Stress concentration on the conductive adhesive 44 which is a connection point of
Be relaxed.

In recent years, as the frame of the liquid crystal display device has been narrowed, the semiconductor chip 2 has been elongated. For example,
The case where the long side of the semiconductor chip is about 20 mm and the short side is about 1 mm will be described with reference to FIG. The thermal expansion coefficient of the semiconductor chip 2 is about 2.42 × 10 −6 and the glass substrate 28
Has a thermal expansion coefficient of about 3 to 10 × 10 −6. When the semiconductor chip 2 and the transparent electrode 46 on the glass substrate 28 are electrically and mechanically connected with the conductive adhesive 44, for example, the conductive adhesive 44 is thermally cured at 110 ° C. and then returned to room temperature. In the substrate 28, at most 10 × 10−
6 × (110−25) × (20 ÷ 2) = 8.5 μm expansion / contraction occurs. In the semiconductor chip 2, 2.4
2 × 10−6 × (110−25) × (20 ÷ 2) = 2μ
Expansion and contraction of about m occur. Therefore, the glass substrate 2
8.5 and the semiconductor chip 2, 8.5 μm−2 μm = 6.
An internal stress of about 5 μm is generated.

The intrinsic stress generated in the glass substrate 28 and the semiconductor chip 2 tends to diverge due to the warpage of both, but if the semiconductor chip 2 has a sufficient thickness, it cannot be warped sufficiently. Stress concentrates on the conductive adhesive 44 which is a connection point between the substrate 28 and the protruding electrode 4 on the semiconductor chip 2. When this stress is absorbed by the conductive adhesive 44 to clean the conductive chip 44, cracks are easily generated in the conductive adhesive 44, causing a problem in connection reliability.
By providing slits 24 perpendicularly to the long sides on the back surface of semiconductor substrate 2, semiconductor chip 2 can follow the warpage of glass substrate 28, so that stress can be dissipated, and glass substrate 28 and semiconductor chip 2 Stress concentration on the conductive adhesive 44, which is a connection point with the upper protruding electrode 4, is reduced or alleviated.

Next, a method of forming a slit will be described. For example, the thickness of the 5-inch wafer 36 shown in FIG. 14 is about 640 μm.

As shown in FIG. 14, a resist film 32 is formed on the wafer 36 by a spinner or the like so as to cover the protruding electrodes 4, and is cured at 145 ° C. for about 20 minutes. Protect.

As shown in FIG. 15, the slit 24 is formed on the back surface of the wafer 36 by a dicing saw in the manner of cutting the wafer.

Since the slit 24 uses a dicing saw blade, the slit width can be determined by the width of the blade to be used (about 20 μm to 30 μm). The thickness of the residue when cutting the back surface of the wafer is about half the thickness of the wafer.

Next, as shown in FIG.
The resist film 32 formed on the device and the protruding electrode of No. 6 was peeled off at 100 ° C. for about 10 minutes using a resist peeling solution, and the wafer 36 was sufficiently washed with pure water or the like and dried.

Finally, as shown in FIG.
Dicing is performed along the dicing line on the protruding electrode side, which is the surface of the semiconductor chip 2, and the semiconductor chip 2 is divided.

The above steps are performed, and slits are formed on the back surface of the semiconductor chip 2 in a matrix or, when the aspect ratio of the semiconductor chip is large, perpendicular to the long side of the semiconductor chip, as shown in FIG. When face-down connection is made to the circuit board 10 or the glass substrate 28 shown in FIG. 5, the semiconductor chip 2 and the circuit board 10 or the glass substrate 28 are learned after the circuit board 10 or the glass substrate 28 is warped. In addition, the stress of the solder or the conductive adhesive 44 after melting the solder bump 20, which is the connection point where the stress is concentrated, can be reduced.

[0062]

As is apparent from the above description, the structure of the semiconductor chip 2 according to the present invention follows the warpage of the circuit board 10 and the glass substrate 28, so that the size of the semiconductor chip 2 is increased. Even if the semiconductor chip 2 is elongated by narrowing the frame, the quality of the solder can be stabilized without peeling of the solder and the conductive adhesive 44 after the solder bump 20 is melted, and without causing a connection failure.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a plan view in which slits are formed in a matrix on the back surface of the semiconductor chip according to the embodiment of the present invention.

FIG. 3 is a plan view in which a slit is formed on a rear surface of a semiconductor chip in a direction perpendicular to a long side in the embodiment of the present invention.

FIG. 4 is a sectional view after flip-chip mounting in the embodiment of the present invention.

FIG. 5 is a cross-sectional view after mounting a COG paste in the embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor chip according to the first prior art of the present invention.

FIG. 7 is a cross-sectional view showing a state in which a flux is supplied to a semiconductor chip according to the first prior art of the present invention.

FIG. 8 is a sectional view showing a state in which a semiconductor chip is mounted on a wiring board according to the first conventional technique of the present invention.

FIG. 9 is a cross-sectional view showing a state in which a semiconductor chip according to the first prior art of the present invention is connected to a wiring board.

FIG. 10 is a sectional view of a semiconductor chip according to a second prior art of the present invention.

FIG. 11 is a cross-sectional view showing a state in which a conductive adhesive is supplied to a semiconductor chip according to a second conventional technique of the present invention.

FIG. 12 is a cross-sectional view of a state in which a glass substrate and a semiconductor chip are connected according to the second conventional technique of the present invention.

FIG. 13 is a cross-sectional view showing a state in which a liquid crystal display device and a semiconductor chip are connected according to the second conventional technique of the present invention.

FIG. 14 is a cross-sectional view showing a state where a resist is formed on a semiconductor wafer according to an embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a state where a slit is formed in a semiconductor wafer according to an embodiment of the present invention.

FIG. 16 is a cross-sectional view of the semiconductor wafer according to the embodiment of the present invention in a state where a resist is removed.

FIG. 17 is a cross-sectional view showing a state where a semiconductor wafer is formed into a semiconductor chip in the embodiment of the present invention.

[Explanation of symbols]

2: Semiconductor chip 4: Projection electrode
6: insulating film 8: mounting pad 10: circuit board
12: Electrode 14: Common electrode film 18: Protrusion electrode such as copper 20: Solder bump 22: Flux
24: slit 26: sealing resin 28: glass substrate
30: projecting electrode 32: resist film 36: wafer 38: liquid crystal display device 40: sealing material
42: liquid crystal 44: conductive paste 46: transparent electrode

Claims (5)

[Claims] 1. A circuit in which a circuit board, an electrode pad provided on the circuit board, and a semiconductor chip and a protruding electrode provided on the semiconductor chip are connected by face-down bonding. A semiconductor device characterized by providing a slit for reducing stress of a semiconductor chip connected face-down by warpage. 2. A circuit in which a circuit board, an electrode provided on the circuit board, and a semiconductor chip and a protruding electrode formed by solder provided on the semiconductor chip are face-down bonded and connected, and a back surface of the semiconductor chip is provided. A semiconductor device is provided with a slit for relieving stress of a semiconductor chip connected face-down bonding due to warpage of a substrate. 3. A liquid crystal display device comprising: a glass substrate; a transparent electrode provided on the glass substrate; and a semiconductor chip and a protruding electrode provided on the semiconductor chip connected face-down by a conductive adhesive. A slit for reducing stress of the semiconductor chip connected face-down bonding due to the warpage of the glass substrate. 4. The semiconductor device according to claim 1, wherein the slit has a depth approximately half the thickness of the semiconductor chip. 5. A slit formed on the back surface of a semiconductor device having the same external dimensions as the aspect ratio of the semiconductor device, characterized in that the slit is formed in a vertical and horizontal matrix, and the aspect ratio of the semiconductor chip is as large as about ten times. 4. The semiconductor device according to claim 1, wherein a slit is formed perpendicular to a longitudinal direction of a back surface of the semiconductor device.