CN104347682A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN104347682A CN104347682A CN201310356743.8A CN201310356743A CN104347682A CN 104347682 A CN104347682 A CN 104347682A CN 201310356743 A CN201310356743 A CN 201310356743A CN 104347682 A CN104347682 A CN 104347682A
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- end points
- side wall
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- resistance
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000011241 protective layer Substances 0.000 claims abstract description 111
- 230000002180 anti-stress Effects 0.000 abstract 8
- 239000012141 concentrate Substances 0.000 description 6
- 238000000502 dialysis Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
Abstract
The invention relates to a semiconductor structure, which is provided with a first corner and comprises a carrier, a first protective layer, a second protective layer and a third protective layer, wherein the carrier is provided with a carrier surface, the carrier surface is provided with a protective layer setting area, the first protective layer is arranged in the protective layer setting area, the first protective layer is provided with a first surface, the first surface is provided with a first setting area, a first anti-stress area and a first exposure area, the first anti-stress area is positioned at the corner of the first setting area, the second protective layer is arranged in the first setting area, the second protective layer is provided with a second surface, the second surface is provided with a second setting area, a second anti-stress area and a second exposure area, the second anti-stress area is positioned at the corner of the second setting area, the third protective layer is arranged in the second setting area, and the first anti-stress area and the second anti-stress area are positioned at the first corner, and the area of the first anti-stress area is not smaller than that of the second anti-stress area.
Description
Technical field
The invention relates to a kind of semiconductor structure, particularly a kind of semiconductor structure avoiding stress to concentrate on corner.
Background technology
Refer to Fig. 7, for the known semiconductor structure 200 of one, it has carrier 210, first protective layer 220, second protective layer 230 and the 3rd protective layer 240, this carrier has surface 211, this first protective layer 220 is arranged on this surface 211, and this first protective layer 220 has the first side wall 221 and connects the second side wall 222 of this first side wall 221, this second protective layer 230 is arranged on this first protective layer 220, this second protective layer 230 has the 3rd side wall 231 and connects the 4th side wall 232 of the 3rd side wall 231, 3rd protective layer 240 is arranged on this second protective layer 230, 3rd protective layer 240 has the 5th side wall 241 and connects the 6th side wall 242 of the 5th side wall 241, due to this first protective layer 220, the size of this second protective layer 230 and the 3rd protective layer 240 is different, and the 3rd side wall 231 of this second protective layer 230 and the 4th side wall 232 junction are right angle, 5th side wall 241 and the 6th side wall 242 junction of the 3rd protective layer 240 are also right angle, therefore when this first protective layer 220, when this second protective layer 230 and the 3rd protective layer 240 layers are located on this surface 211 of this carrier 210, stress easily concentrates on the 3rd side wall 231 and the 4th side wall 232 junction of this second protective layer 230, broken or dialysis in 3rd side wall 231 and the 4th side wall 232 junction, and then affect the yield of this semiconductor structure 200.
As can be seen here, above-mentioned existing semiconductor structure with in use in structure, obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development, and common product does not have appropriate structure to solve the problem, this is obviously the anxious problem for solving of relevant dealer always.Therefore how to found a kind of novel semiconductor structure, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor structure, and its surface by each protective layer has resistance to stress district, makes stress can not concentrate on the corner of each protective layer, and semiconductor structure can be avoided to be broken or dialysis by corner.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the semiconductor structure that the present invention proposes, it has the first corner and the second corner, and this semiconductor structure also comprises: carrier, and it has carrier surface, and this carrier surface has protective layer setting area and the protective layer be positioned at outside this protective layer setting area appears district; First protective layer, it is arranged at this protective layer setting area, this first protective layer has first surface, this first surface has the first setting area, the first resistance to stress district and is positioned at first outside this first setting area and this first resistance to stress district and appears district, and this first resistance to stress district is positioned at the corner of this first setting area; Second protective layer, it is arranged at this first setting area, and this second protective layer appears this first resistance to stress district and this first appears district, this second protective layer has second surface, this second surface has the second setting area, the second resistance to stress district and is positioned at second outside this second setting area and this second resistance to stress district and appears district, and this second resistance to stress district is positioned at the corner of this second setting area; And the 3rd protective layer; it is arranged at this second setting area; and the 3rd protective layer appears this second resistance to stress district and this second appears district, this first resistance to stress district and this second resistance to stress district are positioned at this first corner, and the area in this first resistance to stress district is not less than the area in this second resistance to stress district.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor structure, wherein this second protective layer has the first side wall, second side wall and connect first of this first side wall and this second side wall and connect wall, this first side wall has the first base and this first base has the first end points, this second side wall has the second base and this second base has the second end points, the first line stretcher extended to form by this first end points on this first base is crossing with the second line stretcher that this second end points by this second base extends to form is formed with the first basic point, and connect this first basic point, the region that this first end points and this second end points are formed is this first resistance to stress district.
Aforesaid semiconductor structure, wherein the 3rd protective layer has the 3rd side wall, 4th side wall and connect second of the 3rd side wall and the 4th side wall and connect wall, 3rd side wall has the 3rd base and the 3rd base has the 3rd end points, 4th side wall has the 4th base and the 4th base has the 4th end points, the 3rd line stretcher extended to form by the 3rd end points on the 3rd base is crossing with the 4th line stretcher that the 4th end points by the 4th base extends to form is formed with the second basic point, and connect this second basic point, the region that 3rd end points and the 4th end points are formed is this second resistance to stress district.
Aforesaid semiconductor structure, wherein has the first distance between this second basic point and the 3rd end points, and this second basic point and the 4th end points have second distance, and this first distance equals this second distance.
Aforesaid semiconductor structure, wherein this second protective layer has the first side wall, second side wall and connect first of this first side wall and this second side wall and connect wall, this first side wall has the first top margin and this first top margin has five terminal point, this second side wall has the second top margin and this second top margin has the 6th end points, between this five terminal point to the 3rd end points, there is the 3rd distance, 3rd distance is the beeline of this first top margin to the 3rd base, between 6th end points to the 4th end points, there is the 4th distance, 4th distance is the beeline of this second top margin to the 4th base.
Aforesaid semiconductor structure, wherein this first to connect wall be plane or cambered surface.
Aforesaid semiconductor structure, wherein this second to connect wall be plane or cambered surface.
Aforesaid semiconductor structure; wherein this first surface of this first protective layer has the 3rd resistance to stress district; and the 3rd resistance to stress district is positioned at the corner of this first setting area; this second protective layer appears the 3rd resistance to stress district; this second surface of this second protective layer has the 4th resistance to stress district; 4th resistance to stress district is positioned at the corner of this second setting area; and the 3rd protective layer appears the 4th resistance to stress district; 3rd resistance to stress district and the 4th resistance to stress district are positioned at this second corner, and the area in the 3rd resistance to stress district is not less than the area in the 4th resistance to stress district.
Aforesaid semiconductor structure, wherein this second protective layer has the first side wall, 5th side wall and connect the 3rd of this first side wall and the 5th side wall and connect wall, this first side wall has the first base and this first base has the 7th end points, 5th side wall has the 5th base and the 5th base has the 8th end points, the 5th line stretcher extended to form by the 7th end points on this first base is crossing with the 6th line stretcher that the 8th end points by the 5th base extends to form is formed with the 3rd basic point, and connect the 3rd basic point, the region that 7th end points and the 8th end points are formed is the 3rd resistance to stress district.
Aforesaid semiconductor structure, wherein the 3rd protective layer has the 3rd side wall, 6th side wall and connect the 4th of the 3rd side wall and the 6th side wall and connect wall, 3rd side wall has the 3rd base and the 3rd base has the 9th end points, 6th side wall has the 6th base and the 6th base has the tenth end points, the 7th line stretcher extended to form by the 9th end points on the 3rd base is crossing with the 8th line stretcher that the tenth end points by the 6th base extends to form is formed with the 4th basic point, and connect the 4th basic point, the region that 9th end points and the tenth end points are formed is the 4th resistance to stress district.
Aforesaid semiconductor structure, wherein this second protective layer has the first side wall, 5th side wall and connect the 3rd of this first side wall and the 5th side wall and connect wall, this first side wall has the first top margin and this first top margin has the 11 end points, 5th side wall has the 3rd top margin and the 3rd top margin has the 12 end points, between 11 end points to the 9th end points, there is the 5th distance, 5th distance is the beeline of this first top margin to the 3rd base, between 12 end points to the tenth end points, there is the 6th distance, 6th distance is the beeline of the 3rd top margin to the 6th base.
Aforesaid semiconductor structure, wherein has the 7th distance between the 3rd basic point and the 7th end points, and the 3rd basic point and the 8th end points have the 8th distance, and the 7th distance equals the 8th distance.
Aforesaid semiconductor structure, wherein has the 9th distance between the 4th basic point and the 9th end points, and the 4th basic point and the tenth end points have the tenth distance, and the 9th distance equals the tenth distance.
Aforesaid semiconductor structure, wherein the 3rd to connect wall be plane or cambered surface.
Aforesaid semiconductor structure, wherein the 4th to connect wall be plane or cambered surface.
By technique scheme; semiconductor structure of the present invention at least has following advantages and beneficial effect: because this first protective layer of the present invention has this first resistance to stress district; this second protective layer has this second resistance to stress district; therefore the stress of this semiconductor structure can not concentrate on this first corner, this semiconductor structure can be avoided to be broken by this first corner or dialysis and cause the yield of this semiconductor structure to reduce.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1: according to the first preferred embodiment of the present invention, a kind of exploded perspective view of semiconductor structure.
Fig. 2: according to the first preferred embodiment of the present invention, the stereogram of this semiconductor structure.
Fig. 3: according to the first preferred embodiment of the present invention, the vertical view of this semiconductor structure.
Fig. 4: according to the first preferred embodiment of the present invention, another stereogram of this semiconductor structure.
Fig. 5: according to the second preferred embodiment of the present invention, a kind of stereogram of semiconductor structure.
Fig. 6: according to the second preferred embodiment of the present invention, the vertical view of this semiconductor structure.
Fig. 7: the stereogram of Known semiconductor structure.
100: semiconductor structure 100a: the first corner
100b: the second corner 110: carrier
111: carrier surface 111a: protective layer setting area
111b: protective layer appears district 120: the first protective layer
121: first surface 121a: the first setting area
121b: the first resistance to stress district 121c: the first appears district
121d: the three resistance to stress district 130: the second protective layer
131: second surface 131a: the second setting area
131b: the second resistance to stress district 131c: the second appears district
131d: the four resistance to stress district 132: the first side wall
132a: the first base 132b: the first top margin
133: the second side wall 133a: the second bases
133b: the second top margin 134: the first connects wall
135: the five side wall 135a: the five bases
135b: the three top margin 136: the three connects wall
140: the three protective layer 141: the three side walls
141a: the three base 142: the four side wall
142a: the four base 143: the second connects wall
144: the six side wall 144a: the six bases
145: the four connect wall
A1: the first basic point A2: the second basic point
A3: the three basic point A4: the four basic point
D1: the first distance D2: second distance
D3: the three distance D4: the four distance
D5: the five distance D6: the six distance
D7: the seven distance D8: the eight distance
D9: the nine distance D10: the ten distance
L1: the first line stretcher L2: the second line stretcher
L3: the three line stretcher L4: the four line stretcher
L5: the five line stretcher L6: the six line stretcher
L7: the seven line stretcher L8: the eight line stretcher
P1: the first end points P2: the second end points
P3: the three end points P4: the four end points
P5: the five terminal point P6: the six end points
P7: the seven end points P8: the eight end points
P9: the nine end points P10: the ten end points
P11: the ten one end points P12: the 12 end points
200: semiconductor structure 210: carrier
211: surface 220: the first protective layers
221: the first side wall 222: the second side walls
230: the second protective layer 231: the three side walls
232: the four side wall 240: the three protective layers
241: the five side wall 242: the six side walls
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of semiconductor structure proposed according to the present invention, structure, feature and effect thereof, be described in detail as follows.
Refer to Fig. 1 and Fig. 2, it is the first preferred embodiment of the present invention, a kind of semiconductor structure 100 has the first corner 100a and the second corner 100b, this semiconductor structure 100 includes carrier 110, first protective layer 120, second protective layer 130 and the 3rd protective layer 140, this carrier 110 has carrier surface 111, this carrier surface 111 has protective layer setting area 111a and the protective layer be positioned at outside the 111a of this protective layer setting area appears district 111b, this first protective layer 120 is arranged at this protective layer setting area 111a, this first protective layer 120 has first surface 121, this first surface 121 has the first setting area 121a, first resistance to stress district 121b and be positioned at first outside this first setting area 121a and this first resistance to stress district 121b and appear district 121c, this first resistance to stress district 121b is positioned at the corner of this first setting area 121a, this second protective layer 130 is arranged at this first setting area 121a, and this second protective layer 130 appears this first resistance to stress district 121b and this first appears district 121c, this second protective layer 130 has second surface 131, this second surface 131 has the second setting area 131a, second resistance to stress district 131b and be positioned at second outside this second setting area 131a and this second resistance to stress district 131b and appear district 131c, this second resistance to stress district 131b is positioned at the corner of this second setting area 131a.
Refer to Fig. 2 and Fig. 3, this second protective layer 130 has the first side wall 132, second side wall 133 and connect this first side wall 132 and connect wall 134 with first of this second side wall 133, this first side wall 132 has the first base 132a and this first base 132a has the first end points P1, this second side wall 133 has the second base 133a and this second base 133a has the second end points P2, the the first line stretcher L1 extended to form by this first end points P1 of this first base 132a is crossing with the second line stretcher L2 that this second end points P2 by this second base 133a extends to form is formed with the first basic point A1, and connect this first basic point A1, the region that this first end points P1 and this second end points P2 is formed is this first resistance to stress district 121b, in the present embodiment, this first connects wall 134 for plane.
Referring again to Fig. 1, Fig. 2 and Fig. 3, 3rd protective layer 140 is arranged at this second setting area 131a, and the 3rd protective layer 140 appears this second resistance to stress district 131b and this second appears district 131c, this first resistance to stress district 121b and this second resistance to stress district 131b is positioned at this first corner 100a, and the area of this first resistance to stress district 121b is not less than the area of this second resistance to stress district 131b, in the present embodiment, 3rd protective layer 140 has the 3rd side wall 141, 4th side wall 142 and connect the 3rd side wall 141 and connect wall 143 with second of the 4th side wall 142, 3rd side wall 141 has the 3rd base 141a and the 3rd base 141a has the 3rd end points P3, 4th side wall 142 has the 4th base 142a and the 4th base 142a has the 4th end points P4, the 3rd line stretcher L3 extended to form by the 3rd end points P3 of the 3rd base 141a is crossing with the 4th line stretcher L4 that the 4th end points P4 by the 4th base 142a extends to form is formed with the second basic point A2, and connect this second basic point A2, the region that 3rd end points P3 and the 4th end points P4 is formed is this second resistance to stress district 131b, this second connects wall 143 for plane, and between this second basic point A2 and the 3rd end points P3, there is the first distance D1, this the second basic point A2 and the 4th end points P4 has second distance D2, this first distance D1 equals this second distance D2.
Referring again to Fig. 2 and Fig. 3, in the present embodiment, this first side wall 132 of this second protective layer 130 separately has the first top margin 132b and this first top margin 132b has five terminal point P5, this second side wall 133 has the second top margin 133b and this second top margin 133b has the 6th end points P6, between this five terminal point P5 to the 3rd end points P3, there is the 3rd distance D3, 3rd distance D3 is the beeline of this first top margin 132b to the 3rd base 141a, between 6th end points P6 to the 4th end points P4, there is the 4th distance D4, 4th distance D4 is the beeline of this second top margin 133b to the 4th base 142a.
Refer to Fig. 1 and Fig. 4, this first surface 121 of this first protective layer 120 separately has the 3rd resistance to stress district 121d, and the 3rd resistance to stress district 121d is positioned at the corner of this first setting area 121a, this second protective layer 130 appears the 3rd resistance to stress district 121d, this second surface 131 of this second protective layer 130 has the 4th resistance to stress district 131d, 4th resistance to stress district 131d is positioned at the corner of this second setting area 131a, and the 3rd protective layer 140 appears the 4th resistance to stress district 131d, 3rd resistance to stress district 121d and the 4th resistance to stress district 131d is positioned at this second corner 100b, and the area of the 3rd resistance to stress district 121d is not less than the area of the 4th resistance to stress district 131d, refer to Fig. 3 and Fig. 4, this second protective layer 130 separately has the 5th side wall 135 and connects this first side wall 132 and connects wall 136 with the 3rd of the 5th side wall 135, this first base 132a of this first side wall 132 has the 7th end points P7, 5th side wall 135 has the 5th base 135a and the 5th base 135a has the 8th end points P8, 3rd connects wall 136 for plane, the 5th line stretcher L5 extended to form by the 7th end points P7 of this first base 132a is crossing with the 6th line stretcher L6 that the 8th end points P8 by the 5th base 135a extends to form is formed with the 3rd basic point A3, and connect the 3rd basic point A3, the region that 7th end points P7 and the 8th end points P8 is formed is the 3rd resistance to stress district 121d.
Referring again to Fig. 3 and Fig. 4, 3rd protective layer 140 separately has the 6th side wall 144 and connects the 3rd side wall 141 and connects wall 145 with the 4th of the 6th side wall 144, 3rd base 141a of the 3rd side wall 141 has the 9th end points P9, 6th side wall 144 has the 6th base 144a and the 6th base 144a has the tenth end points P10, 4th connects wall 145 for plane, the 7th line stretcher L7 extended to form by the 9th end points P9 of the 3rd base 141a is crossing with the 8th line stretcher L8 that the tenth end points P10 by the 6th base 144a extends to form is formed with the 4th basic point A4, and connect the 4th basic point A4, the region that 9th end points P9 and the tenth end points P10 is formed is the 4th resistance to stress district 131d.
Referring again to Fig. 3 and Fig. 4, this first top margin 132b of this first side wall 132 of this second protective layer 130 has the 11 end points P11, 5th side wall 135 has the 3rd top margin 135b and the 3rd top margin 135b has the 12 end points P12, between 11 end points P11 to the 9th end points P9, there is the 5th distance D5, 5th distance D5 is the beeline of this first top margin 132b to the 3rd base 141a, between 12 end points P12 to the tenth end points P10, there is the 6th distance D6, 6th distance D6 is the beeline of the 3rd top margin 135b to the 6th base 144a, in addition, in the present embodiment, there is between the 3rd basic point A3 and the 7th end points P7 the 7th distance D7, 3rd basic point A3 and the 8th end points P8 has the 8th distance D8, 7th distance D7 equals the 8th distance D8, there is between the 4th basic point A4 and the 9th end points P9 the 9th distance D9, 4th basic point A4 and the tenth end points P10 has the tenth distance D10, 9th distance D9 equals the tenth distance D10.
Because this first resistance to stress district 121b of the present invention and this second resistance to stress district 131b is positioned at this first corner 100a, 3rd resistance to stress district 121d and the 4th resistance to stress district 131d is positioned at this second corner 100b, therefore stress can be avoided to concentrate on this first corner 100a and this second corner 100b, and this second protective layer 130 this first connect that wall 134 and the 3rd connects wall 136 and the 3rd protective layer 140 this second connect wall 143 and the 4th and connect wall 145 also there is the effect preventing stress from concentrating on corner, therefore the situation that this semiconductor structure 100 is produced dialysis by this first corner 100a or this second corner 100b or broken and cause this semiconductor structure 100 yield not good can be avoided.
Refer to Fig. 5 and Fig. 6, it is the second preferred embodiment of the present invention, the difference of itself and the first preferred embodiment is that this first connects wall 134, this second connects wall 143, 3rd connects wall 136 and the 4th connects wall 145 for cambered surface, when this first connects wall 134, this second connects wall 143, 3rd connects wall 136 and the 4th when connecting wall 145 for cambered surface, also the stress of this semiconductor structure 100 can be avoided to concentrate on this first side wall 132 and this second side wall 133 junction (contiguous this first corner 100a) of this second protective layer 130, therefore this semiconductor structure 100 can be prevented by this first side wall 132 and this second side wall 133 junction dialysis or break.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (15)
1. a semiconductor structure, it is characterized in that it has the first corner and the second corner, this semiconductor structure also comprises:
Carrier, it has carrier surface, and this carrier surface has protective layer setting area and the protective layer be positioned at outside this protective layer setting area appears district;
First protective layer, it is arranged at this protective layer setting area, this first protective layer has first surface, this first surface has the first setting area, the first resistance to stress district and is positioned at first outside this first setting area and this first resistance to stress district and appears district, and this first resistance to stress district is positioned at the corner of this first setting area;
Second protective layer, it is arranged at this first setting area, and this second protective layer appears this first resistance to stress district and this first appears district, this second protective layer has second surface, this second surface has the second setting area, the second resistance to stress district and is positioned at second outside this second setting area and this second resistance to stress district and appears district, and this second resistance to stress district is positioned at the corner of this second setting area; And
3rd protective layer; it is arranged at this second setting area; and the 3rd protective layer appears this second resistance to stress district and this second appears district, this first resistance to stress district and this second resistance to stress district are positioned at this first corner, and the area in this first resistance to stress district is not less than the area in this second resistance to stress district.
2. semiconductor structure as claimed in claim 1, it is characterized in that this second protective layer has the first side wall, second side wall and connect first of this first side wall and this second side wall and connect wall, this first side wall has the first base and this first base has the first end points, this second side wall has the second base and this second base has the second end points, the first line stretcher extended to form by this first end points on this first base is crossing with the second line stretcher that this second end points by this second base extends to form is formed with the first basic point, and connect this first basic point, the region that this first end points and this second end points are formed is this first resistance to stress district.
3. semiconductor structure as claimed in claim 1, it is characterized in that the 3rd protective layer has the 3rd side wall, 4th side wall and connect second of the 3rd side wall and the 4th side wall and connect wall, 3rd side wall has the 3rd base and the 3rd base has the 3rd end points, 4th side wall has the 4th base and the 4th base has the 4th end points, the 3rd line stretcher extended to form by the 3rd end points on the 3rd base is crossing with the 4th line stretcher that the 4th end points by the 4th base extends to form is formed with the second basic point, and connect this second basic point, the region that 3rd end points and the 4th end points are formed is this second resistance to stress district.
4. semiconductor structure as claimed in claim 3, it is characterized in that having the first distance between this second basic point and the 3rd end points, this second basic point and the 4th end points have second distance, and this first distance equals this second distance.
5. semiconductor structure as claimed in claim 3, it is characterized in that this second protective layer has the first side wall, second side wall and connect first of this first side wall and this second side wall and connect wall, this first side wall has the first top margin and this first top margin has five terminal point, this second side wall has the second top margin and this second top margin has the 6th end points, between this five terminal point to the 3rd end points, there is the 3rd distance, 3rd distance is the beeline of this first top margin to the 3rd base, between 6th end points to the 4th end points, there is the 4th distance, 4th distance is the beeline of this second top margin to the 4th base.
6. semiconductor structure as claimed in claim 2, is characterized in that first to connect wall be plane or cambered surface for this.
7. semiconductor structure as claimed in claim 3, is characterized in that second to connect wall be plane or cambered surface for this.
8. semiconductor structure as claimed in claim 1, it is characterized in that this first surface of this first protective layer has the 3rd resistance to stress district, and the 3rd resistance to stress district is positioned at the corner of this first setting area, this second protective layer appears the 3rd resistance to stress district, this second surface of this second protective layer has the 4th resistance to stress district, 4th resistance to stress district is positioned at the corner of this second setting area, and the 3rd protective layer appears the 4th resistance to stress district, 3rd resistance to stress district and the 4th resistance to stress district are positioned at this second corner, and the area in the 3rd resistance to stress district is not less than the area in the 4th resistance to stress district.
9. semiconductor structure as claimed in claim 8, it is characterized in that this second protective layer has the first side wall, 5th side wall and connect the 3rd of this first side wall and the 5th side wall and connect wall, this first side wall has the first base and this first base has the 7th end points, 5th side wall has the 5th base and the 5th base has the 8th end points, the 5th line stretcher extended to form by the 7th end points on this first base is crossing with the 6th line stretcher that the 8th end points by the 5th base extends to form is formed with the 3rd basic point, and connect the 3rd basic point, the region that 7th end points and the 8th end points are formed is the 3rd resistance to stress district.
10. semiconductor structure as claimed in claim 8, it is characterized in that the 3rd protective layer has the 3rd side wall, 6th side wall and connect the 4th of the 3rd side wall and the 6th side wall and connect wall, 3rd side wall has the 3rd base and the 3rd base has the 9th end points, 6th side wall has the 6th base and the 6th base has the tenth end points, the 7th line stretcher extended to form by the 9th end points on the 3rd base is crossing with the 8th line stretcher that the tenth end points by the 6th base extends to form is formed with the 4th basic point, and connect the 4th basic point, the region that 9th end points and the tenth end points are formed is the 4th resistance to stress district.
11. semiconductor structures as claimed in claim 10, it is characterized in that this second protective layer has the first side wall, 5th side wall and connect the 3rd of this first side wall and the 5th side wall and connect wall, this first side wall has the first top margin and this first top margin has the 11 end points, 5th side wall has the 3rd top margin and the 3rd top margin has the 12 end points, between 11 end points to the 9th end points, there is the 5th distance, 5th distance is the beeline of this first top margin to the 3rd base, between 12 end points to the tenth end points, there is the 6th distance, 6th distance is the beeline of the 3rd top margin to the 6th base.
12. semiconductor structures as claimed in claim 9, is characterized in that having the 7th distance between the 3rd basic point and the 7th end points, and the 3rd basic point and the 8th end points have the 8th distance, and the 7th distance equals the 8th distance.
13. semiconductor structures as claimed in claim 10, is characterized in that having the 9th distance between the 4th basic point and the 9th end points, and the 4th basic point and the tenth end points have the tenth distance, and the 9th distance equals the tenth distance.
14. semiconductor structures as claimed in claim 9, it is characterized in that the 3rd, to connect wall be plane or cambered surface.
15. semiconductor structures as claimed in claim 10, it is characterized in that the 4th, to connect wall be plane or cambered surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102127697 | 2013-08-02 | ||
| TW102127697A TWI467757B (en) | 2013-08-02 | 2013-08-02 | Semiconductor structure |
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| Publication Number | Publication Date |
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| CN104347682A true CN104347682A (en) | 2015-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310356743.8A Pending CN104347682A (en) | 2013-08-02 | 2013-08-15 | Semiconductor structure |
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| JP (1) | JP5933645B2 (en) |
| KR (1) | KR101613190B1 (en) |
| CN (1) | CN104347682A (en) |
| SG (1) | SG10201404283UA (en) |
| TW (1) | TWI467757B (en) |
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| CN104518005A (en) * | 2013-09-27 | 2015-04-15 | 颀邦科技股份有限公司 | Semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI467711B (en) * | 2013-09-10 | 2015-01-01 | Chipbond Technology Corp | Semiconductorstructure |
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Also Published As
| Publication number | Publication date |
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| JP2015032826A (en) | 2015-02-16 |
| KR101613190B1 (en) | 2016-04-18 |
| KR20150016110A (en) | 2015-02-11 |
| TWI467757B (en) | 2015-01-01 |
| SG10201404283UA (en) | 2015-03-30 |
| JP5933645B2 (en) | 2016-06-15 |
| TW201507148A (en) | 2015-02-16 |
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