JP2001127024A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2001127024A JP2001127024A JP30683799A JP30683799A JP2001127024A JP 2001127024 A JP2001127024 A JP 2001127024A JP 30683799 A JP30683799 A JP 30683799A JP 30683799 A JP30683799 A JP 30683799A JP 2001127024 A JP2001127024 A JP 2001127024A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- semiconductor
- protective film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係り、特に表面保護膜を改良した半導体装
置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an improved surface protective film and a method of manufacturing the same.
【0002】[0002]
【従来の技術】従来、半導体装置において、半導体素子
表面の損傷等を防ぐために、ウエハ上に形成された半導
体素子を、表面保護膜として例えばポリイミド膜により
完全に覆った後、図8に示すように、コーナー部の形状
に関して特に考慮することなく、直角にパターニングし
てきた。2. Description of the Related Art Conventionally, in a semiconductor device, after a semiconductor element formed on a wafer is completely covered with, for example, a polyimide film as a surface protective film in order to prevent damage to the surface of the semiconductor element, as shown in FIG. In addition, patterning has been performed at a right angle without any particular consideration regarding the shape of the corner portion.
【0003】しかしながら、後工程においてコーナー部
より剥離が生じる等の不具合が生じていた。However, there have been problems such as peeling off from the corners in the subsequent steps.
【0004】[0004]
【発明が解決しようとする課題】この様に、従来の半導
体装置においては、表面保護膜のコーナー部より剥離が
生じ、このため、ラップ工程(ウエーハ裏面を削り所定
厚にする工程)において不均一に削られたり、組立工程
においてモールド樹脂により剥離部分が傷つけられると
いった問題が発生していた。また、放射線(α線)防止
の役割もあるため、その剥離が放射線による装置破壊の
原因の一つとなっていた。As described above, in the conventional semiconductor device, the corners of the surface protection film are separated from each other, so that the lapping process (the process of shaving the back surface of the wafer to a predetermined thickness) is not uniform. In the assembling process, there has been a problem that the peeled portion is damaged by the mold resin. In addition, since it also has a role of preventing radiation (α rays), the peeling has been one of the causes of device destruction due to radiation.
【0005】従って本発明は、このような従来の半導体
装置の欠点を取り除き、表面保護膜の剥離がなく、歩留
まりや信頼性を向上させることが可能になる半導体装置
及びその製造方法を提供することを目的とするものであ
る。Accordingly, the present invention is to provide a semiconductor device which eliminates the drawbacks of the conventional semiconductor device, does not peel off the surface protective film, can improve the yield and the reliability, and a method of manufacturing the same. It is intended for.
【0006】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体素子表面に、揮発性溶剤を含む半導体素子保護材
を塗布・熱硬化することにより形成された半導体素子保
護膜を備え、前記半導体素子保護膜のコーナー部が面取
りされていることを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element surface is provided with a semiconductor element protective film formed by applying and thermally curing a semiconductor element protective material containing a volatile solvent, and a corner portion of the semiconductor element protective film is chamfered. .
【0007】また、本発明の半導体装置においては、前
記面取り角度が115°以上155°以下であることを
特徴とする。Further, in the semiconductor device according to the present invention, the chamfer angle is not less than 115 ° and not more than 155 °.
【0008】本発明の半導体装置の製造方法は、半導体
基板上に形成された複数の半導体素子の表面を、揮発性
溶剤を含む半導体素子保護材で被覆し、各半導体素子毎
にコーナー部を面取りした形にパターニングを行ない、
前記各半導体素子表面に半導体素子保護膜を形成する工
程を備えることを特徴とする。According to a method of manufacturing a semiconductor device of the present invention, a surface of a plurality of semiconductor elements formed on a semiconductor substrate is covered with a semiconductor element protective material containing a volatile solvent, and a corner is chamfered for each semiconductor element. Patterning in the shape
Forming a semiconductor element protection film on the surface of each of the semiconductor elements.
【0009】また、本発明の半導体装置の製造方法にお
いては、前記コーナー部を面取り角度115°以上15
5°以下で面取りすることを特徴とする。Further, in the method of manufacturing a semiconductor device according to the present invention, the corner portion is chamfered at an angle of 115 ° or more and 15 ° or more.
It is characterized by chamfering at an angle of 5 ° or less.
【0010】[0010]
【発明の実施の形態】本発明の一実施形態について、図
1乃至図7を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.
【0011】図1に示すように、ウエーハ1上に並んだ
半導体素子2表面に、半導体素子保護材として感光性ポ
リイミド材を全面塗布する。揮発性溶剤にはNMP(N-
メチル-2-ピロリドン)を用いる。As shown in FIG. 1, a photosensitive polyimide material is applied on the entire surface of a semiconductor element 2 arranged on a wafer 1 as a semiconductor element protection material. NMP (N-
Methyl-2-pyrrolidone) is used.
【0012】これを、図2に示すように、面取り角度1
35°となるマスクパターンを用いて露光、現像を行な
うことによりパターニングし、半導体素子保護膜3を形
成する。ここで、面取り角度4は半導体素子保護膜3の
外周5におけるコーナー部の内角で表す。次にこれを熱
処理し、ポリイミド材を熱硬化させると、パターンは伸
縮により図3に示すように曲線的に仕上がる。ここで、
6はダイシングラインである。[0012] As shown in FIG.
Patterning is performed by performing exposure and development using a mask pattern of 35 ° to form a semiconductor element protection film 3. Here, the chamfer angle 4 is represented by an inner angle of a corner portion on the outer periphery 5 of the semiconductor element protective film 3. Next, when this is heat-treated and the polyimide material is thermally cured, the pattern is completed in a curved manner as shown in FIG. 3 due to expansion and contraction. here,
6 is a dicing line.
【0013】この時、形成した半導体素子保護膜内に残
留する揮発性溶剤が空気中に逃れるため、収縮が生じ
る。この時の模式図を、図4及び図5に示す。ここで、
図4は上面図、図5は断面図である。尚、7はポリイミ
ドの収縮する力を示す。図4においては、コーナーにお
ける収縮方向が分散しているため、図5に示すように、
周辺の収縮力は小さく、膜剥がれを引き起こす程大きな
応力は発生しない。また、従来のパターンにおける模式
図を同様に図6及び図7に示す。収縮方向は2方向とな
り、かつコーナーにおいて集中しているため、45°方
向に大きな収縮力が働き、膜剥がれを引き起こす応力が
発生する。図7に示すように、収縮力は下層膜に接して
いない表面部の方が大きくなるので、膜剥がれを引き起
こす応力8は左上方向に大きく働く。At this time, since the volatile solvent remaining in the formed semiconductor element protective film escapes into the air, shrinkage occurs. FIGS. 4 and 5 show schematic diagrams at this time. here,
FIG. 4 is a top view and FIG. 5 is a sectional view. Here, 7 indicates the contracting force of the polyimide. In FIG. 4, since the contraction directions at the corners are dispersed, as shown in FIG.
The contraction force at the periphery is small, and a stress large enough to cause film peeling does not occur. FIGS. 6 and 7 are schematic views of a conventional pattern. Since the contraction directions are two directions and are concentrated at the corners, a large contraction force acts in the 45 ° direction, and a stress causing film peeling is generated. As shown in FIG. 7, since the contraction force is larger at the surface portion not in contact with the lower layer film, the stress 8 that causes the film to peel is large in the upper left direction.
【0014】このように本実施形態においては、従来の
パターンよりコーナー部における応力集中が緩和される
ことがわかる。As described above, in the present embodiment, it can be seen that the stress concentration at the corners is reduced as compared with the conventional pattern.
【0015】さらに、従来のパターンのものと本実施形
態のパターンのものについて、実際のプロセスに沿って
試験を行なう。まず、Si酸化膜にSi窒化膜を重ねた
2層構造からなるパッシベーション膜を形成する。この
上に、本実施形態と同様にポリイミド膜からなる半導体
素子保護膜を各パターンで形成し、これをマスクとして
パッシベーション膜をCDEとWetの連続エッチング
によりパターニングする。尚、本試験条件は実際に晒さ
れるプロセスのうち、ポリイミドの剥離を引き起こす傾
向のあるものを選択している。Further, a test is performed on the conventional pattern and the pattern of the present embodiment in accordance with an actual process. First, a Si nitride film was overlaid on a Si oxide film
A passivation film having a two-layer structure is formed. On this, a semiconductor element protection film made of a polyimide film is formed in each pattern as in the present embodiment, and the passivation film is patterned by continuous etching of CDE and Wet using these as masks. In this test condition, among the processes to be actually exposed, those having a tendency to cause peeling of the polyimide were selected.
【0016】このようにして形成された半導体素子保護
膜について、従来のものの剥がれの発生は、28サンプ
ル/28サンプル=100%で認められるが、本実施形
態のものは、0サンプル/82サンプル=0%となり、
大幅に改善されることがわかる。このように応力集中が
緩和されることより、剥離の発生が抑えられ、歩留ま
り、信頼性の高い半導体素子保護膜を形成することがで
きる。In the semiconductor element protective film thus formed, peeling of the conventional device is observed at 28 samples / 28 samples = 100%, but in the present embodiment, 0 samples / 82 samples = 0%,
It can be seen that it is greatly improved. By alleviating the stress concentration in this manner, the occurrence of peeling is suppressed, and a semiconductor element protective film with high yield and high reliability can be formed.
【0017】尚、本実施形態においては、全ての面取り
角度を135°としたが、面取り角度は全て等しくある
必要はなく、90°より大きく、180°より小さけれ
ば良い。より好ましくは、135°近傍であり、115
°以上155°以下である。In this embodiment, all the chamfer angles are set to 135 °. However, all the chamfer angles need not be equal, but may be larger than 90 ° and smaller than 180 °. More preferably, it is near 135 °, and 115
以上 ° to 155 °.
【0018】また、本実施形態では直線で面取りした
が、曲線で面取りしても、同等以上の効果を得ることが
できる。Further, in the present embodiment, the chamfering is performed with a straight line, but the same or more effect can be obtained by chamfering with a curved line.
【0019】さらに、本実施形態においては、感光性ポ
リイミド材を用いているが、非感光性ポリイミド材を用
いても良い。また、本実施形態においては、半導体素子
保護材をパターニングした後、熱処理を行なっている
が、熱処理後にパターニングしても良い。このような場
合においても残留溶剤により剥がれ応力が発生している
ので、本実施形態と同様に効果的である。Further, in this embodiment, a photosensitive polyimide material is used, but a non-photosensitive polyimide material may be used. Further, in this embodiment, the heat treatment is performed after the semiconductor element protective material is patterned, but the patterning may be performed after the heat treatment. Even in such a case, since the peeling stress is generated by the residual solvent, it is as effective as the present embodiment.
【0020】この様にして半導体素子保護膜を形成した
後、ラッピング、ダイシングを行ない、組立工程を経て
半導体装置が形成される。After the semiconductor element protective film is formed in this manner, lapping and dicing are performed, and a semiconductor device is formed through an assembling process.
【0021】[0021]
【発明の効果】本発明によれば、剥離がなく、歩留まり
や信頼性を向上させることが可能になる半導体装置及び
その製造方法を提供することができる。According to the present invention, it is possible to provide a semiconductor device capable of improving yield and reliability without delamination and a method of manufacturing the same.
【図1】ウエーハ上に形成された半導体素子を示す図。FIG. 1 is a view showing a semiconductor element formed on a wafer.
【図2】面取りした半導体素子保護膜のコーナー部を示
す図。FIG. 2 is a diagram showing a corner portion of a chamfered semiconductor element protective film.
【図3】熱処理後の半導体素子保護膜のコーナー部を示
す図。FIG. 3 is a diagram showing a corner portion of a semiconductor element protective film after heat treatment.
【図4】本発明の半導体素子保護膜のコーナー部におけ
る模式図(上面図)。FIG. 4 is a schematic diagram (top view) of a corner portion of the semiconductor element protective film of the present invention.
【図5】本発明の半導体素子保護膜のコーナー部におけ
る模式図(断面図)。FIG. 5 is a schematic diagram (cross-sectional view) of a corner portion of the semiconductor element protective film of the present invention.
【図6】従来の半導体素子保護膜のコーナー部における
模式図(上面図)。FIG. 6 is a schematic view (top view) of a corner portion of a conventional semiconductor element protection film.
【図7】従来の半導体素子保護膜のコーナー部における
模式図(断面図)。FIG. 7 is a schematic view (cross-sectional view) of a corner portion of a conventional semiconductor element protection film.
【図8】従来の半導体素子保護膜のコーナー部を示す
図。FIG. 8 is a diagram showing a corner portion of a conventional semiconductor element protection film.
1 ウエハ 2 半導体素子 3 半導体素子保護膜 4 面取り角度 5 半導体素子保護膜外周 6 ダイシングライン 7 ポリイミドの収縮する力 8 膜剥がれを引き起こす応力 DESCRIPTION OF SYMBOLS 1 Wafer 2 Semiconductor element 3 Semiconductor element protective film 4 Chamfer angle 5 Peripheral of semiconductor element protective film 6 Dicing line 7 Shrinking force of polyimide 8 Stress causing film peeling
Claims (4)
導体素子保護材を塗布・熱硬化することにより形成され
た半導体素子保護膜を備え、前記半導体素子保護膜のコ
ーナー部が面取りされていることを特徴とする半導体装
置。1. A semiconductor element protective film formed by applying and thermally curing a semiconductor element protective material containing a volatile solvent on a surface of a semiconductor element, wherein a corner portion of the semiconductor element protective film is chamfered. A semiconductor device characterized by the above-mentioned.
以下であることを特徴とする請求項1記載の半導体装
置。2. The chamfer angle is at least 115 ° and 155 °.
2. The semiconductor device according to claim 1, wherein:
素子の表面を、揮発性溶剤を含む半導体素子保護材で被
覆し、各半導体素子毎にコーナー部を面取りした形にパ
ターニングを行ない、前記各半導体素子表面に半導体素
子保護膜を形成する工程を備えることを特徴とする半導
体装置の製造方法。3. The surface of a plurality of semiconductor elements formed on a semiconductor substrate is covered with a semiconductor element protection material containing a volatile solvent, and patterning is performed in such a manner that a corner is chamfered for each semiconductor element. A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor element protective film on a surface of each semiconductor element.
上155°以下で面取りすることを特徴とする請求項3
記載の半導体装置の製造方法。4. The method according to claim 3, wherein the corner portion is chamfered at a chamfer angle of 115 ° or more and 155 ° or less.
The manufacturing method of the semiconductor device described in the above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30683799A JP2001127024A (en) | 1999-10-28 | 1999-10-28 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30683799A JP2001127024A (en) | 1999-10-28 | 1999-10-28 | Semiconductor device and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001127024A true JP2001127024A (en) | 2001-05-11 |
Family
ID=17961864
Family Applications (1)
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JP30683799A Pending JP2001127024A (en) | 1999-10-28 | 1999-10-28 | Semiconductor device and manufacturing method thereof |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1594042A1 (en) * | 2003-02-12 | 2005-11-09 | Nissha Printing Co., Ltd. | Touch panel |
JP2012109614A (en) * | 2012-02-24 | 2012-06-07 | Seiko Epson Corp | Semiconductor device, circuit board, and electronic apparatus |
JP2014197710A (en) * | 2014-07-11 | 2014-10-16 | セイコーエプソン株式会社 | Semiconductor device, circuit board, and electronic apparatus |
CN104347682A (en) * | 2013-08-02 | 2015-02-11 | 颀邦科技股份有限公司 | Semiconductor structure |
JP2015056658A (en) * | 2013-09-10 | 2015-03-23 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2016171183A (en) * | 2015-03-12 | 2016-09-23 | 日本電信電話株式会社 | Semiconductor integrated circuit |
-
1999
- 1999-10-28 JP JP30683799A patent/JP2001127024A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1594042A1 (en) * | 2003-02-12 | 2005-11-09 | Nissha Printing Co., Ltd. | Touch panel |
EP1594042A4 (en) * | 2003-02-12 | 2008-11-19 | Nissha Printing | Touch panel |
US7710400B2 (en) | 2003-02-12 | 2010-05-04 | Nissha Printing Co., Ltd. | Touch panel having a transparent insulation film resistant to peel-off |
JP2012109614A (en) * | 2012-02-24 | 2012-06-07 | Seiko Epson Corp | Semiconductor device, circuit board, and electronic apparatus |
CN104347682A (en) * | 2013-08-02 | 2015-02-11 | 颀邦科技股份有限公司 | Semiconductor structure |
JP2015032826A (en) * | 2013-08-02 | 2015-02-16 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2015056658A (en) * | 2013-09-10 | 2015-03-23 | ▲き▼邦科技股▲分▼有限公司 | Semiconductor device |
JP2014197710A (en) * | 2014-07-11 | 2014-10-16 | セイコーエプソン株式会社 | Semiconductor device, circuit board, and electronic apparatus |
JP2016171183A (en) * | 2015-03-12 | 2016-09-23 | 日本電信電話株式会社 | Semiconductor integrated circuit |
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