KR0154289B1 - Method of fabricating transistor - Google Patents
Method of fabricating transistor Download PDFInfo
- Publication number
- KR0154289B1 KR0154289B1 KR1019950045982A KR19950045982A KR0154289B1 KR 0154289 B1 KR0154289 B1 KR 0154289B1 KR 1019950045982 A KR1019950045982 A KR 1019950045982A KR 19950045982 A KR19950045982 A KR 19950045982A KR 0154289 B1 KR0154289 B1 KR 0154289B1
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- South Korea
- Prior art keywords
- film
- gate electrode
- photoresist
- photoresist film
- transistor
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 13
- 230000001681 protective effect Effects 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 접합영역을 형성하기 위한 이온 주입 공정시 불순물 이온 주입에 의한 게이트 전극의 특성 저하를 방지하기 위하여 상기 게이트 전극의 상부에 감광막 및 보호막을 형성하므로써 소자의 신뢰성이 향상될 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, wherein the device is formed by forming a photosensitive film and a protective film on top of the gate electrode in order to prevent deterioration of the characteristics of the gate electrode by impurity ion implantation during an ion implantation process for forming a junction region. It relates to a method for manufacturing a transistor of a semiconductor device so that the reliability thereof can be improved.
Description
제1a 내지 1c도는 종래 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제2a 내지 제2c도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘 기판 2 및 12 : 게이트 절연막1 and 11: silicon substrate 2 and 12: gate insulating film
3 및 13 : 도전층 4 및 14 : 제1감광막3 and 13: conductive layers 4 and 14: first photosensitive film
5 및 15 : 불순물 이온 6 및 16 : 제2감광막5 and 15: impurity ions 6 and 16: second photosensitive film
7 및 17 : 접합영역 10 및 20 : 게이트 전극7 and 17: junction region 10 and 20: gate electrode
18 : 보호막18: protective film
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 접합영역을 형성하기 위한 이온 주입 공정시 게이트 전극으로 불순물 이온이 주입되지 않도록 하므로써 소자의 신뢰성이 향상될 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor of a semiconductor device, and more particularly, to a method of manufacturing a transistor of a semiconductor device in which the reliability of the device can be improved by preventing impurity ions from being injected into the gate electrode during an ion implantation process for forming a junction region. It is about.
종래에는 제1a도에 도시된 바와 같이 필드 산화막(도시않됨)이 형성된 실리콘 기판(1)상에 게이트 절연막(2), 도전층(3) 및 제1감광막(4)을 순차적으로 형성한 후 게이트 전극용 마스크를 사용하여 상기 제1감광막(4)을 패터닝하고, 상기 패터닝된 제1감광막(4)을 마스크로 이용하여 노출된 부분의 상기 도전층(3) 및 게이트 절연막(2)을 순차적으로 식각하여 게이트 전극(10)을 형성한다. 상기 제1감광막(4)을 제거한 후 전체 상부면에 제2감광막(6)을 도포하고 제1b도에 도시된 바와 같이 이온이 주입될 부분의 상기 실리콘 기판(1)이 노출되도록 상기 제2감광막(6)을 패터닝한다. 이후 전체 상부면에 불순물 이온을 주입하여 상기 노출된 게이트 전극(10) 양측부의 상기 실리콘 기판(1)에 접합영역(7)을 형성하고 제1c도에 도시된 바와 같이 잔류된 상기 제2감광막(6)을 제거한다. 그런데 이와 같은 공정은 상기 불순물 이온 주입 공정시 상기 제1b도에 도시된 바와 같이 노출된 게이트 전극(10)의 표면 부위에도 불순물 이온이 주입되기 대문에 게이트 전극의 특성이 저하되어 소자의 신뢰성이 저하되는 단점이 있다.Conventionally, as shown in FIG. 1A, a gate insulating film 2, a conductive layer 3, and a first photosensitive film 4 are sequentially formed on a silicon substrate 1 on which a field oxide film (not shown) is formed. The first photosensitive film 4 is patterned using an electrode mask, and the conductive layer 3 and the gate insulating film 2 of the exposed portion are sequentially used using the patterned first photosensitive film 4 as a mask. Etching is performed to form the gate electrode 10. After removing the first photoresist film 4, the second photoresist film 6 is applied to the entire upper surface thereof, and the second photoresist film is exposed to expose the silicon substrate 1 in a portion to be implanted with ions as shown in FIG. 1B. Pattern (6). Thereafter, impurity ions are implanted into the entire upper surface to form a junction region 7 in the silicon substrate 1 at both sides of the exposed gate electrode 10, and the second photoresist film remaining as shown in FIG. 6) Remove. However, in this process, since impurity ions are also implanted in the exposed surface of the gate electrode 10 as shown in FIG. 1B during the impurity ion implantation process, the characteristics of the gate electrode are deteriorated, thereby reducing the reliability of the device. There is a disadvantage.
따라서 본 발명은 접합영역을 형성하기 위한 이온 주입 공정시 게이트 전극으로 불순물 이온이 주입되지 않도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device which can solve the above disadvantages by preventing impurity ions from being injected into the gate electrode during the ion implantation process for forming the junction region.
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 게이트 절연막, 도전층 및 제1감광막을 순차적으로 형성한 후 게이트 전극용 마스크를 이용하여 상기 제1감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 제1감광막을 마스크로 이용하여 노출된 부분의 상기 도전층 및 게이트 전극막을 순차적으로 식각하여 게이트 전극을 형성하는 단계와, 상기 단계로부터 상기 게이트 전극 상부에 잔류된 상기 제1감광막을 경화시킨 후 전체 상부면에 보호막 및 제2감광막을 순차적으로 형성하고 이온이 주입될 부분의 상기 실리콘 기판이 노출되도록 상기 제2감광막을 패터닝하는 단계와, 상기 단계로부터 전체 상부면에 불순물 이온을 주입하여 상기 노출된 게이트 전극 양측부의 상기 실리콘 기판에 접합영역을 형성하는 단계와, 상기 단계로부터 잔류된 상기 제2감광막, 보호막 및 제1감광막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하며, 상기 보호막은 헥사메틸디실라센(HMDS)을 증착하여 형성하는 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming a gate insulating film, a conductive layer and a first photosensitive film on a silicon substrate and patterning the first photosensitive film using a mask for the gate electrode, from the step Sequentially etching the exposed conductive layer and the gate electrode film using the patterned first photoresist film as a mask to form a gate electrode, and curing the first photoresist film remaining on the gate electrode from the step. Thereafter, the protective film and the second photoresist film are sequentially formed on the entire upper surface, and the second photoresist film is patterned to expose the silicon substrate in the portion where the ions are to be implanted. Forming a junction region in the silicon substrate on both sides of the exposed gate electrode, and in the step portion And sequentially removing the remaining second photoresist film, the protective film, and the first photoresist film. The protective film is formed by depositing hexamethyldisilacene (HMDS).
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 제2c도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도로서, 제2a도는 필드 산화막(도시않됨)이 형성된 실리콘 기판(11)상에 게이트 절연막(12), 도전층(13) 및 제1감광막(14)을 순차적으로 형성한 후 게이트 전극용 마스크를 이용하여 상기 제1감광막(14)을 패터닝하고, 상기 패터닝된 제1감광막(14)을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 도전층(13) 및 게이트 절연막(12)을 순차적으로 식각하여 게이트 전극(20)을 형성한 상태의 단면도이다.2A through 2C are cross-sectional views of a device for explaining a method of manufacturing a transistor of a semiconductor device according to the present invention, and FIG. 2A shows a gate insulating film 12 and a conductive layer on a silicon substrate 11 on which a field oxide film (not shown) is formed. After sequentially forming the layer 13 and the first photoresist layer 14, the first photoresist layer 14 is patterned by using a gate electrode mask, and the etching process using the patterned first photoresist layer 14 as a mask. The conductive layer 13 and the gate insulating layer 12 of the exposed portion are sequentially etched to form a gate electrode 20.
제2b도는 180 내지 300℃의 온도 상태에서 상기 게이트 전극(20) 상부에 잔류된 상기 제1감광막(14)을 경화시킨 후 전체 상부면에 보호막(18) 및 제2감광막(16)을 순차적으로 형성하고 이온이 주입될 부분의 상기 실리콘 기판(11)이 노출되도록 상기 제2감광막(16)을 패터닝한다. 이후 전체 상부면에 불순물 이온을 주입하여 상기 노출된 게이트 전극(20) 양측부의 상기 실리콘 기판(11)에 접합영역(17)을 형성한 상태의 단면도로소, 이때 상기 불순물 이온(15)은 상기 제1 및 제2감광막(14 및 16)의 표면에도 주입된다. 또한 상기 보호막(18)은 헥사메틸디실라센(Hexa Methyl DiSilazane:HMDS)을 증착하여 형성한다.2b illustrates that the first photosensitive film 14 remaining on the gate electrode 20 is cured at a temperature of 180 to 300 ° C., and then the protective film 18 and the second photosensitive film 16 are sequentially formed on the entire upper surface thereof. The second photoresist layer 16 is patterned to form and expose the silicon substrate 11 at a portion where ions are to be implanted. After that, the impurity ions are implanted into the entire upper surface to form a junction region 17 in the silicon substrate 11 at both sides of the exposed gate electrode 20. It is also injected into the surfaces of the first and second photosensitive films 14 and 16. In addition, the protective film 18 is formed by depositing hexamethyl disilacene (Hexa Methyl DiSilazane: HMDS).
제2c도는 잔류된 상기 제2감광막(16), 보호막(18) 및 제1감광막(14)을 순차적으로 제거한 상태의 단면도로서, 상기 제2b도의 불순물 이온 주입 공정시 상기 게이트 전극(20)으로 불순물 이온이 주입되는 것이 상기 제1감광막(14) 및 보호막(18)에 의해 방지되어 상기 게이트 전극(20)의 특성 저하가 발생되지 않는다.FIG. 2C is a cross-sectional view of the second photoresist film 16, the protective film 18, and the first photoresist film 14 sequentially removed. Implantation of ions is prevented by the first photosensitive film 14 and the protective film 18 so that deterioration of the characteristics of the gate electrode 20 does not occur.
상술한 바와 같이 본 발명에 의하면 접합영역을 형성하기 위한 이온 주입 공정시 게이트 전극으로 불순물 이온이 주입되지 않도록 하므로써 불순물 이온 주입에 의한 게이트 전극의 특성 저하가 발생하지 않아 소자의 신뢰성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since impurity ions are not injected into the gate electrode during the ion implantation process for forming the junction region, the deterioration of the characteristics of the gate electrode due to the impurity ion implantation does not occur, thereby improving the reliability of the device. Excellent effect
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950045982A KR0154289B1 (en) | 1995-12-01 | 1995-12-01 | Method of fabricating transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950045982A KR0154289B1 (en) | 1995-12-01 | 1995-12-01 | Method of fabricating transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053011A KR970053011A (en) | 1997-07-29 |
| KR0154289B1 true KR0154289B1 (en) | 1998-12-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950045982A KR0154289B1 (en) | 1995-12-01 | 1995-12-01 | Method of fabricating transistor |
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| Country | Link |
|---|---|
| KR (1) | KR0154289B1 (en) |
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1995
- 1995-12-01 KR KR1019950045982A patent/KR0154289B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR970053011A (en) | 1997-07-29 |
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