JPS63271939A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63271939A JPS63271939A JP10739687A JP10739687A JPS63271939A JP S63271939 A JPS63271939 A JP S63271939A JP 10739687 A JP10739687 A JP 10739687A JP 10739687 A JP10739687 A JP 10739687A JP S63271939 A JPS63271939 A JP S63271939A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photosensitive organic
- organic film
- semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 abstract description 2
- 239000013557 residual solvent Substances 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract 2
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 241000723353 Chrysanthemum Species 0.000 description 2
- 235000007516 Chrysanthemum Nutrition 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005453 pelletization Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に半導体装備の製造方法に関し、特に半導体装置
の表面保護膜（パッジベージ冒ン膜）ｒｉ、半導体装置
表面の傷防止、耐湿性向上を目的として窒化膜を使用し
ているが一方でｒｉ樹脂封止形パッケージにおいてｒｔ
樹脂の応力にょシ表面保＃！Ｉ＃′十半導体装置にクラ
ックが入るという問題から表面保護膜である窒化膜の上
にバッファー暎として有機膜を付ける方法が一般的とな
りつつある。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing semiconductor equipment, and particularly relates to a method for manufacturing semiconductor equipment, and in particular to a surface protection film (pudgeage-proofing film) for semiconductor devices, prevention of scratches on the surface of semiconductor devices, and improvement of moisture resistance. Nitride film is used for this purpose, but on the other hand, RT
Resin stress-free surface protection! Due to the problem of cracks appearing in semiconductor devices, a method of attaching an organic film as a buffer on a nitride film, which is a surface protection film, is becoming common.
第４図（ａｌ〜（ｅ）及び第５図は従来のパッジベージ
璽ン膜および半導体装置の製造方法である。まず第４図
（ａ）に示す様に半導体素子を形成した半導体基板１の
上に第１のバッジベージ曹ン膜としてプラズマ法により
シリコン窒化膜３を１０００λ〜１００００Ａ程度堆積
させその上にポジ型ホトレジスト５を塗布する０次に第
４図（ｂ）ｌ’（示す様に外部引き出し用電極２を鉢出
させるため開口部を無光した後勤口部のホトレジストを
除去する。次ＩＦＪ４図（Ｃ）に示す様にドライエツチ
ング法によりホトレジストをマスクとして′成極２上の
シリコン窒化膜３をエツチングし不要となったホトレジ
ストを全面除去する。次に第４図（ｄｌに示す様にシリ
コン窒化膜３の上に有機膜としてポリイはド情脂６を塗
布しさらにホトレジスト５を塗布する。さらに電極２を
蕗出させる為に開口部を無光しこの部分のホトレジス）
？＜除去する。次に第４図ｔｅｌに示す様に電極開口部
のボリイずドをホトレジストヲマスクとしてエツチング
し最後に不要となったホトレジストを全面除去する。4(a) to 5(e) and 5 show a conventional method for manufacturing a padding film and a semiconductor device.First, as shown in FIG. 4(a), a semiconductor substrate 1 on which semiconductor elements are formed is placed. A silicon nitride film 3 of about 1000λ to 10000A is deposited as a first badge-base carbon film by plasma method, and a positive photoresist 5 is applied thereon. In order to expose the electrode 2, the photoresist at the back end of the electrode 2 is removed.Next, as shown in FIG. 3 and remove the unnecessary photoresist from the entire surface. Next, as shown in FIG. .Furthermore, in order to make the electrode 2 stick out, the opening was made dark and photoresist was applied to this part)
? <Remove. Next, as shown in FIG. 4, the photoresist is used as a mask to etch the electrode opening, and finally, the unnecessary photoresist is completely removed.
次に第５図に示した様に半導体基板をペレッタイズした
半導体チップ５をリードフレーム６にダイマウントし次
にボンディングし粥脂８で封止する。Next, as shown in FIG. 5, a semiconductor chip 5 obtained by pelletizing a semiconductor substrate is die-mounted on a lead frame 6, then bonded and sealed with gruel 8.
上述した従来のバッジベージ言ン膜形成方法はパッジベ
ージ１ン膜としてのシリコン窒化膜３とポリイミド樹脂
を引出し電極臓出の為にそれぞれフォトリングラフイー
法により開口部分のみ除去きせる必要が有りフォトリン
グラフイ一工程を２回行なわなければならないという欠
点がある。In the conventional badge page film formation method described above, it is necessary to extract the silicon nitride film 3 and the polyimide resin as the badge page film and remove only the opening portions using the photophosphorography method to expose the electrodes. A disadvantage is that one step must be performed twice.
本発明の半導体装置の製造方法は半導体素子を有する半
導体基板上に無機系絶縁膜層を形成する工程とｒｎＪ記
絶縁膜上に感光性有機膜を形成する工程と前記感光性有
機膜の一部分を開口する工程と前記感光性有機膜をマス
クとして？＋’＋Ｊ記無磯系絶縁膜をエツチングする工
程とエツチングが終了した後前記感光性有機膜を残すこ
とを特徴とする半導体装置の製造方法。The method for manufacturing a semiconductor device of the present invention includes a step of forming an inorganic insulating film layer on a semiconductor substrate having a semiconductor element, a step of forming a photosensitive organic film on the insulating film, and a step of forming a part of the photosensitive organic film. The opening process and using the photosensitive organic film as a mask? +'+J A method for manufacturing a semiconductor device, comprising the steps of etching a non-porous insulating film and leaving the photosensitive organic film after the etching is completed.
次に、本発明について図面を参照して駅間する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）〜（ｄ）、第２図は本発明の一実施例を説
明するための工程順に示した半導体装置の断面図である
。FIGS. 1(a) to (d) and FIG. 2 are cross-sectional views of a semiconductor device shown in order of steps for explaining an embodiment of the present invention.
この実施例でｒｔまず第１図ｔａ）に示す様に半導体素
子を形成した半導体基板１の上に第１のパッジベージ冒
ン膜としてフ゛ラズマＣＶＤ法によりシリコン窒化膜３
ｋｌＯ００Ａ〜１００ＯＯＡ堆積させる。次に第１図（
ｂｌに示す様にその上に感光性有機膜４．たとえば感光
性ボリイはド４を０．５μｍ〜２０Ａｍ程度塗布した後
プリベークを１００℃前後のＮ３雰囲気中で行う。次に
第１図ｔｃ）に示す様に通常用いられている無光、現像
を行い引き出し電極部分のポリイミドｌｌａを除去しポ
リイはド膜の感光成分および残溶剤の除去のためのポス
トベークを行う。次に第１図（ｄｌに示す様にシリコン
窒化膜３をポリイミド膜４をマスクにして通常用いられ
ているエツチングガスとしてＣＦ４又は０８添加ＣＦ４
を用いたドライエツチング法によシリコン酸化膜を除去
する。In this embodiment, first, as shown in FIG. 1 (ta), a silicon nitride film 3 is deposited by plasma CVD as a first padding film on a semiconductor substrate 1 on which a semiconductor element is formed.
Deposit klO00A to 100OOA. Next, Figure 1 (
As shown in bl, a photosensitive organic film 4. For example, in the case of photosensitive polyurethane, pre-baking is performed in an N3 atmosphere at around 100 DEG C. after applying Do4 to a thickness of about 0.5 .mu.m to 20 .mu.m. Next, as shown in Figure 1 (tc), the normally used lightless development is carried out to remove the polyimide 11a on the lead-out electrode part, and the polyimide is post-baked to remove the photosensitive components and residual solvent of the film. . Next, as shown in FIG.
The silicon oxide film is removed by dry etching using.
次に第２図に示す様に上記方法により作成された半導体
基板をペレッタイズし半導体チップ５をリードフレーム
６にダイマウントし次にボンディングし樹脂８で封止す
る。Next, as shown in FIG. 2, the semiconductor substrate produced by the above method is pelletized, a semiconductor chip 5 is die-mounted on a lead frame 6, and then bonded and sealed with a resin 8.
尚本製造方法において第１のパッジベージ曹ン膜として
シリコン窒化膜を用いたがこれに代えてＣＶＤ法による
シリコン酸化膜、ＰＳＧ膜あるいはこれらの複合＠を用
いる事は容易に類推出来る。In this manufacturing method, a silicon nitride film is used as the first padded carbon film, but it can be easily inferred that a silicon oxide film formed by a CVD method, a PSG film, or a composite thereof may be used instead.
また感光性ポリイミドにかえてゴム系ホトレジストを用
いる事も可能である。It is also possible to use a rubber photoresist instead of photosensitive polyimide.
〔実施ガ２〕
第３図は本発明の絹２の実施例を説明するための半導体
装置の断面図である。[Embodiment 2] FIG. 3 is a sectional view of a semiconductor device for explaining an embodiment of silk 2 of the present invention.
本実施例は第１の実施例で示したパッンベーシ曹ン映の
形成方法で製造された半導体基板をペレッタイズし半導
体チップ５をＣＯＢ基板にダイマウントし次にボンディ
ングし樹脂８を滴下する。In this embodiment, a semiconductor substrate manufactured by the method of forming a pan-based coating shown in the first embodiment is pelletized, a semiconductor chip 5 is die-mounted on a COB substrate, and then bonded and a resin 8 is dropped.
以上説明したように本発明はパッシベーション膜の製造
方法において最上層の膜として感光性ポリイミドを用い
る事により引き出し電極部を開口する際にフォ） ＩＪ
ングラフィ一工程が１回で済みかつ下層バッシペーシッ
ン膜のエツチングマスクとして用いた感光性ポリイミド
を残す事によりモールドパッケージの樹脂による応力緩
和材として利用出来る効果がある。As explained above, the present invention uses a photosensitive polyimide as the top layer film in a method for manufacturing a passivation film, so that it can be used when opening an extraction electrode part.
One printing process is required, and by leaving the photosensitive polyimide used as an etching mask for the lower bash pacing film, the resin can be used as a stress relieving material for the molded package.
第１図ｔａｌ〜（ｄｌは本発明の一実施例を説明する為
の工程ｊ１に示した半導体チップの断面図、第２図ｒｉ
組立後の半導体装置の断面図、第３図ｒｉ第２の実施例
の組立後の半導体装置の断面図、第４図（ａｌ〜（ｅ）
ｄ従来のパッジベージ１ン換の製造方法を工程順に示し
た半導体チップの断面図、第５図は従来の組立後の半碑
体釦ｉ°断面図である。
１・・・・・・半導体基板、２・・・・・・アルば電極
、３・・・・・・シリコン窒化膜、４・・・・・・感光
性ポリ、イぐド、５・・・・・・半導体チップ、６・・
・・・・リードフレーム、７−・・・ボンディングワイ
ヤー、８・・・・・・樹脂、９・・団・ＣＯＢ基版、１
０・・・・・・樹脂枠。
第１図
菊３図
躬４図Figure 1 tal~(dl is a sectional view of the semiconductor chip shown in step j1 for explaining one embodiment of the present invention, Figure 2 ri
Cross-sectional view of the semiconductor device after assembly, FIG. 3ri Cross-sectional view of the semiconductor device after assembly of the second embodiment, FIGS.
d A cross-sectional view of a semiconductor chip showing the conventional manufacturing method for one-piece padge page in the order of steps, and FIG. 5 is a cross-sectional view of a conventional half-shaped button after assembly. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Album electrode, 3...Silicon nitride film, 4...Photosensitive poly, Igudo, 5... ...semiconductor chip, 6...
...Lead frame, 7--Bonding wire, 8--Resin, 9--Group/COB base plate, 1
0...Resin frame. Figure 1 Chrysanthemum Figure 3 Chrysanthemum Figure 4
Claims (1)
成する工程と前記無機系絶縁膜上に感光性有機膜を形成
する工程と前記感光性有機膜の一部分を開口する工程と
前記感光性有機膜をマスクとして前記無機系絶縁膜をエ
ッチングする工程と前記感光性有機膜が前記無機系絶縁
膜上に延在する状態で前記半導体基板をペレットに分け
マウント、ボンディング、樹脂封止する工程を含むこと
を特徴とする半導体装置の製造方法。A step of forming an inorganic insulating film on a semiconductor substrate having a semiconductor element, a step of forming a photosensitive organic film on the inorganic insulating film, a step of opening a part of the photosensitive organic film, and a step of opening the photosensitive organic film. etching the inorganic insulating film using as a mask, and dividing the semiconductor substrate into pellets with the photosensitive organic film extending over the inorganic insulating film, mounting, bonding, and sealing with a resin. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10739687A JPS63271939A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10739687A JPS63271939A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63271939A true JPS63271939A (en) | 1988-11-09 |
Family
ID=14458081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10739687A Pending JPS63271939A (en) | 1987-04-28 | 1987-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63271939A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6784528B2 (en) * | 2001-12-14 | 2004-08-31 | Sharp Kabushiki Kaisha | Semiconductor device with plating wiring connecting IC electrode pad to terminal |
| US6989334B2 (en) | 1998-03-20 | 2006-01-24 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239018A (en) * | 1985-08-14 | 1987-02-20 | Mitsubishi Electric Corp | Formation of passivation film |
-
1987
- 1987-04-28 JP JP10739687A patent/JPS63271939A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239018A (en) * | 1985-08-14 | 1987-02-20 | Mitsubishi Electric Corp | Formation of passivation film |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6989334B2 (en) | 1998-03-20 | 2006-01-24 | Renesas Technology Corp. | Manufacturing method of a semiconductor device |
| US7247576B2 (en) | 1998-03-20 | 2007-07-24 | Renesas Technology Corp. | Method of manufacturing a semiconductor device |
| US7678706B2 (en) | 1998-03-20 | 2010-03-16 | Renesas Technology Corp. | Method of manufacturing a semiconductor device |
| US6784528B2 (en) * | 2001-12-14 | 2004-08-31 | Sharp Kabushiki Kaisha | Semiconductor device with plating wiring connecting IC electrode pad to terminal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4328262A (en) | Method of manufacturing semiconductor devices having photoresist film as a permanent layer | |
| TWI269374B (en) | Method for making a semiconductor device | |
| US6632700B1 (en) | Method to form a color image sensor cell while protecting the bonding pad structure from damage | |
| US9082681B2 (en) | Adhesive bonding technique for use with capacitive micro-sensors | |
| KR900001656B1 (en) | Forming method of passivation film | |
| JPS63271939A (en) | Manufacture of semiconductor device | |
| JP2002270735A (en) | Semiconductor device and its manufacturing method | |
| US6174824B1 (en) | Post-processing a completed semiconductor device | |
| JPS59232424A (en) | Semiconductor device and manufacture of the same | |
| JPH038581B2 (en) | ||
| JPH0661233A (en) | Manufacture of semiconductor device | |
| JP2003282614A (en) | Semiconductor device and its manufacturing method | |
| JP3726578B2 (en) | Manufacturing method of semiconductor device | |
| JP2000323605A (en) | Semiconductor device, manufacture thereof, electronic device using the same | |
| JP6927430B2 (en) | Manufacturing method of semiconductor devices | |
| JP3077372B2 (en) | Method of manufacturing bump electrode for integrated circuit device | |
| JP2004063729A (en) | Electrode structure and its forming method | |
| JPS62179136A (en) | Semiconductor device and manufacture thereof | |
| JPS61231758A (en) | Solid-state image pickup device | |
| JPS62232962A (en) | Solid-state image sensing device | |
| JPS63269554A (en) | Semiconductor device | |
| JPS6153858B2 (en) | ||
| JPS6190450A (en) | Semiconductor device | |
| JPS6128212B2 (en) | ||
| JPH0738468B2 (en) | Method of manufacturing magnetoresistive element |