JPS60137049A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPS60137049A JPS60137049A JP58251388A JP25138883A JPS60137049A JP S60137049 A JPS60137049 A JP S60137049A JP 58251388 A JP58251388 A JP 58251388A JP 25138883 A JP25138883 A JP 25138883A JP S60137049 A JPS60137049 A JP S60137049A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- island
- semiconductor device
- leads
- sealed semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体チップを載せる矩形のアイランドに平行
または直角な面上に複数の外部リードを並列に配置した
樹脂封止型半導体装置、すなわちＤ Ｉ Ｐ （Ｄｕａ
ｌ工ｎ１ｉｎｅ Ｐａｃｋａｇｅ ）、フラットパッケ
ージ、Ｓ工Ｌ （Ｓｉｎｇｌｅ工ｎ１ｉｎｅ ）等の樹
脂封止型半導体装置に関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device in which a plurality of external leads are arranged in parallel on a plane parallel to or perpendicular to a rectangular island on which a semiconductor chip is mounted, that is, a D I P (Dua
The present invention relates to resin-sealed semiconductor devices such as single package, flat package, and single package.
第１図は半導体装置を樹脂封止する樹脂封止装置である
。半導体装置を樹脂封止するための樹脂は、ボットｌか
ら各ランナλを通って金型３に送られる。金型３内に樹
脂が充填されると金型３によシ封止される。例えばＤ工
Ｐの半導体装置をこの樹脂封止装置で樹脂封止する場合
、ポンディンダ終了後の半導体装置ＩＯを長方形の金型
３に外部リードを短辺に平行になるように配置しておこ
々う。金型３の樹脂入口端ｔは金型３の短辺に設けられ
ておシ、樹脂流入方向は金型３の長辺に沿っている。し
たがって樹脂流入方向は第２図において矢印で示すよう
になり、半導体テップ／／が載せられたアイランド７．
２に対して直角になる。すると樹脂の流れに対してアイ
ランド／２の抵抗が大きく、アイランドノコが持ちあが
ったシ変形したりするという問題があった。また半導体
テップ／／と内部リード１３とを結ぶボンディンダワイ
ヤ／Ｑも、流入する樹脂によシ流されたシ切断されたシ
するという問題があった。FIG. 1 shows a resin sealing device for resin-sealing a semiconductor device. Resin for resin-sealing the semiconductor device is sent from the bot 1 to the mold 3 through each runner λ. When the mold 3 is filled with resin, it is sealed by the mold 3. For example, when a D/P semiconductor device is resin-sealed using this resin sealing device, the semiconductor device IO after the ponding process is placed in a rectangular mold 3 with the external leads parallel to the short sides. cormorant. The resin inlet end t of the mold 3 is provided on the short side of the mold 3, and the resin inflow direction is along the long side of the mold 3. Therefore, the resin inflow direction is as shown by the arrow in FIG. 2, and the island 7.
It is perpendicular to 2. Then, there was a problem that the island/2 had a large resistance against the flow of the resin, and the island saw was lifted up and deformed. Further, there was a problem in that the bonder wire /Q connecting the semiconductor chip // and the internal lead 13 was also washed away by the inflowing resin and was cut.
本発明は上記事情を考慮してなされたもので、半導体チ
ップを載せるアイランドが変形したシポンディングワイ
ヤが切れたりし々い樹脂封止型半導体装置を提供するこ
とを目的とする。The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a resin-sealed semiconductor device in which an island on which a semiconductor chip is placed is deformed and the bonding wire is easily cut.
この目的を達成するために本発明による樹脂封止型半導
体装置は、半導体チップを載せるアイランドの辺を外部
リードに対し約９〜７０度傾けたことを特徴とする。In order to achieve this object, the resin-sealed semiconductor device according to the present invention is characterized in that the sides of the island on which the semiconductor chip is mounted are inclined at about 9 to 70 degrees with respect to the external leads.
第２図に本発明の一実施例による樹脂封止型半導体装置
を示す。２列にり本ずつ並列に配された外部リードｌＳ
と、これに連結する内部リード１３と、タイツ々／乙に
支えられたアイランド／Ｕとを有するリードフレームを
用いるが、本実施例のアイランド／２は、外部リード／
Ｓに対しくｚ、ｒ傾いて設けられている点に特徴がある
。このアイランド１２には半導体チップ／／が載せられ
、半導体テップ／／と内部リード１３とはポンディング
ワイヤ／ｌＩによシミ気菌に接続される。FIG. 2 shows a resin-sealed semiconductor device according to an embodiment of the present invention. External leads LS arranged in parallel in two rows
A lead frame is used which has an inner lead 13 connected to this, and an island/U supported by tights/O.In this embodiment, the island/2 is connected to the outer lead/U.
It is distinctive in that it is provided at an angle of z and r with respect to S. A semiconductor chip // is mounted on this island 12, and the semiconductor chip // and internal leads 13 are connected to the stain by bonding wires /lI.
このようにアイランド／２を傾けて設けることによシ、
第３図に矢印で示すように樹脂が流入してきても抵抗が
小さくてすみ、アイランド７．２の変形を防止できる。By tilting the island/2 in this way,
Even if the resin flows in as shown by the arrow in FIG. 3, the resistance is small and deformation of the island 7.2 can be prevented.
またボンディングワイヤ／ｌが切断されたシすることも
防止でき゛る。It is also possible to prevent the bonding wire /l from being cut.
先の実施例ではアイランド／コをグｒ傾けたが、樹脂流
入に対する抵抗を小さくできればよく約９〜７０度の範
囲が有効である。In the previous embodiment, the island/co was tilted to a degree, but the range of about 9 to 70 degrees is effective as long as the resistance to resin inflow can be made small.
また先の実施例ではＤ工Ｐの半導体装置であったが、フ
ラットパッケージやＳ工Ｌパッケージ等の他の樹脂封止
型半導体装置においても、樹脂流入方向に対してアイラ
ンドを傾けることによυ本発明の適用か可能である。In addition, although the previous example was a D-process P semiconductor device, other resin-sealed semiconductor devices such as flat packages and S-process L packages can also be used by tilting the island with respect to the resin inflow direction. Application of the present invention is possible.
以上の通シ本発明によれは半導体ナツプのアイランドの
変形やボンディングワイヤの切断を防止でき、信頼性の
高い樹脂封止型半導体装置を提供できる。In summary, according to the present invention, deformation of the island of the semiconductor nap and breakage of the bonding wire can be prevented, and a highly reliable resin-sealed semiconductor device can be provided.
第１図は樹脂封止装置の平面図、第２図は従来の樹脂封
止型半導体装置の平面図、第３図は本発明の一実施例に
よる樹脂制止型半導体装置の平面図である。
／・・・ポット、２・・・ランナ、３・・・金型、≠・
・・樹脂入口端、１０・半導体装置、ｌ／・・・半導体
チップ、／２・・アイランド、／３ 内部リード、／４
’・・ボンディングワイヤ。
出凰入代理人 猪 股 清
８Ｊ且FIG. 1 is a plan view of a resin-sealed device, FIG. 2 is a plan view of a conventional resin-sealed semiconductor device, and FIG. 3 is a plan view of a resin-sealed semiconductor device according to an embodiment of the present invention. /...pot, 2...runner, 3...mold, ≠・
・・Resin inlet end, 10・Semiconductor device, l/・・・Semiconductor chip, /2・・Island, /3 Internal lead, /4
'...Bonding wire. Entry/Department Agent Kiyoshi Inomata 8J
Claims (1)
角な面上に複数の外部リードを並列に設けた樹脂封止型
半導体装置において、 前記アイランドの辺を前記外部リードに対して約２０〜
７０度傾けたことを特徴とする樹脂封止型半導体装置。[Claims] In a resin-sealed semiconductor device in which a plurality of external leads are provided in parallel on a surface parallel to or perpendicular to a rectangular island on which a semiconductor tip is mounted, a side of the island is set relative to the external lead. Approximately 20~
A resin-sealed semiconductor device characterized by being tilted at 70 degrees.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58251388A JPS60137049A (en) | 1983-12-26 | 1983-12-26 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58251388A JPS60137049A (en) | 1983-12-26 | 1983-12-26 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60137049A true JPS60137049A (en) | 1985-07-20 |
Family
ID=17222095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58251388A Pending JPS60137049A (en) | 1983-12-26 | 1983-12-26 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60137049A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525180B2 (en) | 2005-10-24 | 2009-04-28 | Panasonic Corporation | Semiconductor mount substrate, semiconductor device and method of manufacturing semiconductor package |
| CN110265379A (en) * | 2019-06-26 | 2019-09-20 | 深圳市尚明精密模具有限公司 | The tilting IC down-lead bracket in base island and encapsulation IC |
| CN110265379B (en) * | 2019-06-26 | 2024-07-16 | 富满微电子集团股份有限公司 | IC lead support with inclined base island and packaged IC |
-
1983
- 1983-12-26 JP JP58251388A patent/JPS60137049A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525180B2 (en) | 2005-10-24 | 2009-04-28 | Panasonic Corporation | Semiconductor mount substrate, semiconductor device and method of manufacturing semiconductor package |
| CN110265379A (en) * | 2019-06-26 | 2019-09-20 | 深圳市尚明精密模具有限公司 | The tilting IC down-lead bracket in base island and encapsulation IC |
| CN110265379B (en) * | 2019-06-26 | 2024-07-16 | 富满微电子集团股份有限公司 | IC lead support with inclined base island and packaged IC |
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