JPH0476504B2 - - Google Patents
Info
- Publication number
- JPH0476504B2 JPH0476504B2 JP61008379A JP837986A JPH0476504B2 JP H0476504 B2 JPH0476504 B2 JP H0476504B2 JP 61008379 A JP61008379 A JP 61008379A JP 837986 A JP837986 A JP 837986A JP H0476504 B2 JPH0476504 B2 JP H0476504B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- metal member
- oxide film
- integrated circuit
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止型半導体装置の金属部材
の表面処理に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to surface treatment of metal members of resin-sealed semiconductor devices.
第４図は、従来の集積回路フレームを示す平面
図である。図において、１は集積回路フレーム、
２はパツケージの外形線、３は集積回路素子、４
は集積回路素子３を載せるダイパツト、５はリー
ド、６は集積回路素子３と、リード５を接続する
金線、７は樹脂の流れをせき止めるタイバであ
る。
FIG. 4 is a plan view showing a conventional integrated circuit frame. In the figure, 1 is an integrated circuit frame;
2 is the outline of the package, 3 is the integrated circuit element, and 4 is the outline of the package.
5 is a die pad on which the integrated circuit element 3 is mounted, 5 is a lead, 6 is a gold wire connecting the integrated circuit element 3 and the lead 5, and 7 is a tie bar for blocking the flow of resin.
従来の技術では、前記集積回路フレームと樹脂
との接着力にばらつきがあり、不均一なので熱ス
トレスによる応力が弱い場所に集中し、クラツク
が発生することがある。これが原因となり界面ひ
び割れ、金線切れや、クラツクから水分が浸入す
るため耐湿性等の品質が劣化する問題があつた。
In the conventional technology, the adhesive strength between the integrated circuit frame and the resin varies and is non-uniform, so stress due to thermal stress is concentrated in weak areas, and cracks may occur. This caused problems such as interfacial cracks, gold wire breaks, and moisture infiltration through the cracks, resulting in deterioration of quality such as moisture resistance.
この発明は、上記のようにな問題点を改善する
ためになされたもので、前記界面での接着力を向
上させて均一にし、信頼度の高い製品を得ること
を目的とする。 This invention was made to improve the above-mentioned problems, and aims to improve and make the adhesive force at the interface uniform, thereby obtaining a highly reliable product.
この発明に係る樹脂封止型半導体装置は、半導
体素子と、半導体素子を載置すると共に外部との
信号の授受を行なう金属部材と、金属部材の表面
に形成された酸化シリコン膜と、半導体素子およ
び金属部材を包囲して設けられた樹脂とを備えた
ものである。
A resin-sealed semiconductor device according to the present invention includes a semiconductor element, a metal member on which the semiconductor element is mounted and which transmits and receives signals to and from the outside, a silicon oxide film formed on the surface of the metal member, and a semiconductor element. and a resin provided surrounding the metal member.
この発明においては、金属部材表面に酸化シリ
コン膜が設けられているので、熱的に安定で、ワ
イヤボンデイング等の熱処理による金属部材の酸
化を防止し、樹脂との接着力を向上させる。
In this invention, since the silicon oxide film is provided on the surface of the metal member, it is thermally stable, prevents oxidation of the metal member due to heat treatment such as wire bonding, and improves adhesive strength with resin.
第１図は、この発明の一実施例を示す平面図で
あり、第３図と同一符号は、同一のものを示す。
FIG. 1 is a plan view showing an embodiment of the present invention, and the same reference numerals as in FIG. 3 indicate the same parts.
フレーム１の表面と裏面の全面に蒸着により酸
化膜８として酸化シリコン膜を生成したのち、ダ
イパツト４に集積回路素子３を接着し、金線６で
集積回路素子３とリード５を接続し、これらを樹
脂で封止する。 After forming a silicon oxide film as an oxide film 8 on the entire surface and back surface of the frame 1, the integrated circuit element 3 is adhered to the die pad 4, and the integrated circuit element 3 and the leads 5 are connected with gold wires 6. Seal with resin.
第２図は、この発明の他の実施例を示す平面図
であり酸化膜８をパツケージ外形線２で囲まれた
範囲、すなわち図示しない樹脂で封止される金属
部材の部分に生成されたものである。 FIG. 2 is a plan view showing another embodiment of the present invention, in which an oxide film 8 is formed in the area surrounded by the package outline 2, that is, in the part of the metal member to be sealed with a resin (not shown). It is.
第３図はこの発明の他の実施例を示す平面図で
あり、第１図、第２図のように表と裏と同じ範囲
に酸化膜８を生成するのではなく、第２図の実施
例の表側の金線を接続する部分であるボンデイン
グエリア９とダイパツト４上に集積回路素子３が
載る部分を除いて酸化膜８を生成したものであ
る。 FIG. 3 is a plan view showing another embodiment of the present invention, in which the oxide film 8 is not formed in the same area on the front and back as in FIGS. 1 and 2, but in the embodiment shown in FIG. In this example, an oxide film 8 is formed except for the bonding area 9 where the gold wires are connected on the front side and the area where the integrated circuit element 3 is placed on the die pad 4.
〔発明の効果〕
以上の様に、この発明は金属部材の表面に酸化
シリコン膜を設けて樹脂封止するようにしたので
金属部材と樹脂との接着力が増加するという効果
がある。[Effects of the Invention] As described above, the present invention has the effect of increasing the adhesive force between the metal member and the resin because the silicon oxide film is provided on the surface of the metal member and the resin is sealed.
第１図はこの発明の一実施例を示す平面図。第
２図、第３図はそれぞれこの発明の他の実施例を
示す平面図、第４図は従来の樹脂封止型半導体装
置に使用される金属部材を示す。
図において１は集積回路フレーム、２はパツケ
ージ外形線、３は集積回路素子、４はダイパツ
ト、５はリード、６は金線、７はタイバ、８は酸
化膜である。図中、同一符号は同一、又は相当部
分を示す。
FIG. 1 is a plan view showing an embodiment of the present invention. FIGS. 2 and 3 are plan views showing other embodiments of the present invention, and FIG. 4 shows a metal member used in a conventional resin-sealed semiconductor device. In the figure, 1 is an integrated circuit frame, 2 is a package outline, 3 is an integrated circuit element, 4 is a die pad, 5 is a lead, 6 is a gold wire, 7 is a tie bar, and 8 is an oxide film. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
共に外部との信号の授受を行なう金属部材と、前
記金属部材の表面に形成された酸化シリコン膜
と、前記半導体素子および金属部材を包囲して設
けられた樹脂とを備えたことを特徴とする樹脂封
止型半導体装置。 ２ 酸化シリコン膜は、蒸着によつて形成される
ことを特徴とする特許請求の範囲第１項記載の樹
脂封止型半導体装置。[Scope of Claims] 1. A semiconductor element, a metal member on which the semiconductor element is mounted and which transmits and receives signals to and from the outside, a silicon oxide film formed on the surface of the metal member, and a semiconductor element and the metal member. 1. A resin-sealed semiconductor device comprising: a resin surrounding a member. 2. The resin-sealed semiconductor device according to claim 1, wherein the silicon oxide film is formed by vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP837986A JPS62166553A (en) | 1986-01-18 | 1986-01-18 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP837986A JPS62166553A (en) | 1986-01-18 | 1986-01-18 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62166553A JPS62166553A (en) | 1987-07-23 |
| JPH0476504B2 true JPH0476504B2 (en) | 1992-12-03 |
Family
ID=11691587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP837986A Granted JPS62166553A (en) | 1986-01-18 | 1986-01-18 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62166553A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0587966U (en) * | 1992-04-28 | 1993-11-26 | シャープ株式会社 | Lead frame |
| US6166446A (en) * | 1997-03-18 | 2000-12-26 | Seiko Epson Corporation | Semiconductor device and fabrication process thereof |
| JP5761280B2 (en) * | 2013-09-12 | 2015-08-12 | 株式会社デンソー | Semiconductor package and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60201651A (en) * | 1984-03-26 | 1985-10-12 | Hitachi Cable Ltd | Lead frame for semiconductor |
-
1986
- 1986-01-18 JP JP837986A patent/JPS62166553A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60201651A (en) * | 1984-03-26 | 1985-10-12 | Hitachi Cable Ltd | Lead frame for semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62166553A (en) | 1987-07-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R360 | Written notification for declining of transfer of rights |
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|
| R360 | Written notification for declining of transfer of rights |
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|
| R371 | Transfer withdrawn |
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|
| S111 | Request for change of ownership or part of ownership |
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|
| R350 | Written notification of registration of transfer |
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|
| EXPY | Cancellation because of completion of term |