JPH02140700U - - Google Patents

Info

Publication number
JPH02140700U
JPH02140700U JP1989046627U JP4662789U JPH02140700U JP H02140700 U JPH02140700 U JP H02140700U JP 1989046627 U JP1989046627 U JP 1989046627U JP 4662789 U JP4662789 U JP 4662789U JP H02140700 U JPH02140700 U JP H02140700U
Authority
JP
Japan
Prior art keywords
address
data
program counter
prom
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989046627U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989046627U priority Critical patent/JPH02140700U/ja
Priority to US07/510,137 priority patent/US5239656A/en
Priority to EP90107349A priority patent/EP0393626B1/en
Priority to DE69027805T priority patent/DE69027805T2/de
Priority to KR1019900005600A priority patent/KR900016861A/ko
Publication of JPH02140700U publication Critical patent/JPH02140700U/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/74Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22Microcontrol or microprogram arrangements
    • G06F9/24Loading of the microprogram
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Description

【図面の簡単な説明】
第1図は本考案の実施例を示すPROM内蔵マ
イクロコンピユータの要部構成図、第2図は従来
のPROM内蔵マイクロコンピユータの機能ブロ
ツク図、第3図は第2図の読出し命令動作を示す
図、第4図は第2図のエラー訂正フローチヤート
、第5図は第2図の比較命令動作を示す図、第6
図は第1図中のプログラムカウンタの要部回路図
、第7図は第2図中のワンタイムPROMの構成
図、第8図は第1図の読出し命令動作を示す図、
第9図は第1図の比較命令動作を示す図である。 2……内部データバス、4……命令デコーダ・
エンコーダ、6,7……一時レジスタ、8……A
LU、12……スタツクポインタ、13……デー
タポインタ、14…RAM、15A……プログラ
ムカウンタ、16……ROM、17……BAペア
レジスタ、18……ワンタイムPROM、21…
…アドレス変換回路。

Claims (1)

  1. 【実用新案登録請求の範囲】 単一のデータをプログラムカウンタで指定され
    るPROMの第1のアドレス及びその第1のアド
    レスと一定の関係にある第2のアドレスに書込む
    手段と、 前記プログラムカウンタで指定されるPROM
    の第1のアドレスの第1のデータと第2のアドレ
    スの第2のデータをそれぞれ読出す手段と、 前記読出された第1と第2のデータの論理積を
    とり単一の出力データとする手段とを備えたPR
    OM内蔵マイクロコンピユータにおいて、 制御信号により前記第1のアドレスを前記第2
    のアドレスへ変換するアドレス変換回路を前記プ
    ログラムカウンタに設け、 前記読出された第1と第2のデータの論理積を
    プリチヤージ方式のデータバス上で求める手段を
    設けたことを特徴とするPROM内蔵マイクロコ
    ンピユータ。
JP1989046627U 1989-04-20 1989-04-20 Pending JPH02140700U (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1989046627U JPH02140700U (ja) 1989-04-20 1989-04-20
US07/510,137 US5239656A (en) 1989-04-20 1990-04-17 Semiconductor memory device for self-correcting data output errors by taking the logical product of first and second identical data outputs
EP90107349A EP0393626B1 (en) 1989-04-20 1990-04-18 Microcomputer with a built-in prom
DE69027805T DE69027805T2 (de) 1989-04-20 1990-04-18 Mikrorechner mit eingebautem PROM
KR1019900005600A KR900016861A (ko) 1989-04-20 1990-04-20 프롬(Programmable ROM) 내장 마이크로 컴퓨터

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989046627U JPH02140700U (ja) 1989-04-20 1989-04-20

Publications (1)

Publication Number Publication Date
JPH02140700U true JPH02140700U (ja) 1990-11-26

Family

ID=12752527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989046627U Pending JPH02140700U (ja) 1989-04-20 1989-04-20

Country Status (5)

Country Link
US (1) US5239656A (ja)
EP (1) EP0393626B1 (ja)
JP (1) JPH02140700U (ja)
KR (1) KR900016861A (ja)
DE (1) DE69027805T2 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04162300A (ja) * 1990-10-26 1992-06-05 Nec Corp 半導体メモリ
US5539697A (en) * 1994-08-03 1996-07-23 Bi-Search Corporation Method and structure for using defective unrepairable semiconductor memory
DE19846461B4 (de) * 1997-10-08 2006-05-11 Hitachi, Ltd. Sensoreinstellschaltung
US6009012A (en) * 1998-06-03 1999-12-28 Motorola Inc. Microcontroller having a non-volatile memory and a method for selecting an operational mode
US6594192B1 (en) * 2000-08-31 2003-07-15 Stmicroelectronics, Inc. Integrated volatile and non-volatile memory
US8201291B2 (en) 2007-09-25 2012-06-19 Kids Ii, Inc. Redundant support feature for bassinet assembly and play yard combination

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074034A (ja) * 1983-09-30 1985-04-26 Toshiba Corp パイプライン制御方式
JPS6151695A (ja) * 1984-08-22 1986-03-14 Hitachi Ltd 半導体集積回路装置
JPH0787032B2 (ja) * 1985-07-08 1995-09-20 日本電気アイシ−マイコンシステム株式会社 半導体記憶装置
JPH0194599A (ja) * 1987-10-05 1989-04-13 Mitsubishi Electric Corp 半導体記憶装置
JPH01173147A (ja) * 1987-12-28 1989-07-07 Oki Electric Ind Co Ltd Prom内蔵マイクロコンピュータ

Also Published As

Publication number Publication date
DE69027805D1 (de) 1996-08-22
US5239656A (en) 1993-08-24
EP0393626B1 (en) 1996-07-17
KR900016861A (ko) 1990-11-14
EP0393626A2 (en) 1990-10-24
DE69027805T2 (de) 1997-03-06
EP0393626A3 (en) 1991-09-25

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