JPH0213969B2 - - Google Patents
Info
- Publication number
- JPH0213969B2 JPH0213969B2 JP59215879A JP21587984A JPH0213969B2 JP H0213969 B2 JPH0213969 B2 JP H0213969B2 JP 59215879 A JP59215879 A JP 59215879A JP 21587984 A JP21587984 A JP 21587984A JP H0213969 B2 JPH0213969 B2 JP H0213969B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- value
- drift
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21587984A JPS6194416A (ja) | 1984-10-15 | 1984-10-15 | 多値信号識別回路 |
US06/702,762 US4602374A (en) | 1984-02-27 | 1985-02-19 | Multi-level decision circuit |
EP85101929A EP0153708B1 (fr) | 1984-02-27 | 1985-02-22 | Circuit de décision à niveaux multiples |
CA000475068A CA1241390A (fr) | 1984-02-27 | 1985-02-25 | Circuit de prise de decision multiniveau |
AU39178/85A AU560059B2 (en) | 1984-02-27 | 1985-02-26 | Multilevel decision circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21587984A JPS6194416A (ja) | 1984-10-15 | 1984-10-15 | 多値信号識別回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6194416A JPS6194416A (ja) | 1986-05-13 |
JPH0213969B2 true JPH0213969B2 (fr) | 1990-04-05 |
Family
ID=16679768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21587984A Granted JPS6194416A (ja) | 1984-02-27 | 1984-10-15 | 多値信号識別回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6194416A (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1271996A (fr) * | 1988-03-09 | 1990-07-24 | David Lawrence Lynch | Appareil et methode de codage a gain variable |
JP2814937B2 (ja) * | 1994-12-28 | 1998-10-27 | 日本電気株式会社 | 直並列型a/d変換器のオフセット補正方式 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5027346A (fr) * | 1973-04-11 | 1975-03-20 | ||
JPS58120351A (ja) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | 直流ずれ補償方式 |
-
1984
- 1984-10-15 JP JP21587984A patent/JPS6194416A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5027346A (fr) * | 1973-04-11 | 1975-03-20 | ||
JPS58120351A (ja) * | 1982-01-13 | 1983-07-18 | Fujitsu Ltd | 直流ずれ補償方式 |
Also Published As
Publication number | Publication date |
---|---|
JPS6194416A (ja) | 1986-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4706265A (en) | Code converting system and method for band compression of digital signals | |
US4602374A (en) | Multi-level decision circuit | |
KR100333006B1 (ko) | 서브-레인징아날로그-디지탈변환기 | |
US5243625A (en) | Receiver for multivalued digital signals | |
KR101153541B1 (ko) | 디지털 전원 제어 시스템들을 위한 자기 추적 adc | |
US7061416B2 (en) | Adaptive-type sigma-delta A/D converter | |
JPH0420523B2 (fr) | ||
US6081565A (en) | Amplitude based coarse automatic gain control circuit | |
JPH0213969B2 (fr) | ||
US5363100A (en) | Digital peak-threshold tracking method and apparatus | |
JPH09107288A (ja) | A/d変換器の最適ダイナミックレンジを維持するa/d変換器の基準レベルの調整回路及び方法 | |
JPH1151977A (ja) | インバータ回路 | |
US20040207550A1 (en) | Parallel a/d converter | |
JPS59144218A (ja) | 多値識別器 | |
JPH07226683A (ja) | A/d変換装置 | |
JPH0661863A (ja) | 直流ディザ入力型δς変調型ad変換器 | |
JPS61194918A (ja) | 多値識別回路 | |
JP2766876B2 (ja) | グリッチパターン検出回路 | |
JPH0478213B2 (fr) | ||
JP2689714B2 (ja) | しきい値制御回路 | |
JPS60180259A (ja) | 多値識別回路 | |
JPH0611122B2 (ja) | 多値識別回路 | |
JPS60125042A (ja) | 自動レベル調整回路 | |
JPS61296829A (ja) | ブリツジドタツプ等化器 | |
JPH0257037A (ja) | 最適識別レベル制御方式 |