JPH02105430A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02105430A JPH02105430A JP63258674A JP25867488A JPH02105430A JP H02105430 A JPH02105430 A JP H02105430A JP 63258674 A JP63258674 A JP 63258674A JP 25867488 A JP25867488 A JP 25867488A JP H02105430 A JPH02105430 A JP H02105430A
- Authority
- JP
- Japan
- Prior art keywords
- mounting material
- semiconductor element
- semiconductor device
- powder
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 36
- 229920001721 polyimide Polymers 0.000 claims abstract description 7
- 239000000843 powder Substances 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 3
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000009719 polyimide resin Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052582 BN Inorganic materials 0.000 abstract description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- 239000004593 Epoxy Substances 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000006023 eutectic alloy Substances 0.000 description 5
- 238000003909 pattern recognition Methods 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体素子を回路基
板に固着した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor element is fixed to a circuit board.
従来、半導体装置における半導体素子のマウント材とし
ては、Ａｕ−３ｉ共晶合金やエポキシ系もしくはポリイ
ミド系樹脂に銀粉末を含有させた銀ペーストをマウント
材として使用していた。Conventionally, as a mounting material for a semiconductor element in a semiconductor device, a silver paste made of an Au-3i eutectic alloy, an epoxy resin, or a polyimide resin containing silver powder has been used as a mounting material.
上述した従来のマウント材によるマウント方法としては
、Ａｕ−３ｉ共晶合金を用いる場合は、あらかじめＡｕ
メツキを施こしである回路基板の半導体固着部（以下ア
イランド部と記す）に、Ａｕ−３ｉ （Ｓｔを１〜３％
含有）の片を置き、その上に半導体素子をのせた状態で
窒素雰囲気中にて加熱振動を加えることにより、Ａｕ−
３ｉ共晶合金を形成し、半導体素子をアイランド部に固
着していた。しかしながらこの方法では、マウント材で
あるＡｕ−５ｉ片の酸化性が高い為、加熱時の雰囲気中
にわずかでも酸素が存在すると、マウント材が酸化して
しまい、アイランド部と半導体素子の裏面とを一様にＡ
ｕ−３ｔ共晶合金で固着することが出来ず、著しい場合
には、半導体素子にくわわる熱ストレスの為に、半導体
素子にクラック等が発生することがあった。As for the mounting method using the conventional mounting material mentioned above, when using Au-3i eutectic alloy, Au
Au-3i (St of 1 to 3%
By placing a piece of Au-containing) and applying heating vibration in a nitrogen atmosphere with a semiconductor element placed on it, Au-
A 3i eutectic alloy was formed, and the semiconductor element was fixed to the island portion. However, in this method, since the Au-5i piece that is the mounting material has a high oxidizing property, if even a small amount of oxygen exists in the atmosphere during heating, the mounting material will oxidize, and the island part and the back side of the semiconductor element will be damaged. Uniformly A
The u-3t eutectic alloy cannot be fixed, and in severe cases, cracks may occur in the semiconductor element due to the thermal stress applied to the semiconductor element.
又、従来のマウント材として銀ペーストを用いるマウン
ト方法では、マウント材の酸化の問題がなく、またＡｕ
−３ｉ共晶合金と比較すると弾性が高い為、熱ストレス
等による半導体素子のクラック等の発生がないという利
点を有している。しかしながら、この銀ペーストを用い
たマウント方法では、第３図に示すように、半導体素子
上の電極４ａ″と回路基板上に形成された内部型ｆ！１
ａ″とを金属細線５を用いて電気的に接続する工程（以
下ボンディング工程と記す）において、半導体素子上の
電極４ａ″をパターン認識を用いて認識する際に、銀ペ
ースト３″からの反射光３ａ″により電Ｎ４ａ”とマウ
ント材３″の反射光３ａ″部との誤認識を生じやすいと
いう欠点がある。In addition, with the conventional mounting method using silver paste as the mounting material, there is no problem of oxidation of the mounting material, and
Since it has higher elasticity than the -3i eutectic alloy, it has the advantage of not causing cracks in semiconductor elements due to thermal stress or the like. However, in this mounting method using silver paste, as shown in FIG. 3, the electrode 4a'' on the semiconductor element and the internal mold f!
a'' using a thin metal wire 5 (hereinafter referred to as a bonding step), when recognizing the electrode 4a'' on the semiconductor element using pattern recognition, the reflection from the silver paste 3'' There is a drawback that the light 3a'' tends to cause a misidentification between the electric light N4a'' and the reflected light 3a'' portion of the mount material 3''.
第１の発明の半導体装置は、回路基板上に半導体素子が
エポキシ系もしくはポリイミド系樹脂を・主成分とする
マウント材により固着されている。In the semiconductor device of the first aspect of the invention, a semiconductor element is fixed onto a circuit board using a mounting material whose main component is epoxy or polyimide resin.
第２の発明の半導体装置は、回路基板上に半導体素子が
エポキシ系もしくはポリイミド系樹脂に導電性あるいは
熱伝導性が良くかつ反射率が低い物質からなる粉末を含
有するマウント材により固着されている。In the semiconductor device of the second invention, a semiconductor element is fixed on a circuit board by a mounting material containing powder made of an epoxy or polyimide resin and a substance having good electrical conductivity or thermal conductivity and low reflectance. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は第１の発明の一実施例のサーデイツプタイプの
半導体装置の模式的断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device of a deep dip type according to an embodiment of the first invention.
この実施例では、セラミック基板１のアイランド部１ａ
は、一般に、電気的にフローティングとなっているので
、マウント材２ａには、電気的な導電性は必要としない
為、マウント材としては従来のように銀粉末を含有した
ペースト材を用いる必要はない。In this embodiment, the island portion 1a of the ceramic substrate 1 is
is generally electrically floating, so the mounting material 2a does not require electrical conductivity, so there is no need to use a paste material containing silver powder as the mounting material as in the past. do not have.
従って、銀粉末を含有しないために、ボンディング工程
において半導体素子４の電極をパターン認識にて認識す
る際に、マウント材からの反射光が低減し、誤認の発生
率を大幅に低減出来る。Therefore, since it does not contain silver powder, when recognizing the electrodes of the semiconductor element 4 by pattern recognition in the bonding process, reflected light from the mounting material is reduced, and the incidence of misidentification can be significantly reduced.
第２図は第２の発明の一実施例の模式的断面図である。FIG. 2 is a schematic cross-sectional view of an embodiment of the second invention.
この実施例は積層セラミックタイプの半導体装置であり
、マウント材３′を用い半導体素子４′がアイランドｌ
ａ’にマウントされている。This embodiment is a laminated ceramic type semiconductor device, in which a semiconductor element 4' is mounted on an island using a mounting material 3'.
It is mounted on a'.
この積層タイプのセラミックケースでは、セラミック基
板１′のアイランド部１ａ’は、ケース製造時に任意の
外部リード２′と電気的に接続することが出来るため、
カーボン粉末を含有させたマウント材３′を用いること
により、半導体素子４′の半導体基板電位を特定の電位
に保持出来る。また、マウント材３′中に含有されるカ
ーボン粉末は一般に黒色であるため、半導体素子４′上
の電極をパターン認識する際に、マウント材３′からの
反射光が従来の銀を含有するマウント材よりも少ないた
め、誤認識をおこしにくい。In this laminated type ceramic case, the island portion 1a' of the ceramic substrate 1' can be electrically connected to any external lead 2' during case manufacturing.
By using the mounting material 3' containing carbon powder, the semiconductor substrate potential of the semiconductor element 4' can be maintained at a specific potential. Furthermore, since the carbon powder contained in the mounting material 3' is generally black, when pattern recognition is performed on the electrodes on the semiconductor element 4', the reflected light from the mounting material 3' is different from that of the conventional silver-containing mount. It is less likely to be misrecognized because it is smaller than wood.
また、マウント材として低熱抵抗を要求される場合には
、窒化ホウ素、窒化アルミ１炭化ケイ素のいずれかの粉
末を含有させることによりマウント材の熱伝導率を向上
することが出来る。Furthermore, when low thermal resistance is required for the mount material, the thermal conductivity of the mount material can be improved by containing powder of either boron nitride or aluminum nitride monosilicon carbide.
ここで、マウント材に含有させるカーボン、窒化ホウ素
、窒化アルミ、炭化ケイ素等の含有量は、マウント強度
の要求より９０％（体積比）以下が望ましく、また、マ
ウント後のマウント材の厚みとしては、電気導電率、熱
伝導率の要求より、１０μｍ以下が望ましいが、本発明
では、特にこの値に限定されるものではない。Here, the content of carbon, boron nitride, aluminum nitride, silicon carbide, etc. contained in the mount material is preferably 90% (volume ratio) or less due to the requirements for mount strength, and the thickness of the mount material after mounting is , electrical conductivity, and thermal conductivity, it is desirable that the thickness be 10 μm or less, but the present invention is not particularly limited to this value.
以上説明したように、本発明は半導体装置における半導
体素子のマウント材としてエポキシ系またはポリイミド
系樹脂とその溶剤のみからなるマウント材、もしくは、
電気導電性、低熱抵抗性が要求される場合には、前記マ
ウント材にカーボン、窒化ホウ素、窒化アルミ、炭化ケ
イ素粉末を含有させたマウント材を用いることにより、
熱ス）・レスによる半導体素子のクラックを防止出来、
しかもボンディング工程におけるパターン認識の誤認識
を大幅に低減出来るという効果がある。As explained above, the present invention provides a mounting material consisting only of epoxy or polyimide resin and its solvent as a mounting material for a semiconductor element in a semiconductor device, or
When electrical conductivity and low thermal resistance are required, by using a mounting material containing carbon, boron nitride, aluminum nitride, or silicon carbide powder,
It can prevent cracks in semiconductor elements due to heat loss.
Furthermore, there is an effect that erroneous recognition in pattern recognition in the bonding process can be significantly reduced.
第１図は、本第１の発明の一実施例の模式的断面図、第
２図は本第２の発明の一実施例の模式的断面図、第３図
は従来の銀を含有するマウント材を用いて半導体素子を
マウントした半導体装置の一実施例のボンディング工程
を説明するための模式図である。
１．１’、１”・・・セラミック基板、１ａ、１ａ′・
・・アイランド部、１ａ ・・・内部電極、２゜２’、
２”・・・外部リード、３．３’、３”・・・マウント
材、３ａ″・・・マウント材からの反射光、４゜４’、
４”・・・半導体素子、４ａ ・・・電極、５・・・金
属細線、６・・・光源、７・・・テレビカメラ。FIG. 1 is a schematic sectional view of an embodiment of the first invention, FIG. 2 is a schematic sectional view of an embodiment of the second invention, and FIG. 3 is a conventional mount containing silver. FIG. 2 is a schematic diagram for explaining a bonding process of an example of a semiconductor device in which a semiconductor element is mounted using a material. 1.1', 1"...Ceramic substrate, 1a, 1a'.
... Island part, 1a ... Internal electrode, 2゜2',
2"...External lead, 3.3', 3"...Mount material, 3a"...Reflected light from mount material, 4°4',
4"...Semiconductor element, 4a...Electrode, 5...Metal thin wire, 6...Light source, 7...TV camera.
Claims (1)
リイミド系樹脂を主成分とするマウント材により固着さ
れていることを特徴とする半導体装置。 ２、回路基板上に半導体素子がエポキシ系もしくは、ポ
リイミド系樹脂に導電性あるいは熱伝導性が良くかつ反
射率が低い物質からなる粉末を含有するマウント材によ
り固着されていることを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device characterized in that a semiconductor element is fixed on a circuit board with a mounting material whose main component is epoxy or polyimide resin. 2. A semiconductor characterized in that a semiconductor element is fixed on a circuit board with a mounting material containing powder made of epoxy or polyimide resin and a substance that has good electrical conductivity or thermal conductivity and low reflectance. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63258674A JPH02105430A (en) | 1988-10-13 | 1988-10-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63258674A JPH02105430A (en) | 1988-10-13 | 1988-10-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02105430A true JPH02105430A (en) | 1990-04-18 |
Family
ID=17323527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63258674A Pending JPH02105430A (en) | 1988-10-13 | 1988-10-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02105430A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057248A (en) * | 1995-02-09 | 2002-02-22 | Kyocera Corp | Package and mounting structure thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891653A (en) * | 1981-11-27 | 1983-05-31 | Copal Co Ltd | Automatic wire bonding method for semiconductor device using low reflectivity conductive adhesive paste |
| JPS604523A (en) * | 1983-06-23 | 1985-01-11 | Sumitomo Bakelite Co Ltd | Electrical insulating resin paste |
| JPS6354731A (en) * | 1986-08-25 | 1988-03-09 | Hitachi Vlsi Eng Corp | Semiconductor device |
-
1988
- 1988-10-13 JP JP63258674A patent/JPH02105430A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891653A (en) * | 1981-11-27 | 1983-05-31 | Copal Co Ltd | Automatic wire bonding method for semiconductor device using low reflectivity conductive adhesive paste |
| JPS604523A (en) * | 1983-06-23 | 1985-01-11 | Sumitomo Bakelite Co Ltd | Electrical insulating resin paste |
| JPS6354731A (en) * | 1986-08-25 | 1988-03-09 | Hitachi Vlsi Eng Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057248A (en) * | 1995-02-09 | 2002-02-22 | Kyocera Corp | Package and mounting structure thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5937321A (en) | Method for manufacturing ceramic multilayer circuit | |
| JPH0778900A (en) | Plastic package structure for power device and its assembly | |
| JP2895920B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH09307050A (en) | Lead frame and semiconductor device using it | |
| JPH02105430A (en) | Semiconductor device | |
| JPH0817870A (en) | Semiconductor device | |
| JP2593524Y2 (en) | Hybrid IC | |
| JP3297959B2 (en) | Semiconductor device | |
| JPH034543A (en) | Semiconductor device | |
| JP2734977B2 (en) | Semiconductor device, mounting structure and manufacturing method thereof | |
| JPH10340933A (en) | Manufacture of semiconductor device | |
| JPS6050342B2 (en) | Lead frame for semiconductor device manufacturing | |
| JP3013611B2 (en) | Method for manufacturing semiconductor device | |
| JPH09275176A (en) | Plastic molded type semiconductor device | |
| JPS6224654A (en) | Semiconductor package | |
| JPH06216396A (en) | Acceleration sensor | |
| JPS60171747A (en) | Semiconductor device | |
| JPH05251585A (en) | Ic module | |
| KR920000559B1 (en) | Semiconductor device | |
| JPS6043660B2 (en) | semiconductor equipment | |
| JPH01225141A (en) | Resin-sealed semiconductor device | |
| JPH04252041A (en) | Manufacture of hybrid integrated circuit | |
| JPH08306744A (en) | Electronic device | |
| JPH02121360A (en) | Electronic component mounting substrate | |
| JPH05203663A (en) | Piezoelectric vibration sensor device |