JP2734977B2 - Semiconductor device, mounting structure and manufacturing method thereof - Google Patents
Semiconductor device, mounting structure and manufacturing method thereofInfo
- Publication number
- JP2734977B2 JP2734977B2 JP6059653A JP5965394A JP2734977B2 JP 2734977 B2 JP2734977 B2 JP 2734977B2 JP 6059653 A JP6059653 A JP 6059653A JP 5965394 A JP5965394 A JP 5965394A JP 2734977 B2 JP2734977 B2 JP 2734977B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- electrode
- semiconductor device
- chip
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップをフェイ
スダウン方式で基板上に高密度に実装するための半導体
装置並びにその実装構造及び製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for mounting a semiconductor chip on a substrate in a face-down manner at a high density, and a mounting structure and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来の半導体装置には例えば特開平１−
２７６７５０号公報に記載されたものがある。図５は、
従来の半導体装置の断面図である。この従来の半導体装
置では、パッシベーション１３が施された半導体チップ
１の電極２ａ上に第１バンプ１１をメッキ法またはボー
ルバンプ法を用いて形成した後に半導体チップ１を絶縁
樹脂９に埋め込み成型する。このとき第１バンプ１１の
一部を絶縁樹脂９から露出させる。次いで、第１バンプ
１１及び絶縁樹脂９の表面に銀ペーストなどの導電ペー
ストをスクリーン印刷法によって印刷して回路導体層１
０を形成し、回路導体層１０上にメッキ法等を用いて第
２バンプ１２を形成する。このようにして製造された半
導体装置をフェイスダウンし、基板７上の電極２ｃと第
２バンプ１２とをはんだ８を用いて接続する。2. Description of the Related Art A conventional semiconductor device is disclosed in, for example,
There is one described in Japanese Patent No. 276750. FIG.
FIG. 14 is a cross-sectional view of a conventional semiconductor device. In this conventional semiconductor device, the first bumps 11 are formed on the electrodes 2a of the semiconductor chip 1 to which the passivation 13 has been applied by using a plating method or a ball bump method, and then the semiconductor chip 1 is embedded in the insulating resin 9 and molded. At this time, a part of the first bump 11 is exposed from the insulating resin 9. Next, a conductive paste such as a silver paste is printed on the surfaces of the first bumps 11 and the insulating resin 9 by a screen printing method to form the circuit conductor layer 1.
0 is formed, and the second bump 12 is formed on the circuit conductor layer 10 by using a plating method or the like. The semiconductor device manufactured in this manner is face-down, and the electrode 2c on the substrate 7 and the second bump 12 are connected using the solder 8.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の半導体
装置は、回路導体層１０に導電ペーストを用いているた
め電気抵抗値が大きくなり、信号伝達速度が遅くなると
いう欠点がある。また射出成型法、スクリーン印刷法、
メッキ法などの特殊技術を多用しているため工程が複雑
で製造コストが高くなるという欠点があった。The above-mentioned conventional semiconductor device has a drawback that since the conductive paste is used for the circuit conductor layer 10, the electric resistance increases and the signal transmission speed decreases. In addition, injection molding, screen printing,
Since many special techniques such as a plating method are used, there is a disadvantage that the process is complicated and the manufacturing cost is increased.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップの表面の周縁部に固着された角型枠と、こ
の角型枠の前記半導体チップとは反対側の面に設けられ
た枠電極と、前記半導体チップの表面に設けられたチッ
プ電極と前記枠電極とを電気的に接続するボンディング
ワイヤと、前記半導体チップの表面の回路面及び前記チ
ップ電極と前記ボンディングワイヤとの接続部を封止す
る樹脂とを含んで構成される。According to the present invention, there is provided a semiconductor device comprising:
A square frame fixed to a peripheral portion of the surface of the semiconductor chip, a frame electrode provided on a surface of the square frame opposite to the semiconductor chip, and a chip electrode provided on the surface of the semiconductor chip. It is configured to include a bonding wire for electrically connecting the frame electrode, and a resin for sealing a circuit surface on a surface of the semiconductor chip and a connection portion between the chip electrode and the bonding wire.
【０００５】本発明の半導体装置の製造方法は、 半導
体チップの表面の周縁部に角型枠を固着する工程と、こ
の角型枠の前記半導体チップとは反対側の面に設けられ
た枠電極と前記半導体チップの表面に設けられたチップ
電極とをワイヤボンディング接続する工程と、前記半導
体チップの表面の回路面及び前記チップ電極とボンディ
ングワイヤとの接続部とを樹脂封止する工程とを有す
る。According to the method of manufacturing a semiconductor device of the present invention, there is provided a method of fixing a square frame to a peripheral portion of a surface of a semiconductor chip, and a frame electrode provided on a surface of the square frame opposite to the semiconductor chip. And a step of wire bonding connecting a chip electrode provided on the surface of the semiconductor chip with a wire, and a step of resin-sealing a circuit surface on the surface of the semiconductor chip and a connection portion between the chip electrode and the bonding wire. .
【０００６】[0006]
【実施例】次に、本発明について図面を参照して詳細に
説明する。Next, the present invention will be described in detail with reference to the drawings.
【０００７】図１および図２は、本発明の一実施例を示
す斜視図（樹脂６を除いて示す）および断面図である。FIGS. 1 and 2 are a perspective view (excluding the resin 6) and a sectional view showing an embodiment of the present invention.
【０００８】本発明の半導体装置は、半導体チップ１の
表面上に角型枠３ａをエポキシ系接着剤４を用いて接着
し、次いで半導体チップ１上の電極２ａと角型枠３ａ上
の電極２ｂとをワイヤ５を用いてワイヤボンディング接
続し、樹脂６で半導体チップ１の表面上の回路面および
ワイヤボンディング接続部を封止する。その後、半導体
装置をフェイスダウンし、基板７上の電極２ｃと、角型
枠３ａ上の電極２ｂのワイヤボンディング接続部とをは
んだ８を用いて接続する。ワイヤボンディング接続する
際にワイヤのループ部を長くすることにより接続部への
応力集中やワイヤ切れを抑えることができる。In the semiconductor device of the present invention, a square frame 3a is bonded to the surface of the semiconductor chip 1 using an epoxy adhesive 4, and then the electrodes 2a on the semiconductor chip 1 and the electrodes 2b on the square frame 3a are bonded. Are connected by wire bonding using the wire 5, and the circuit surface on the surface of the semiconductor chip 1 and the wire bonding connection portion are sealed with the resin 6. Thereafter, the semiconductor device is face-down, and the electrode 2c on the substrate 7 and the wire bonding connection portion of the electrode 2b on the square frame 3a are connected using the solder 8. By increasing the length of the loop portion of the wire at the time of wire bonding connection, stress concentration on the connection portion and breakage of the wire can be suppressed.
【０００９】角型枠３ａはセラミック系材料もしくはガ
ラスエポキシ等の耐熱プラスチック材料を用いることに
より、低コスト化を図ることができる。ワイヤボンディ
ング接続するワイヤ５は細く、Ａｕの場合ははんだへ溶
け込みやすいので、銅もしくはパラジウムを主成分とし
た材料にすることにより、はんだへの溶け込みが抑制さ
れ接続部の信頼性を高くすることができる。The cost can be reduced by using a heat-resistant plastic material such as a ceramic material or glass epoxy for the square frame 3a. The wire 5 to be connected by wire bonding is thin, and in the case of Au, it is easy to dissolve into the solder. Therefore, by using a material containing copper or palladium as a main component, it is possible to suppress the penetration into the solder and increase the reliability of the connection portion. it can.
【００１０】また、本発明の参考例として図３および図
４に示すように、周囲の縁壁３ｃの上面に電極２ｂを有
する升型枠３ｂの凹部の底面に裏面を接着剤４で接着す
ることにより半導体チップ１を搭載する。ワイヤ５によ
る電極２ａ，２ｂの接続基板７への実装構造は図１，２
に示す実施例と同様である。本例では半導体チップ１の
裏面が升型枠３ｂに接着されるので半導体チップ１の機
械的強度を高くすることができる。As a reference example of the present invention, as shown in FIGS. 3 and 4, the back surface is adhered to the bottom surface of the concave portion of the square frame 3b having the electrode 2b on the upper surface of the peripheral edge wall 3c with an adhesive 4. Thus, the semiconductor chip 1 is mounted. The mounting structure of the electrodes 2a and 2b on the connection board 7 by the wires 5 is shown in FIGS.
This is the same as the embodiment shown in FIG. In this example, the mechanical strength of the semiconductor chip 1 can be increased because the back surface of the semiconductor chip 1 is bonded to the square frame 3b.
【００１１】[0011]
【発明の効果】本発明の半導体装置は、半導体チップと
基板との接続はワイヤボンディングおよびはんだ付けを
用いているので、導電ペーストを用いる接続の場合より
は電気抵抗値が低く信号伝達速度を速くすることができ
る。またワイヤボンディングを用いているにもかかわら
ず基板への搭載には、はんだ接続によるためはんだリフ
ロにより基板へ実装することが可能である。すなわち、
本発明の半導体装置は、量産対応のワイヤボンディング
技術を用いていることと、形態がパッケージの構造とな
っているため基板への実装に他の部品との一括リフロを
用いることができることとにより、基板実装までの製造
工程が簡略になり低コスト化を図ることができるという
効果がある。According to the semiconductor device of the present invention, since the connection between the semiconductor chip and the substrate is performed by wire bonding and soldering, the electric resistance value is lower and the signal transmission speed is higher than in the case of connection using a conductive paste. can do. Further, despite the use of wire bonding, the mounting on the substrate is performed by solder connection, so that it can be mounted on the substrate by solder reflow. That is,
The semiconductor device of the present invention uses a wire bonding technology for mass production, and since it has a package structure, a package reflow with other components can be used for mounting on a substrate. There is an effect that the manufacturing process up to the mounting of the substrate is simplified, and the cost can be reduced.
【図１】本発明の一実施例の斜視図である。FIG. 1 is a perspective view of one embodiment of the present invention.
【図２】図１に示す実施例の断面図である。FIG. 2 is a sectional view of the embodiment shown in FIG.
【図３】本発明の参考例の斜視図である。FIG. 3 is a perspective view of a reference example of the present invention.
【図４】図３に示す参考例の断面図である。FIG. 4 is a sectional view of the reference example shown in FIG. 3;
【図５】従来の半導体装置の断面図である。FIG. 5 is a sectional view of a conventional semiconductor device.
Claims (3)
た角型枠と、この角型枠の前記半導体チップとは反対側
の面に設けられた枠電極と、前記半導体チップの表面に
設けられたチップ電極と前記枠電極とを電気的に接続す
るボンディングワイヤと、前記半導体チップの表面の回
路面及び前記チップ電極と前記ボンディングワイヤとの
接続部を封止する樹脂とを含むことを特徴とする半導体
装置。1. A square frame fixed to a peripheral portion of a surface of a semiconductor chip, a frame electrode provided on a surface of the square frame opposite to the semiconductor chip, and a frame electrode provided on a surface of the semiconductor chip. A bonding wire for electrically connecting the chip electrode to the frame electrode, and a resin for sealing a circuit surface on a surface of the semiconductor chip and a connection portion between the chip electrode and the bonding wire. Semiconductor device.
基板に対向させた請求項１記載の半導体装置と、枠電極
と前記基板上に設けられた基板電極とを接続するはんだ
とを含むことを特徴とする半導体装置の実装構造。2. The semiconductor device according to claim 1, wherein the substrate has a front surface side of the semiconductor chip facing the substrate, and a solder for connecting a frame electrode and a substrate electrode provided on the substrate. A mounting structure of a semiconductor device, characterized in that:
固着する工程と、この角型枠の前記半導体チップとは反
対側の面に設けられた枠電極と前記半導体チップの表面
に設けられたチップ電極とをワイヤボンディング接続す
る工程と、前記半導体チップの表面の回路面及び前記チ
ップ電極とボンディングワイヤとの接続部とを樹脂封止
する工程とを含むことを特徴とする半導体装置の製造方
法。3. A step of fixing a square frame to a peripheral portion of a surface of a semiconductor chip, a frame electrode provided on a surface of the square frame opposite to the semiconductor chip, and a frame electrode provided on a surface of the semiconductor chip. A wire bonding connection between the chip electrode and the bonding wire, and a step of resin-sealing a circuit surface on the surface of the semiconductor chip and a connection portion between the chip electrode and the bonding wire. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6059653A JP2734977B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor device, mounting structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6059653A JP2734977B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor device, mounting structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07273136A JPH07273136A (en) | 1995-10-20 |
| JP2734977B2 true JP2734977B2 (en) | 1998-04-02 |
Family
ID=13119384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6059653A Expired - Lifetime JP2734977B2 (en) | 1994-03-30 | 1994-03-30 | Semiconductor device, mounting structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2734977B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02215138A (en) * | 1989-02-15 | 1990-08-28 | Toshiba Corp | Semiconductor device |
| JP2752803B2 (en) * | 1991-05-17 | 1998-05-18 | 九州日本電気株式会社 | Method for manufacturing semiconductor device |
-
1994
- 1994-03-30 JP JP6059653A patent/JP2734977B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07273136A (en) | 1995-10-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19971202 |