JP2002057248A - Package and mounting structure thereof - Google Patents

Package and mounting structure thereof

Info

Publication number
JP2002057248A
JP2002057248A JP2001249503A JP2001249503A JP2002057248A JP 2002057248 A JP2002057248 A JP 2002057248A JP 2001249503 A JP2001249503 A JP 2001249503A JP 2001249503 A JP2001249503 A JP 2001249503A JP 2002057248 A JP2002057248 A JP 2002057248A
Authority
JP
Japan
Prior art keywords
package
insulating substrate
circuit board
thermal expansion
sintered body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001249503A
Other languages
Japanese (ja)
Other versions
JP3677468B2 (en
Inventor
Koichi Yamaguchi
浩一 山口
Kunihide Yomo
邦英 四方
Hideto Yonekura
秀人 米倉
Takeshi Kubota
武志 窪田
Yasuyoshi Kunimatsu
廉可 國松
Noriaki Hamada
紀彰 浜田
Tsukasa Yanagida
司 柳田
Masaya Kokubu
正也 國分
Hitoshi Kumadawara
均 隈田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001249503A priority Critical patent/JP3677468B2/en
Publication of JP2002057248A publication Critical patent/JP2002057248A/en
Application granted granted Critical
Publication of JP3677468B2 publication Critical patent/JP3677468B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Compositions Of Oxide Ceramics (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally when a package is mounted on an external electric circuit board such as a printed board, the package cannot be electrically connected stably with the external electric circuit board, due to large thermal stress caused by the difference between the thermal expansion coefficients of the both. SOLUTION: A package (A) has respectively a ceramic insulation board 1, connection pads 3a formed on the rear surface or side surface of the insulation board 1, and each metallized wiring layer 3 for connecting an element 5 mounted on the top surface of the insulation board 1 with each connection pad 3a, is provided on the surface of the insulation board 1 or in its inside. Also, the package A is mounted on an external electric circuit board (B), by welding with a brazing material the connection pads 3a to the board B. In the package A, the insulation board 1 is made of a ceramic sintered body, having a thermal expansion coefficient of 80-180×10-7/ deg.C in a temperature range of 40-400 deg.C, and the element 5 is bonded to the insulation board 1 with a flexible bonding material.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、パッケージと、パ
ッケージの外部電気回路基板への実装構造に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package and a structure for mounting the package on an external electric circuit board.

【0002】[0002]

【従来技術】従来、半導体素子、特にLSI(大規模集
積回路素子)等の半導体集積回路素子を収容するための
半導体素子収納用パッケージは、一般にアルミナセラミ
ックス等の電気絶縁材料からなり、その上面中央部に半
導体素子を収容するための凹所を有する絶縁基板と、前
記絶縁基板の凹所周辺から導出されるタングステン、モ
リブデン等の高融点金属粉末から成る複数個のメタライ
ズ配線層と、前記絶縁基板の下面あるいは側面に形成さ
れ、メタライズ配線層が電気的に接続される複数個の接
続パッドと、所望により前記接続パッドにロウ付け取着
された接続端子と、蓋体とから構成されており、絶縁基
板の凹所底面に半導体素子を接着材を介して接着固定さ
せ、半導体素子の各電極とメタライズ配線層とをボンデ
ィングワイヤを介して電気的に接続させるとともに絶縁
基板上面に蓋体をガラス、樹脂等の封止材を介して接合
させ、絶縁基板と蓋体とから成る容器内部に半導体素子
を気密に封止することによって製品としての半導体素子
収納用パッケージとなる。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit), is generally made of an electrically insulating material such as alumina ceramics, and has a top center. An insulating substrate having a recess for accommodating a semiconductor element in a portion thereof, a plurality of metallized wiring layers made of a refractory metal powder such as tungsten or molybdenum derived from the periphery of the recess of the insulating substrate; A plurality of connection pads formed on the lower surface or side surfaces of the metallized wiring layer and electrically connected to the metallized wiring layer, connection terminals brazed and attached to the connection pads as desired, and a lid, A semiconductor element is bonded and fixed to the bottom of the recess of the insulating substrate via an adhesive, and each electrode of the semiconductor element and the metallized wiring layer are connected via a bonding wire. By connecting the lid to the upper surface of the insulating substrate via a sealing material such as glass or resin, and hermetically sealing the semiconductor element inside the container consisting of the insulating substrate and the lid. As a semiconductor device storage package.

【0003】また、かかる半導体素子収納用パッケージ
は、外部電気回路基板の配線導体と接続するには、半導
体素子収納用パッケージの前記絶縁基板に設けられた接
続端子と外部電気回路基板の配線導体とを半田等のロウ
材により電気的に接続することができる。
In order to connect the semiconductor element housing package to a wiring conductor of an external electric circuit board, a connection terminal provided on the insulating substrate of the semiconductor element housing package and a wiring conductor of the external electric circuit board are connected. Can be electrically connected by a brazing material such as solder.

【0004】一般に、半導体素子の集積度が高まるほ
ど、半導体素子に形成される電極数も増大するが、これ
に伴いこれを収納する半導体収納用パッケージにおける
端子数も増大することになる。ところが、電極数が増大
するに伴いパッケージ自体の寸法を大きくするにも限界
があり、より小型化を要求される以上、パッケージにお
ける端子の密度を高くすることが必要となる。
In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. As a result, the number of terminals in a semiconductor housing package for housing the same increases. However, as the number of electrodes increases, there is a limit in increasing the size of the package itself. Therefore, as more miniaturization is required, it is necessary to increase the density of terminals in the package.

【0005】これまでのパッケージにおける端子の密度
を高めるための構造としては、パッケージの下面に接続
端子としてコバールなどの金属ピンを接続したピングリ
ッドアレイ(PGA)が最も一般的であるが、最近で
は、パッケージの4つの側面に導出されたメタライズ配
線層にガルウイング状(L字状)の金属ピンが接続され
たタイプのクワッドフラットパッケージ(QFP)、パ
ッケージの4つの側面に電極パッドを備えリードピンが
ないリードレスチップキャリア(LCC)、さらに接続
端子を半田からなる球状端子により構成したボールグリ
ッドアレイ(BGA)等があり、これらの中でもBGA
が最も高密度化が可能であると言われている。
[0005] As a structure for increasing the terminal density in a conventional package, a pin grid array (PGA) in which metal pins such as Kovar are connected as connection terminals to the lower surface of the package is the most common, but recently, it has been recently used. A quad flat package (QFP) in which gull-wing (L-shaped) metal pins are connected to metallized wiring layers led out on four sides of the package, and electrode pads are provided on four side faces of the package without lead pins There is a leadless chip carrier (LCC), and a ball grid array (BGA) in which connection terminals are formed by spherical terminals made of solder. Among these, BGA
It is said that the highest density is possible.

【0006】このボールグリッドアレイ(BGA)で
は、接続パッドに半田などのロウ材からなる球状あるい
は柱状の端子をロウ付けした接続端子により構成し、こ
の接続端子を外部電気回路基板の配線導体上に載置当接
させ、しかる後、前記端子を約250〜400℃の温度
で加熱溶融し、球状端子を配線導体に接合させることに
よって外部電気回路基板上に実装することが行われてい
る。このような実装構造により、半導体素子収納用パッ
ケージの内部に収容されている半導体素子はその各電極
がメタライズ配線層及び接続端子を介して外部電気回路
基板に電気的に接続される。
In this ball grid array (BGA), connection terminals are formed by connecting spherical or columnar terminals made of a brazing material such as solder to connection pads, and the connection terminals are formed on wiring conductors of an external electric circuit board. The terminals are placed in contact with each other, and then the terminals are heated and melted at a temperature of about 250 to 400 ° C., and the spherical terminals are bonded to a wiring conductor to be mounted on an external electric circuit board. With such a mounting structure, each electrode of the semiconductor element housed in the semiconductor element housing package is electrically connected to the external electric circuit board via the metallized wiring layer and the connection terminal.

【0007】また、半導体素子収納用パッケージにおけ
る絶縁基板としては、その用途に応じてアルミナ、ムラ
イト、ガラス−セラミックスなどの焼結体からなる絶縁
材料が主として用いられている。
Further, as an insulating substrate in a package for housing a semiconductor element, an insulating material made of a sintered body such as alumina, mullite, glass-ceramic or the like is mainly used depending on its use.

【0008】一方、外部電気回路基板としては、主とし
てガラス−エポキシ複合材料からなる絶縁体の表面にC
u、Ag、Auなどからなる配線導体が被着形成された
ものが用いられている。
On the other hand, as an external electric circuit board, the surface of an insulator mainly composed of a glass-epoxy composite material has C
A wiring conductor formed of u, Ag, Au, or the like is used.

【0009】[0009]

【発明が解決しようとする課題】これらのパッケージに
おける絶縁基板として使用されているアルミナ、ムライ
トなどのセラミックスは、200MPa以上の高強度を
有し、しかもメタライズ配線層などとの多層化技術とし
て信頼性の高いことで有用ではあるが、その熱膨張係数
は約40〜70×10-7/℃程度であるのに対して、パ
ッケージが実装される外部電気回路基板として最も多用
されているガラス−エポキシなどからなるプリント基板
の熱膨張係数は120〜180×10-7/℃と非常に大
きい。
The ceramics such as alumina and mullite used as an insulating substrate in these packages have a high strength of 200 MPa or more, and have a high reliability as a multi-layered technology with metallized wiring layers. Although its usefulness is high, its thermal expansion coefficient is about 40 to 70 × 10 −7 / ° C., whereas glass-epoxy, which is most frequently used as an external electric circuit board on which a package is mounted, is used. The thermal expansion coefficient of a printed circuit board made of such a material is as large as 120 to 180 × 10 −7 / ° C.

【0010】そのため、半導体素子収納用パッケージの
内部に半導体集積回路素子を収容し、しかる後、プリン
ト基板などの外部電気回路基板に実装した場合、半導体
集積回路素子の作動時に発する熱が絶縁基板と外部電気
回路基板の両方に繰り返し印加されると前記絶縁基板と
外部電気回路基板との間に両者の熱膨張係数の相違に起
因する大きな熱応力が発生する。この熱応力は、パッケ
ージにおける端子数が300以下の比較的少ない場合に
は、大きな影響はないが、端子数が300を超え、パッ
ケージそのものが大型化するに従い、その影響が増大す
る傾向にある。
Therefore, when the semiconductor integrated circuit element is accommodated in the package for accommodating the semiconductor element and then mounted on an external electric circuit board such as a printed circuit board, heat generated during operation of the semiconductor integrated circuit element is transferred to the insulating substrate. When repeatedly applied to both of the external electric circuit boards, a large thermal stress is generated between the insulating substrate and the external electric circuit board due to a difference in thermal expansion coefficient between the two. This thermal stress has no significant effect when the number of terminals in the package is relatively small, that is, 300 or less, but the influence tends to increase as the number of terminals exceeds 300 and the package itself becomes larger.

【0011】即ち、パッケージの作動および停止の繰り
返しにより熱応力が繰り返し印加されると、この熱応力
が絶縁基板下面の接続パッドの外周部、及び外部電気回
路基板の配線導体と端子との接合界面に作用し、その結
果、接続パッドが絶縁基板より剥離したり、端子が配線
導体より剥離したりし、半導体素子収納用パッケージの
接続端子を外部電気回路基板の配線導体に長期にわたり
安定に電気的接続させることができないという欠点を有
していた。
That is, when a thermal stress is repeatedly applied by repeating the operation and the stop of the package, the thermal stress is applied to the outer peripheral portion of the connection pad on the lower surface of the insulating substrate and the bonding interface between the wiring conductor and the terminal of the external electric circuit board. As a result, the connection pads are peeled off from the insulating substrate, the terminals are peeled off from the wiring conductors, and the connection terminals of the semiconductor element storage package are stably electrically connected to the wiring conductors of the external electric circuit board for a long time. It had the disadvantage that it could not be connected.

【0012】従って、本発明は、上記欠点を解消すべ
く、半導体素子などの素子を搭載したパッケージをガラ
ス−エポキシ樹脂等の高熱膨張の絶縁体からなる外部電
気回路基板に対して、強固に且つ長期にわたり安定した
接続状態を維持できる高信頼性のパッケージと、その実
装構造を提供することを目的とするものである。
Accordingly, the present invention solves the above-mentioned drawbacks by firmly mounting a package mounting an element such as a semiconductor element on an external electric circuit board made of a high thermal expansion insulator such as a glass-epoxy resin. It is an object of the present invention to provide a highly reliable package capable of maintaining a stable connection state for a long time, and a mounting structure thereof.

【0013】[0013]

【課題を解決するための手段】本発明のパッケージは、
セラミック絶縁基板と、該絶縁基板下面または側面に形
成された接続パッドと、絶縁基板上面に搭載された素子
と前記接続パッドとを接続するために前記絶縁基板の表
面あるいは内部に配設されたメタライズ配線層とを具備
し、前記接続パッドをロウ材によって接合することによ
って外部電気回路基板に実装されるパッケージにおい
て、前記絶縁基板が40〜400℃の温度範囲における
熱膨張係数が80〜180×10-7/℃のセラミック焼
結体からなり、前記素子が前記絶縁基板に可撓性材料に
よって接着されていることを特徴とするものである。
The package of the present invention comprises:
A ceramic insulating substrate, a connection pad formed on the lower surface or side surface of the insulating substrate, and a metallization disposed on or in the insulating substrate for connecting an element mounted on the upper surface of the insulating substrate and the connection pad. A wiring layer, wherein the insulating substrate has a thermal expansion coefficient of 80 to 180 × 10 in a temperature range of 40 to 400 ° C. -7 / ° C., wherein the element is bonded to the insulating substrate with a flexible material.

【0014】また、本発明のパッケージの実装構造は、
40〜400℃における熱膨張係数が12〜16ppm
/℃の絶縁体の表面に配線導体が被着形成された外部電
気回路基板上に、上記のパッケージの前記接続パッドを
前記配線導体にロウ材を介して接合することによって実
装してなることを特徴とするものである。
Further, the package mounting structure of the present invention is as follows.
The coefficient of thermal expansion at 40 to 400 ° C is 12 to 16 ppm
The connection pad of the above package is mounted on an external electric circuit board having a wiring conductor adhered and formed on the surface of an insulator at / ° C by bonding the connection pad to the wiring conductor via a brazing material. It is a feature.

【0015】なお、上記パッケージおよびその実装構造
においては、前記パッケージにおける接続パッドに、ロ
ウ材からなる接続端子が取着されていたり、前記接続パ
ッドに高融点材料の球状もしくは柱状端子からなる接続
端子が低融点のロウ材によってロウ付けされていること
が望ましい。
In the above package and its mounting structure, a connection terminal made of a brazing material is attached to a connection pad of the package, or a connection terminal made of a spherical or columnar terminal made of a high melting point material is attached to the connection pad. Is desirably brazed with a low melting point brazing material.

【0016】また、前記セラミック焼結体としては、S
iO2およびAl23を主体とする焼結体であって、焼
結体中に少なくともクリストバライト結晶および/また
はムライト結晶相が析出してなる焼結体、あるいはガラ
ス相と、40〜400℃の温度範囲における熱膨張係数
が60×10-7/℃以上の金属酸化物からなる結晶相が
含まれている焼結体であることが望ましい。
Further, as the ceramic sintered body, S
a sintered body mainly composed of iO 2 and Al 2 O 3 , wherein at least cristobalite crystal and / or mullite crystal phase is precipitated in the sintered body, or a glass phase, and 40 to 400 ° C. It is preferable that the sintered body contains a crystal phase composed of a metal oxide having a coefficient of thermal expansion of 60 × 10 −7 / ° C. or more in the temperature range described above.

【0017】[0017]

【作用】本発明では、ガラス−エポキシ基板などのプリ
ント基板からなる外部電気回路基板に対して実装される
パッケージにおける絶縁基板として40〜400℃の温
度範囲における熱膨張係数が80〜180×10-7/℃
のセラミック焼結体を用いることにより、絶縁基板と外
部電気回路基板との間の熱膨張係数の差が小さくなり、
その結果、絶縁基板と外部電気回路基板の熱膨張係数の
相違に起因する熱応力によってパッケージと外部電気回
路基板とが接続不良を起こすことがなく、これによって
もパッケージに搭載された素子と外部電気回路基板とを
長期間にわたり正確に且つ強固に電気的接続させること
が可能となる。
According to the present invention, the thermal expansion coefficient in a temperature range of 40 to 400 ° C. is 80 to 180 × 10 as an insulating substrate in a package mounted on an external electric circuit board such as a glass-epoxy board or the like. 7 / ℃
By using the ceramic sintered body of, the difference in thermal expansion coefficient between the insulating substrate and the external electric circuit board is reduced,
As a result, a connection failure between the package and the external electric circuit board does not occur due to a thermal stress caused by a difference in thermal expansion coefficient between the insulating substrate and the external electric circuit board. It is possible to accurately and firmly electrically connect the circuit board to the circuit board for a long period of time.

【0018】また、絶縁基板として、SiO2およびA
23を主体とするセラミック焼結体であって、焼結体
中に少なくともクリストバライト結晶および/またはム
ライト結晶相が析出してなる焼結体、あるいはガラス相
と、40〜400℃の温度範囲における熱膨張係数が6
0×10-7/℃以上の金属酸化物からなる結晶相を含む
セラミック焼結体を用いることにより、ガラス相組成や
前述の結晶相の析出量を制御することにより、熱膨張係
数を80〜180×10-7/℃の範囲で容易に制御する
ことができる。
Further, as the insulating substrate, SiO 2 and A
A ceramic sintered body consisting mainly of l 2 O 3, sintered bodies at least cristobalite crystals and / or mullite crystalline phase in the sintered body is formed by deposition, or a glass phase, a temperature of 40 to 400 ° C. 6 coefficient of thermal expansion in the range
By using a ceramic sintered body containing a crystal phase composed of a metal oxide having a temperature of 0 × 10 −7 / ° C. or more, the thermal expansion coefficient can be controlled to 80 to 50% by controlling the glass phase composition and the amount of the crystal phase precipitated. It can be easily controlled in the range of 180 × 10 −7 / ° C.

【0019】さらに、パッケージにおいて、素子と絶縁
基板とを可撓性材料によって接着することによって、素
子と絶縁基板との間に大きな熱膨張差があってもそれを
緩衝できるために、素子が剥離するのを防止することが
できる。
Further, in the package, by bonding the element and the insulating substrate with a flexible material, even if there is a large difference in thermal expansion between the element and the insulating substrate, the element can be separated. Can be prevented.

【0020】[0020]

【発明の実施の形態】以下、本発明を一実施例を示す添
付図面に基づき詳細に説明する。図1及び図3は本発明
におけるBGA型半導体素子収納用パッケージの実装構
造の一実施例を示し、Aは半導体素子収納用パッケー
ジ、Bは外部電気回路基板である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings showing an embodiment. 1 and 3 show one embodiment of a mounting structure of a BGA type semiconductor device housing package according to the present invention, wherein A is a semiconductor device housing package, and B is an external electric circuit board.

【0021】半導体素子収納用パッケージAは、絶縁基
板1と、蓋体2と、メタライズ配線層3と、接続端子4
およびパッケージの内部に収納される半導体素子5によ
り構成され、絶縁基板1及び蓋体2は半導体素子5を内
部に気密に収容するための容器6を構成する。つまり、
絶縁基板1は上面中央部に半導体素子5が載置収容され
る凹部1aが設けてあり、凹部1a底面には半導体素子
5は可撓性接着材を介して接着固定される。
The package A for housing a semiconductor element comprises an insulating substrate 1, a lid 2, a metallized wiring layer 3, and connection terminals 4.
And the semiconductor element 5 housed inside the package. The insulating substrate 1 and the lid 2 constitute a container 6 for airtightly housing the semiconductor element 5 inside. That is,
The insulating substrate 1 has a recess 1a in the center of the upper surface in which the semiconductor element 5 is placed and accommodated. The semiconductor element 5 is bonded and fixed to the bottom of the recess 1a via a flexible adhesive.

【0022】また、絶縁基板1には半導体素子5が載置
収容される凹部1aの周辺から下面にかけて複数個のメ
タライズ配線層3が被着形成されており、更に絶縁基板
1の下面には図2に示すように多数の凹部1bが設けら
れており、凹部1bの底面にはメタライズ配線層3と電
気的に接続された接続パッド3aが被着形成されてい
る。この接続パッド3aの表面には半田(錫−鉛合金)
などのロウ材から成る突起状端子4が外部電気回路基板
への接続端子4として取着されている。この突起状端子
4の取付方法としては、球状もしくは柱状のロウ材を接
続パッド3aに並べる方法と、スクリーン印刷法により
ロウ材を接続パッド3a上に印刷する方法がある。
Further, a plurality of metallized wiring layers 3 are formed on the insulating substrate 1 from the periphery to the lower surface of the concave portion 1a in which the semiconductor element 5 is mounted and accommodated. As shown in FIG. 2, a large number of concave portions 1b are provided, and connection pads 3a electrically connected to the metallized wiring layer 3 are formed on the bottom surfaces of the concave portions 1b. Solder (tin-lead alloy) is provided on the surface of the connection pad 3a.
A protruding terminal 4 made of a brazing material is attached as a connection terminal 4 to an external electric circuit board. As a method of attaching the protruding terminal 4, there are a method of arranging a spherical or columnar brazing material on the connection pad 3a, and a method of printing the brazing material on the connection pad 3a by a screen printing method.

【0023】この接続パッド3aに取着されている接続
端子4は絶縁基板1の下面に突出部4aを有しており、
半導体素子5の各電極が接続されている接続パッド3a
を外部電気回路基板Bの配線導体8に接続させるととも
に半導体素子収納用パッケージAを外部電気回路基板B
上に実装させる作用を為す。
The connection terminal 4 attached to the connection pad 3a has a protrusion 4a on the lower surface of the insulating substrate 1,
Connection pad 3a to which each electrode of semiconductor element 5 is connected
Is connected to the wiring conductor 8 of the external electric circuit board B, and the semiconductor element housing package A is connected to the external electric circuit board B.
It works on top.

【0024】なお、接続パッド3aと電気的に接続され
たメタライズ配線層3は、半導体素子5の各電極とボン
ディングワイヤ7を介して電気的に接続されることによ
り、半導体素子5の電極は、接続パッド3aと電気的に
接続されることになる。なお、外部電気回路基板Bは、
絶縁体9の表面に配線導体8が形成されている。
The metallized wiring layer 3 electrically connected to the connection pad 3a is electrically connected to each electrode of the semiconductor element 5 via a bonding wire 7, so that the electrode of the semiconductor element 5 is It is electrically connected to the connection pad 3a. The external electric circuit board B is
The wiring conductor 8 is formed on the surface of the insulator 9.

【0025】一方、外部電気回路基板Bは、絶縁体9と
配線導体8により構成されており、絶縁体9が少なくと
も有機樹脂を含む材料からなるプリント基板からなる。
具体的には、ガラス−エポキシ系複合材料などのような
40〜400℃における熱膨張係数が120〜160×
10-7/℃の絶縁材料からなる。また、この回路基板B
の表面に形成される配線導体8は、絶縁体9との線熱膨
張係数の整合性と、良電気伝導性の点で通常Cu、A
u、Al、Ni、Pd−Snなどの金属導体からなる。
なお、本発明における熱膨張係数は、すべて線熱膨張係
数を意味する。
On the other hand, the external electric circuit board B comprises an insulator 9 and a wiring conductor 8, and the insulator 9 is formed of a printed board made of a material containing at least an organic resin.
Specifically, the coefficient of thermal expansion at 40 to 400 ° C. such as a glass-epoxy composite material is 120 to 160 ×
It is made of an insulating material of 10 -7 / ° C. Also, this circuit board B
The wiring conductor 8 formed on the surface of the substrate is usually made of Cu, A in view of the consistency of the linear thermal expansion coefficient with the insulator 9 and the good electrical conductivity.
u, Al, Ni, Pd-Sn and other metal conductors.
The thermal expansion coefficients in the present invention all mean linear thermal expansion coefficients.

【0026】半導体素子収納用パッケージAを外部電気
回路基板Bに実装するには、パッケージAの絶縁基板1
下面の接続パッド3aに取着されている半田から成る突
起状端子4を外部電気回路基板Bの配線導体8上に載置
当接させ、しかる後、約250〜400℃の温度で加熱
することにより、半田などのロウ材からなる突起状端子
4自体が溶融し、端子4を配線導体8に接合させること
によって外部電気回路基板B上に実装される。この時、
配線導体8の表面には突起状端子4とのロウ材による接
続を容易に行うためにロウ材が被着形成されていること
が望ましい。
To mount the semiconductor element housing package A on the external electric circuit board B, the insulating substrate 1 of the package A
The protruding terminal 4 made of solder attached to the connection pad 3a on the lower surface is placed and abutted on the wiring conductor 8 of the external electric circuit board B, and then heated at a temperature of about 250 to 400 ° C. As a result, the protruding terminal 4 itself made of a brazing material such as solder is melted, and the terminal 4 is bonded to the wiring conductor 8 to be mounted on the external electric circuit board B. At this time,
It is desirable that a brazing material be adhered to the surface of the wiring conductor 8 in order to easily connect to the protruding terminals 4 using the brazing material.

【0027】また、他の例として、図3に示すように前
記接続端子4として、接続パッド3aに対して高融点材
料からなる球状端子10を低融点ロウ材11によりロウ
付けしたものが適用できる。この高融点材料は、ロウ付
けに使用される低融点ロウ材11よりも高融点であるこ
とが必要で、ロウ付け用ロウ材が例えばPb40重量%
−Sn60重量%の低融点の半田からなる場合、球状端
子10は例えばPb90重量%−Sn10重量%の高融
点半田や、Cu、Ag、Ni、Al、Au、Pt、Fe
などの金属により構成される。
As another example, as shown in FIG. 3, as the connection terminal 4, one obtained by brazing a spherical terminal 10 made of a high melting point material to a connection pad 3a with a low melting point brazing material 11 can be applied. . The high melting point material needs to have a higher melting point than the low melting point brazing material 11 used for brazing, and the brazing brazing material is, for example, 40% by weight of Pb.
When the solder is made of solder having a low melting point of 60% by weight of Sn, the spherical terminal 10 may be made of a solder having a high melting point of 90% by weight of Pb and 10% by weight of Sn, or Cu, Ag, Ni, Al, Au, Pt, Fe.
And the like.

【0028】かかる構成においてはパッケージAの絶縁
基板1下面の接続パッド3aに取着されている球状端子
10を外部電気回路基板Bの配線導体8上に載置当接さ
せ、しかる後、球状端子10を半田などのロウ材12に
より配線導体8に接着させて外部電気回路基板B上に実
装することができる。また、低融点のロウ材としてAu
−Sn合金を用いて接続端子を外部電気回路基板に接続
してもよく、さらに上記球状端子に代わりに柱状の端子
を用いてもよい。
In such a configuration, the spherical terminal 10 attached to the connection pad 3a on the lower surface of the insulating substrate 1 of the package A is placed and abutted on the wiring conductor 8 of the external electric circuit board B. 10 can be mounted on the external electric circuit board B by bonding it to the wiring conductor 8 with a brazing material 12 such as solder. Au is used as a low melting point brazing material.
The connection terminal may be connected to the external electric circuit board using a -Sn alloy, and a columnar terminal may be used instead of the spherical terminal.

【0029】次に、図4にリードレスチップキャリア
(LCC)型パッケージCの外部伝回路基板Bへの実装
構造について説明する。なお、図4において、図1と同
一部材については同一の符号を付与した。図4における
パッケージCでは、半導体素子の電極と個々に接続され
たメタライズ配線層3が絶縁基板1の4の側面に導出さ
れ、側面に導出されたメタライズ配線層3が接続パッド
を兼ねた接続端子4を構成している。また、このパッケ
ージCによれば、電磁波障害を防止するために、半導体
素子5を収納する凹部1aにエポキシ樹脂等が充填さ
れ、また凹部は導電性樹脂からなる蓋体13により密閉
されている。また、パッケージCの底面にはアースのた
めの導電層14が形成されている。
Next, the mounting structure of the leadless chip carrier (LCC) type package C on the external transmission circuit board B will be described with reference to FIG. In FIG. 4, the same members as those in FIG. 1 are denoted by the same reference numerals. In the package C shown in FIG. 4, the metallized wiring layers 3 individually connected to the electrodes of the semiconductor element are led out to the side surfaces of the insulating substrate 1, and the metallized wiring layers 3 led out to the side surfaces are connection terminals that also serve as connection pads. 4. Further, according to the package C, in order to prevent electromagnetic interference, the concave portion 1a for accommodating the semiconductor element 5 is filled with an epoxy resin or the like, and the concave portion is sealed by the lid 13 made of a conductive resin. Further, a conductive layer 14 for grounding is formed on the bottom surface of the package C.

【0030】このパッケージCを外部電気回路基板Bに
実装するには、パッケージCの絶縁基板1側面の接続端
子4を外部電気回路基板Bの配線導体8上に載置当接さ
せてロウ材等により電気的に接続する。この時、接続端
子4は配線導体8の表面にはロウ材による接続を容易に
行うためでそれぞれロウ材が被着されていることが望ま
しい。
In order to mount the package C on the external electric circuit board B, the connection terminals 4 on the side of the insulating substrate 1 of the package C are placed and abutted on the wiring conductors 8 of the external electric circuit board B to form a brazing material or the like. For electrical connection. At this time, the connection terminals 4 are desirably coated with a brazing material on the surface of the wiring conductor 8 in order to facilitate connection with the brazing material.

【0031】本発明によれば、このような外部電気回路
基板Bの表面に実装される半導体素子収納用パッケージ
として、その絶縁基板1が、セラミック焼結体からな
り、且つ40〜400℃の温度範囲における熱膨張係数
が80〜180×10-7/℃、特に90〜140×10
-7/℃であることが重要である。これは、前述した外部
電気回路基板Bとの熱膨張係数差により熱応力の発生を
緩和し、外部電気回路基板BとパッケージA,Cとの電
気的接続状態を長期にわたり良好な状態に維持するため
に重要であり、この熱膨張係数が80×10-7/℃より
小さいか、あるいは180×10-7/℃より大きいと、
いずれも熱膨張差に起因する熱応力が大きくなり、外部
電気回路基板BとパッケージA,Cとの電気的接続状態
が悪化することを防止することができない。
According to the present invention, as a package for housing a semiconductor element mounted on the surface of such an external electric circuit board B, the insulating substrate 1 is made of a ceramic sintered body and has a temperature of 40 to 400 ° C. Coefficient of thermal expansion in the range of 80 to 180 × 10 −7 / ° C., especially 90 to 140 × 10
It is important that it is -7 / ° C. This alleviates the occurrence of thermal stress due to the difference in thermal expansion coefficient between the external electric circuit board B and the external electric circuit board B, and maintains a good electrical connection between the external electric circuit board B and the packages A and C for a long period of time. When the coefficient of thermal expansion is smaller than 80 × 10 −7 / ° C. or larger than 180 × 10 −7 / ° C.,
In any case, the thermal stress caused by the difference in thermal expansion becomes large, and it cannot be prevented that the electrical connection between the external electric circuit board B and the packages A and C deteriorates.

【0032】なお、絶縁基板1の熱膨張係数が80〜1
80×10-7/℃と大きくなるに伴い、Siを基板とす
る半導体素子5との熱膨張差が逆に大きくなってしまう
場合がある。そのため、本発明によれば、半導体素子5
の絶縁基板1への接着材として熱膨張差を緩衝可能な可
撓性の材料、例えば、エポキシ系、ポリイミド系などの
有機系接着材や、場合によってはこれにAgなどの金属
を配合した接着材を用いることによって、半導体素子5
が熱膨張差により剥離しないようにすることができる。
The thermal expansion coefficient of the insulating substrate 1 is 80 to 1
As the temperature increases to 80 × 10 −7 / ° C., the difference in thermal expansion from the semiconductor element 5 using Si as a substrate may increase on the contrary. Therefore, according to the present invention, the semiconductor element 5
A flexible material capable of buffering a difference in thermal expansion as an adhesive to the insulating substrate 1 such as an organic adhesive such as an epoxy-based or polyimide-based adhesive, or an adhesive obtained by mixing a metal such as Ag with the adhesive in some cases. By using the material, the semiconductor element 5
Can be prevented from being separated due to a difference in thermal expansion.

【0033】高熱膨張係数を有するセラミック焼結体と
しては、例えば、Al23−SiO 2系焼結体であり、
焼結体中にα−クリストバライト結晶相および/または
ムライト結晶相を含むものが挙げられる。α−クリスト
バライト自体が125〜580×10-7/℃の高い熱膨
張係数を有することから、このα−クリストバライトを
適量含有せしめることにより絶縁基板としての熱膨張係
数を高めることができる。また、ムライト結晶相は熱膨
張係数は4.5×10-7/℃と低いが、その他の成分と
して高融点のシリカガラスを含有せしめることにより焼
結体全体として高熱膨張化することができる。
A ceramic sintered body having a high coefficient of thermal expansion;
For example, for example, AlTwoOThree-SiO TwoA sintered body,
Α-cristobalite crystal phase and / or
Those containing a mullite crystal phase are exemplified. α-Christo
Barite itself is 125-580 × 10-7/ ° C high thermal expansion
Α-Cristobalite
By adding an appropriate amount, the thermal expansion
The number can be increased. In addition, the mullite crystal phase is thermally expanded.
The tension coefficient is 4.5 × 10-7/ ℃, but with other components
By containing high melting point silica glass
High thermal expansion can be achieved as a whole body.

【0034】上記の焼結体中にα−クリストバライト結
晶相および/またはムライト結晶相を含む焼結体を作製
する方法としては、特願平6−327301号に記載さ
れるように、出発原料としてAl23粉末と、SiO2
粉末と、周期律表第2a族、第3a族のうちの少なくと
も1種の金属の化合物を0.5重量%以上、ムライト粉
末を0.5重量%以上含み、全体組成におけるAlの酸
化物換算量/Siの酸化物換算量の重量比率が0.72
以上、1未満の範囲となる組成物、あるいは、SiO2
粉末もしくはSiO2粉末とAl23粉末と、周期律表
第2a族、第3a族のうちの少なくとも1種の金属の化
合物を0.5重量%以上、ムライト粉末を10重量%以
上含み、全体組成におけるAlの酸化物換算量/Siの
酸化物換算量の重量比率が0.6以上、1未満の範囲と
なる組成物を用いて、1600℃以下の温度で焼成する
とクリストバライト結晶を析出させることができる。
As a method for producing a sintered body containing the α-cristobalite crystal phase and / or mullite crystal phase in the above-mentioned sintered body, as described in Japanese Patent Application No. 6-327301, Al 2 O 3 powder, SiO 2
0.5% by weight or more of a powder and a compound of at least one metal of Groups 2a and 3a of the periodic table, and 0.5% by weight or more of mullite powder; Weight ratio of amount of Si / oxide equivalent amount is 0.72
Or less than 1 or SiO 2
Powder or SiO 2 powder, Al 2 O 3 powder, at least 0.5% by weight of a compound of at least one metal of Group 2a and Group 3a of the periodic table, and 10% by weight or more of mullite powder; Cristobalite crystals are precipitated by baking at a temperature of 1600 ° C. or less using a composition in which the weight ratio of the oxide equivalent amount of Al / the oxide equivalent amount of Si in the entire composition is 0.6 or more and less than 1. be able to.

【0035】また、1600℃を越える温度で焼成する
と、ムライト結晶相が析出するとともに、高熱膨張のS
iO2主成分のいわゆるSiO2ガラスが生成されるため
に高熱膨張化を実現できる。
Further, when firing at a temperature exceeding 1600 ° C., a mullite crystal phase is precipitated, and high thermal expansion S
Since a so-called SiO 2 glass containing iO 2 as a main component is generated, high thermal expansion can be realized.

【0036】また、他の焼結体としては、いわゆるガラ
ス質焼結体あるいはガラス−セラミック焼結体が挙げら
れ、ガラス形成成分として、それ自体高熱膨張を有する
化合物を添加して焼結体中の結晶相として高熱膨張係数
を有する結晶相を析出させて熱膨張係数を制御すること
ができる。これら焼結体の組成としては、SiO2を必
須成分として、その他の成分がLi、Na、Kなどのア
ルカリ金属、Ca、Ba、Sr、Mgなどのアルカリ土
類金属、Al、Zn、Pb、Ti、Zr、PおよびBの
群から選ばれる少なくとも1種以上の組み合わせからな
り、かかる焼結体中に高熱膨張を有する結晶相、具体的
には40〜400℃における熱膨張係数が60×10-7
/℃以上の結晶相として、クリストバライト(Si
2)、クォーツ(SiO2)、トリジマイト(Si
2)、フォルステライト(2MgO・SiO2)、スピ
ネル(MgO・Al23)、ウォラストナイト(CaO
・SiO2)、モンティセラナイト(CaO・MgO・
SiO2)、ネフェリン(Na2O・Al23・Si
2)、リチウムシリケート(Li2O・SiO2)、ジ
オプサイド(CaO・MgO・2SiO2)、メルビナ
イト(3CaO・MgO・2SiO2)、アケルマイト
(2CaO・MgO・2SiO2)、マグネシア(Mg
O)、アルミナ(Al23)、カーネギナイト(Na2
O・Al23・2SiO2)、エンスタタイト(MgO
・SiO2)、ホウ酸マグネシウム(2MgO・B
23)、セルシアン(BaO・Al23・2Si
2)、B23・2MgO・2SiO2の群から選ばれる
少なくとも1種以上が析出した焼結体が挙げられる。特
に80×10-7/℃以上の結晶相が良い。
The other sintered body may be a so-called vitreous sintered body or a glass-ceramic sintered body. As a glass-forming component, a compound having a high thermal expansion itself is added. A crystalline phase having a high thermal expansion coefficient can be precipitated as the crystalline phase to control the thermal expansion coefficient. As the composition of these sintered bodies, SiO 2 is an essential component, and other components are alkali metals such as Li, Na, and K; alkaline earth metals such as Ca, Ba, Sr, and Mg; Al, Zn, and Pb; A crystalline phase having at least one kind selected from the group consisting of Ti, Zr, P and B and having a high thermal expansion in such a sintered body, specifically having a thermal expansion coefficient of 60 × 10 at 40 to 400 ° C. -7
Cristobalite (Si)
O 2 ), quartz (SiO 2 ), tridymite (Si
O 2 ), forsterite (2MgO.SiO 2 ), spinel (MgO.Al 2 O 3 ), wollastonite (CaO
・ SiO 2 ), Monticellanite (CaO ・ MgO ・
SiO 2 ), nepheline (Na 2 O.Al 2 O 3 .Si)
O 2), lithium silicate (Li 2 O · SiO 2) , Jiopusaido (CaO · MgO · 2SiO 2) , Merubinaito (3CaO · MgO · 2SiO 2) , Akerumaito (2CaO · MgO · 2SiO 2) , magnesia (Mg
O), alumina (Al 2 O 3 ), carneginite (Na 2
O.Al 2 O 3 .2SiO 2 ), enstatite (MgO
.SiO 2 ), magnesium borate (2MgO.B)
2 O 3 ), Celsian (BaO.Al 2 O 3 .2Si)
O 2 ) and a sintered body in which at least one or more selected from the group consisting of B 2 O 3 .2MgO.2SiO 2 are precipitated. Particularly, a crystal phase of 80 × 10 −7 / ° C. or more is preferable.

【0037】また、パッケージA,Cの絶縁基板1内に
配設されたメタライズ配線層3としては、W,Moなど
の高融点金属の他、Cu、Ag、Ni、Pd、Auのう
ちの1種以上により構成することができる。
The metallized wiring layer 3 disposed in the insulating substrate 1 of the packages A and C may be made of one of Cu, Ag, Ni, Pd and Au in addition to a high melting point metal such as W and Mo. It can be composed of more than one kind.

【0038】このようなパッケージA,Cを製造する方
法としては、絶縁基板1を構成するための原料粉末に適
当な有機バインダー、可塑剤、溶剤を添加混合して泥漿
物を作るとともに該泥漿物をドクターブレード法やカレ
ンダーロール法を採用することによってグリーンシート
(生シート)と作製する。そして、メタライズ配線層3
及び接続パッド3aとして、適当な金属粉末に有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
を前記グリーンシートに周知のスクリーン印刷法により
所定パターンに印刷塗布する。また、場合によっては、
前記グリーンシートに適当な打ち抜き加工してスルーホ
ールを形成し、このホール内にもメタライズペーストを
充填する。そしてこれらのグリーンシートを複数枚積層
し、グリーンシートとメタライズ配線層3および接続パ
ッド3aとを同時に焼成することにより多層構造のパッ
ケージを得ることができる。
As a method of manufacturing such packages A and C, a suitable organic binder, a plasticizer and a solvent are added to a raw material powder for forming the insulating substrate 1 and mixed to form a slurry, and the slurry is formed. Is manufactured as a green sheet (raw sheet) by employing a doctor blade method or a calendar roll method. And the metallized wiring layer 3
And, as the connection pad 3a, a metal paste obtained by adding an organic binder, a plasticizer, and a solvent to a suitable metal powder and mixing is printed and applied on the green sheet in a predetermined pattern by a known screen printing method. Also, in some cases,
An appropriate punching process is performed on the green sheet to form a through hole, and this hole is filled with a metallizing paste. By stacking a plurality of these green sheets and simultaneously firing the green sheets, the metallized wiring layers 3 and the connection pads 3a, a package having a multilayer structure can be obtained.

【0039】このように同時焼成する場合、用いるメタ
ライズ配線層の種類により絶縁基板の材質を同時に焼成
できるように制御することが必要である。例えば、メタ
ライズ配線層をW、Mo等の高融点金属により構成する
場合には、絶縁基板としても1400〜1700℃の高
温で焼成されるような、例えばAl23−SiO2、A
23−MgO、Al23−SiO2−MgOの組成物
がよい。また、メタライズ配線層をCu、Ag、Niな
どにより構成する場合には、850〜1300℃の低温
で焼成できるような、例えばSiO2−MgO、SiO2
−Al23−Na2O、SiO2−MgO−CaO、Si
2−Al23−Li2O、SiO2−MgO−Li2O、
SiO2−ZnO−Li2O、SiO2−MgO−Ba
O、SiO 2−BaO−Al23−B23、SiO2−N
2O−P25−CaO、SiO2−Na2O−Al23
−P25−ZnO、SiO2−BaO−Al23−Mg
O−TiO2−ZrO2、SiO2−Al23−BaO−
Na2O等の組成物が望ましい。
When co-firing is performed as described above,
Simultaneous firing of insulating substrate material depending on the type of rise wiring layer
It is necessary to control it. For example, meta
The rise wiring layer is made of a high melting point metal such as W and Mo.
In this case, a high temperature of 1400 to 1700 ° C.
E.g. AlTwoOThree-SiOTwo, A
lTwoOThree-MgO, AlTwoOThree-SiOTwo-Composition of MgO
Is good. Further, the metallized wiring layer is made of Cu, Ag, Ni, etc.
In the case of using a low temperature of 850 to 1300 ° C
Such as SiOTwo-MgO, SiOTwo
-AlTwoOThree-NaTwoO, SiOTwo-MgO-CaO, Si
OTwo-AlTwoOThree−LiTwoO, SiOTwo-MgO-LiTwoO,
SiOTwo-ZnO-LiTwoO, SiOTwo-MgO-Ba
O, SiO Two-BaO-AlTwoOThree-BTwoOThree, SiOTwo-N
aTwoOPTwoOFive-CaO, SiOTwo-NaTwoO-AlTwoOThree
−PTwoOFive-ZnO, SiOTwo-BaO-AlTwoOThree-Mg
O-TiOTwo-ZrOTwo, SiOTwo-AlTwoOThree-BaO-
NaTwoA composition such as O is desirable.

【0040】[0040]

【実施例】以下、本発明をさらに具体的な例で説明す
る。 実施例1 全原料中におけるAl23/SiO2の重量比率が0.
4以上1以下の混合粉末(Al23の平均結晶粒径0.
6μm、SiO2の平均結晶粒径0.8μm)、CaC
3・MgCO3粉末(平均結晶粒径1.5μm)、Y2
3粉末にムライト粉末(平均結晶粒径1.0μm)
を、成形体組成が表1に示す割合となるように秤量混合
し、1軸プレス成形法により3.5×3.5×15mm
の形状に成形した後、大気中で表1に示すような焼成温
度条件で焼成した。尚、CaCO3、MgCO3粉末は、
CaO,MgOに変化したものとして表した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to more specific examples. Example 1 The weight ratio of Al 2 O 3 / SiO 2 in all the raw materials was 0.
Mixed powder of 4 or more and 1 or less (average crystal grain size of Al 2 O 3 .
6 μm, average crystal grain size of SiO 2 0.8 μm), CaC
O 3 · MgCO 3 powder (average crystal grain size 1.5 μm), Y 2
Mullite powder to O 3 powder (average crystal grain size: 1.0 μm)
Are weighed and mixed such that the composition of the molded article has the ratio shown in Table 1, and 3.5 × 3.5 × 15 mm by a uniaxial press molding method.
After being formed into the shape shown in Table 1, it was fired in the atmosphere under the firing temperature conditions shown in Table 1. The CaCO 3 and MgCO 3 powders are
The results are shown as changed to CaO and MgO.

【0041】(焼結体の特性評価)次に、上記のように
して得られた焼結体に対して結晶相をX線回折測定によ
り同定した。さらに40〜400℃の熱膨張率を測定し
表1に示した。また、焼結体を直径60mm、厚さ2m
mに加工し、JISC2141の手法で比誘電率を求め
た。測定はQメータ(Y.H.P4284A)を用いて
行い、1MHz,1.0Vrsmの条件で25℃におけ
る静電容量を測定し、この静電容量から25℃における
比誘電率を測定した。この結果を表1に示した。
(Evaluation of Characteristics of Sintered Body) Next, the crystal phase of the sintered body obtained as described above was identified by X-ray diffraction measurement. Further, the coefficient of thermal expansion at 40 to 400 ° C. was measured and is shown in Table 1. The sintered body is 60 mm in diameter and 2 m in thickness.
m, and the relative permittivity was determined by the method of JISC2141. The measurement was performed using a Q meter (YHP4284A), the capacitance at 25 ° C. was measured under the conditions of 1 MHz and 1.0 Vrsm, and the relative dielectric constant at 25 ° C. was measured from the capacitance. The results are shown in Table 1.

【0042】(実装時の熱サイクル試験)次に、表1に
おける各原料組成物を用いて、溶媒としてトルエン+I
PA、バインダーとしてアクリル樹脂、可塑剤としてD
BPを用いてドクターブレード法により厚み500μm
のグリーンシートを作製した。
(Heat cycle test at mounting) Next, using each raw material composition shown in Table 1, toluene + I was used as a solvent.
PA, acrylic resin as binder, D as plasticizer
500μm thickness by doctor blade method using BP
Green sheet was produced.

【0043】このグリーンシートの表面にWメタライズ
ペーストをスクリーン印刷法に基づきメタライズ配線層
を塗布した。また、グリーンシートの所定箇所にスルー
ホールを形成しスルーホール内が最終的に基板の下面に
露出するように形成し、そのスルーホール内にもWメタ
ライズペーストを充填した。そして、メタライズペース
トが塗布されたグリーンシートをスルーホールの位置合
わせを行いながら6枚積層し圧着した。
A metallized wiring layer was coated on the surface of the green sheet with a W metallized paste by screen printing. In addition, a through hole was formed at a predetermined portion of the green sheet so that the inside of the through hole was finally exposed on the lower surface of the substrate, and the inside of the through hole was filled with a W metallizing paste. Then, six green sheets to which the metallizing paste was applied were laminated and pressure-bonded while positioning the through holes.

【0044】この積層体を表1の各焼成温度で1600
℃の雰囲気中でメタライズ配線層と絶縁基板とを同時に
焼成しパッケージ用の配線基板を作製した。
The laminated body was subjected to 1600 at each firing temperature shown in Table 1.
The metallized wiring layer and the insulating substrate were simultaneously fired in an atmosphere at a temperature of ℃ to produce a wiring substrate for a package.

【0045】次に、配線基板の下面にスルーホールに接
続する箇所に凹部を形成しタングステンからなる接続パ
ッドを作製し、Niメッキ後、Auメッキを施した。
Next, a concave portion was formed on the lower surface of the wiring substrate at a position connected to the through hole, a connection pad made of tungsten was manufactured, and after Ni plating, Au plating was performed.

【0046】そして、その接続パッドに図1に示すよう
に半田(錫10%−鉛90%)からなる球状端子を取着
した。なお、球状端子は、1cm2当たり25端子の密
度で配線基板の下面全体に形成した。
Then, a spherical terminal made of solder (10% tin-90% lead) was attached to the connection pad as shown in FIG. The spherical terminals were formed on the entire lower surface of the wiring substrate at a density of 25 terminals per 1 cm 2 .

【0047】一方、ガラス−エポキシ基板からなる40
〜800℃における熱膨張係数が130×10-7/℃の
絶縁体の表面に銅箔からなる配線導体が形成されたプリ
ント基板を準備した。
On the other hand, a glass-epoxy substrate 40
A printed board was prepared in which a wiring conductor made of copper foil was formed on the surface of an insulator having a thermal expansion coefficient of 130 × 10 −7 / ° C. at −800 ° C.

【0048】そして、上記のパッケージ用絶縁基板をプ
リント基板の上の配線導体とパッケージ用絶縁基板の球
状端子が接続されるように位置合わせし、これをN2
雰囲気中で260℃で3分間熱処理しパッケージ用絶縁
基板をプリント基板表面に実装した。この熱処理により
パッケージ用絶縁基板の球状端子が溶けてプリント基板
の配線導体と電気的に接続されたことを確認した。
Then, the above-mentioned package insulating substrate is aligned so that the wiring conductor on the printed board and the spherical terminal of the package insulating substrate are connected, and this is placed in an atmosphere of N 2 at 260 ° C. for 3 minutes. After heat treatment, the package insulating substrate was mounted on the surface of the printed circuit board. By this heat treatment, it was confirmed that the spherical terminals of the package insulating substrate were melted and electrically connected to the wiring conductors of the printed circuit board.

【0049】次に、上記のようにしてパッケージ用絶縁
基板をプリント基板表面に実装したものを大気の雰囲気
にて−40℃と125℃に制御された恒温槽に試験サン
プルを15分/15分の保持を1サイクルとして最高1
000サイクル繰り返した。
Next, the test sample was mounted on the surface of the printed circuit board with the package insulating substrate mounted as described above in a thermostat controlled at −40 ° C. and 125 ° C. in an air atmosphere for 15 minutes / 15 minutes. Up to 1 with 1 cycle of holding
000 cycles were repeated.

【0050】そして、各サイクル毎にプリント基板の配
線導体とパッケージ用絶縁基板との電気抵抗を測定し電
気抵抗に変化が現れるまでのサイクル数を表1に示し
た。
The electrical resistance between the wiring conductor of the printed circuit board and the package insulating substrate was measured for each cycle, and the number of cycles until the electrical resistance changed was shown in Table 1.

【0051】[0051]

【表1】 [Table 1]

【0052】表1の結果から明らかなように、結晶相と
してクリストバライト結晶相が析出し熱膨張係数が80
〜180×10-7/℃のセラミックスを絶縁基板として
作製したパッケージ用絶縁基板では、昇降温1000サ
イクル後もプリント基板の配線導体とパッケージ用絶縁
基板との間に電気抵抗変化は全く見られなかった。
As is clear from the results in Table 1, the cristobalite crystal phase was precipitated as the crystal phase, and the thermal expansion coefficient was 80%.
In the case of a package insulating substrate manufactured using ceramics of up to 180 × 10 −7 / ° C. as an insulating substrate, no change in electrical resistance is observed between the wiring conductor of the printed circuit board and the package insulating substrate even after 1000 cycles of temperature rise and fall. Was.

【0053】これに対して、従来の熱膨張係数が80×
10-7/℃未満のAl23系焼結体を用いた試料No.
13では、100サイクルで電気抵抗が高くなり、接続
不良が生じた。また、熱膨張係数が180×10-7/℃
を超える試料No.1、2においても500サイクル以
下で接続不良が生じた。
On the other hand, the conventional thermal expansion coefficient is 80 ×
Sample No. using an Al 2 O 3 based sintered body of less than 10 −7 / ° C.
In No. 13, the electrical resistance increased in 100 cycles, resulting in poor connection. The thermal expansion coefficient is 180 × 10 −7 / ° C.
Sample no. In the cases of Nos. 1 and 2, connection failure occurred in 500 cycles or less.

【0054】実施例2 原料として、BaCO3、SiO2、B23、MgO、Z
rO2、Li2O、CaCO3等を用いて、表2の組成に
なるように秤量混合した。この混合物を850〜950
℃で仮焼し、粉砕後、有機バインダーを添加して十分に
混合した後、1軸プレス法により3.5×3.5×15
mmの形状の成形体を作製し、この成形体を大気の雰囲
気中で900〜1100℃で焼成して焼結体を作製し
た。
Example 2 BaCO 3 , SiO 2 , B 2 O 3 , MgO, Z
Using rO 2 , Li 2 O, CaCO 3, etc., they were weighed and mixed so as to have the composition shown in Table 2. This mixture is 850-950
After calcining at ℃, pulverizing, adding an organic binder and mixing well, and then 3.5 × 3.5 × 15 by uniaxial pressing.
A molded body having a shape of mm was produced, and the molded body was fired at 900 to 1100 ° C. in an atmosphere of the air to produce a sintered body.

【0055】次に、上記のようにして得られた焼結体に
対して結晶相をX線回折測定により同定した。さらに4
0〜400℃の熱膨張係数を測定し表3に示した。ま
た、焼結体を直径60mm、厚さ2mmに加工し、JI
SC2141の手法で比誘電率を求めた。測定はQメー
タ(Y.H.P4284A)を用いて行い、1MHz,
1.0Vrsmの条件で25℃における静電容量を測定
し、この静電容量から25℃における比誘電率を測定し
た。この結果を表3に示した。
Next, the crystal phase of the sintered body obtained as described above was identified by X-ray diffraction measurement. 4 more
The coefficient of thermal expansion at 0 to 400 ° C. was measured and is shown in Table 3. The sintered body was processed to a diameter of 60 mm and a thickness of 2 mm,
The relative permittivity was determined by the method of SC2141. The measurement was performed using a Q meter (YHP4284A), and 1 MHz,
The capacitance at 25 ° C. was measured under the condition of 1.0 Vrsm, and the relative dielectric constant at 25 ° C. was measured from the capacitance. The results are shown in Table 3.

【0056】(実装時の熱サイクル試験)次に、表2に
おける各原料組成物を用いて、溶媒としてトルエン+I
PA、バインダーとしてアクリル樹脂、可塑剤としてD
BPを用いてドクターブレード法により厚み500μm
のグリーンシートを作製した。
(Heat cycle test at mounting) Next, using each of the raw material compositions shown in Table 2, toluene + I
PA, acrylic resin as binder, D as plasticizer
500μm thickness by doctor blade method using BP
Green sheet was produced.

【0057】このグリーンシートの表面にCuメタライ
ズペーストをスクリーン印刷法に基づきメタライズ配線
層を塗布した。また、グリーンシートの所定箇所にスル
ーホールを形成しスルーホール内が最終的に基板の下面
に露出するように形成し、そのスルーホール内にもCu
メタライズペーストを充填した。そして、メタライズペ
ーストが塗布されたグリーンシートをスルーホールの位
置合わせを行いながら6枚積層し圧着した。
A metallized wiring layer was coated on the surface of the green sheet with a Cu metallized paste by screen printing. Further, a through hole is formed at a predetermined position of the green sheet so that the inside of the through hole is finally exposed on the lower surface of the substrate.
Filled with metallized paste. Then, six green sheets to which the metallizing paste was applied were laminated and pressure-bonded while positioning the through holes.

【0058】この積層体を表2の各焼成温度(℃)で脱
バインダ工程:N2+H2O、本焼成:N2の雰囲気中で
メタライズ配線層と絶縁基板とを同時に焼成しパッケー
ジ用の配線基板を作製した。
At a firing temperature (° C.) shown in Table 2, the metallized wiring layer and the insulating substrate were simultaneously fired in a binder removal step: N 2 + H 2 O, and a main firing: N 2 atmosphere. A wiring board was manufactured.

【0059】次に、実施例1と同様に配線基板の下面に
スルーホールに接続する箇所に凹部を形成しCuメタラ
イズからなる接続パッドを作製した。そして、その接続
パッドに図1に示すように半田(錫30〜10%−鉛7
0〜90%)からなる接続端子を取着した。なお、接続
端子は、1cm2当たり30端子の密度で配線基板の下
面全体に形成した。
Next, in the same manner as in Example 1, a concave portion was formed on the lower surface of the wiring board at a position connected to the through hole, and a connection pad made of Cu metallized was manufactured. Then, as shown in FIG. 1, solder (30 to 10% tin-lead 7)
(0-90%). The connection terminals were formed on the entire lower surface of the wiring substrate at a density of 30 terminals per 1 cm 2 .

【0060】一方、ガラス−エポキシ基板からなる40
〜800℃における熱膨張係数が130×10-7/℃の
絶縁体の表面に銅箔からなる配線導体が形成されたプリ
ント基板を準備した。
On the other hand, a glass-epoxy substrate 40
A printed board was prepared in which a wiring conductor made of copper foil was formed on the surface of an insulator having a thermal expansion coefficient of 130 × 10 −7 / ° C. at −800 ° C.

【0061】そして、上記のパッケージ用絶縁基板をプ
リント基板の上の配線導体とパッケージ用絶縁基板の接
続端子が接続されるように位置合わせし、これをN2
雰囲気中で260℃で3分間熱処理しパッケージ用絶縁
基板をプリント基板表面に実装した。この熱処理により
パッケージ用絶縁基板の半田からなる接続端子が溶けて
プリント基板の配線導体と電気的に接続されたことを確
認した。
Then, the above-mentioned package insulating substrate is aligned so that the wiring conductor on the printed circuit board and the connection terminal of the package insulating substrate are connected, and this is placed in an atmosphere of N 2 at 260 ° C. for 3 minutes. After heat treatment, the package insulating substrate was mounted on the surface of the printed circuit board. By this heat treatment, it was confirmed that the solder-made connection terminals of the package insulating substrate were melted and electrically connected to the wiring conductors of the printed circuit board.

【0062】次に、上記のようにしてパッケージ用絶縁
基板をプリント基板表面に実装したものを大気の雰囲気
にて−40℃と125℃の各温度に制御した恒温槽に試
験サンプルを15分/15分の保持を1サイクルとして
最高1000サイクル繰り返した。そして、各サイクル
毎にプリント基板の配線導体とパッケージ用絶縁基板と
の電気抵抗を測定し電気抵抗に変化が現れるまでのサイ
クル数を表3に示した。
Then, the test sample was placed in a thermostat controlled at -40 ° C. and 125 ° C. in an air atmosphere at a temperature of −40 ° C. and a temperature of 125 ° C., respectively. Up to 1,000 cycles were repeated with one cycle of holding for 15 minutes. Then, the electric resistance between the wiring conductor of the printed circuit board and the insulating substrate for the package was measured for each cycle, and the number of cycles until the electric resistance changed was shown in Table 3.

【0063】[0063]

【表2】 [Table 2]

【0064】[0064]

【表3】 [Table 3]

【0065】表2、3の結果から明らかなように、熱膨
張係数が80〜180×10-7/℃のガラスセラミック
スを絶縁基板として作製したパッケージ用絶縁基板で
は、昇降温1000サイクル後もプリント基板の配線導
体とパッケージ用絶縁基板との間に電気抵抗変化は全く
見られず、極めて安定で良好な電気的接続状態を維持で
きた。
As is clear from the results shown in Tables 2 and 3, the insulating substrate for a package made of glass ceramics having a thermal expansion coefficient of 80 to 180 × 10 −7 / ° C. as an insulating substrate printed even after 1000 cycles of temperature rise and fall. No change in electrical resistance was observed between the wiring conductors of the substrate and the package insulating substrate, and an extremely stable and favorable electrical connection was maintained.

【0066】[0066]

【発明の効果】本発明におけるパッケージを熱膨張係数
が大きいプリント基板などの外部電気回路基板に実装し
た場合においても、両者の熱膨張係数の差に起因する応
力発生を抑制し、パッケージと外部電気回路基板とを長
期間にわたり正確、かつ強固に電気的接続させることが
可能となる。しかも、半導体回路素子の大型化による多
ピン化に十分対応できる信頼性の高いパッケージの実装
構造を実現できる。
According to the present invention, even when the package of the present invention is mounted on an external electric circuit board such as a printed circuit board having a large coefficient of thermal expansion, the generation of stress due to the difference between the two coefficients of thermal expansion is suppressed, and the package and the external It is possible to make accurate and strong electrical connection with the circuit board for a long period of time. In addition, a highly reliable package mounting structure that can sufficiently cope with an increase in the number of pins due to an increase in the size of the semiconductor circuit element can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明におけるBGA型半導体素子収納用パッ
ケージの実装構造を説明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a mounting structure of a BGA type semiconductor device housing package according to the present invention.

【図2】図1の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.

【図3】接続端子の他の実施例における要部拡大断面図
である。
FIG. 3 is an enlarged sectional view of a main part of another embodiment of the connection terminal.

【図4】本発明におけるリードレスチップキャリア型の
半導体素子収納用パッケージの実装構造を説明するため
の断面図である。
FIG. 4 is a cross-sectional view for explaining a mounting structure of a leadless chip carrier type semiconductor element storage package according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・絶縁基板 1a・・凹部 2・・・蓋体 3・・・メタライズ配線層 3a・・接続パッド 4・・・接続端子 4a・・突出部 5・・・半導体素子 6・・・容器 8・・・配線導体 9・・・絶縁体 A・・・BGA型半導体素子収納用パッケージ B・・・外部電気回路基板 C・・・LCC型半導体素子収納用パッケージ DESCRIPTION OF SYMBOLS 1 ... Insulating board 1a ... Depression 2 ... Lid 3 ... Metallized wiring layer 3a ... Connection pad 4 ... Connection terminal 4a ... Protrusion 5 ... Semiconductor element 6 ... Container 8 ... Wiring conductor 9 ... Insulator A ... BGA type semiconductor element storage package B ... External electric circuit board C ... LCC type semiconductor element storage package

───────────────────────────────────────────────────── フロントページの続き (72)発明者 窪田 武志 鹿児島県国分市山下町1番1号 京セラ株 式会社鹿児島国分工場内 (72)発明者 國松 廉可 鹿児島県国分市山下町1番1号 京セラ株 式会社鹿児島国分工場内 (72)発明者 浜田 紀彰 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 柳田 司 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 國分 正也 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 隈田原 均 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Takeshi Kubota 1-1, Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Corporation Kagoshima Kokubu Plant (72) Inventor Ryuni Kunimatsu 1-1, Yamashita-cho, Kokubu-shi, Kagoshima No. Within the Kyocera Corporation Kagoshima Kokubu Plant (72) Inventor Noriaki Hamada 1-4 Yamashita-cho, Kokubu City, Kagoshima Prefecture Inside the Kyocera Corporation Research Institute (72) Inventor Tsukasa Yanagita 1-4 Yamashita-cho, Kokubu City, Kagoshima Prefecture Inside the Kyocera Research Institute (72) Inventor Masaya Kokubu 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute (72) Inventor Hitoshi Kumadahara 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima No.In Kyocera Research Institute

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】セラミック絶縁基板と、該絶縁基板下面ま
たは側面に形成された接続パッドと、絶縁基板上面に搭
載された素子と前記接続パッドとを接続するために前記
絶縁基板の表面あるいは内部に配設されたメタライズ配
線層とを具備し、前記接続パッドをロウ材によって接合
することによって外部電気回路基板に実装されるパッケ
ージにおいて、前記絶縁基板が40〜400℃の温度範
囲における熱膨張係数が80〜180×10-7/℃のセ
ラミック焼結体からなり、前記素子が前記絶縁基板に可
撓性接着材によって接着されていることを特徴とするパ
ッケージ。
1. A ceramic insulating substrate, connection pads formed on the lower surface or side surfaces of the insulating substrate, and a surface or inside of the insulating substrate for connecting an element mounted on the upper surface of the insulating substrate and the connection pads. And a metallized wiring layer disposed thereon, wherein the package is mounted on an external electric circuit board by bonding the connection pads with a brazing material. A package comprising a ceramic sintered body of 80 to 180 × 10 −7 / ° C., wherein the element is bonded to the insulating substrate with a flexible adhesive.
【請求項2】前記接続パッドにロウ材からなる接続端子
が取着されている請求項1記載のパッケージ。
2. The package according to claim 1, wherein a connection terminal made of a brazing material is attached to said connection pad.
【請求項3】前記接続パッドに高融点材料の球状もしく
は柱状端子からなる接続端子が低融点のロウ材によって
ロウ付けされてなる請求項1または請求項2記載のパッ
ケージ。
3. The package according to claim 1, wherein connection terminals comprising spherical or columnar terminals of a high melting point material are brazed to said connection pads with a low melting point brazing material.
【請求項4】前記セラミック焼結体が、SiO2および
Al23を主体とする焼結体であって、該焼結体中に少
なくともクリストバライト結晶および/またはムライト
結晶相が析出してなる請求項1乃至請求項3のいずれか
記載のパッケージ。
4. The ceramic sintered body is a sintered body mainly composed of SiO 2 and Al 2 O 3 , wherein at least cristobalite crystal and / or mullite crystal phases are precipitated in the sintered body. The package according to claim 1.
【請求項5】前記セラミック焼結体が、ガラス相と、4
0〜400℃の温度範囲における熱膨張係数が60×1
-7/℃以上の金属酸化物からなる結晶相を含む請求項
1乃至請求項3のいずれか記載のパッケージ。
5. The method according to claim 1, wherein the ceramic sintered body comprises a glass phase,
The coefficient of thermal expansion in the temperature range of 0 to 400 ° C. is 60 × 1
The package according to any one of claims 1 to 3, further comprising a crystal phase composed of a metal oxide having a temperature of 0-7 / C or higher.
【請求項6】前記可撓性接着材が、有機系接着材、ある
いはこれに金属を配合した接着材である請求項1乃至請
求項5のいずれか記載のパッケージ。
6. The package according to claim 1, wherein the flexible adhesive is an organic adhesive or an adhesive obtained by mixing a metal with the organic adhesive.
【請求項7】40〜400℃における熱膨張係数が12
〜16ppm/℃の絶縁体の表面に配線導体が被着形成
された外部電気回路基板上に、請求項1乃至請求項6の
いずれか記載のパッケージの接続パッドを前記配線導体
にロウ材を介して接合することによって実装してなるこ
とを特徴とするパッケージの実装構造。
7. A thermal expansion coefficient at 40 to 400 ° C. of 12
A connection pad of the package according to any one of claims 1 to 6, wherein a wiring conductor is attached to a surface of an insulator at a temperature of up to 16 ppm / ° C. A package mounting structure characterized by being mounted by joining together.
JP2001249503A 1995-02-09 2001-08-20 Package and its mounting structure Expired - Fee Related JP3677468B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001249503A JP3677468B2 (en) 1995-02-09 2001-08-20 Package and its mounting structure

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-21653 1995-02-09
JP2165395 1995-02-09
JP2001249503A JP3677468B2 (en) 1995-02-09 2001-08-20 Package and its mounting structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP19520795A Division JP3297567B2 (en) 1995-02-09 1995-07-31 Package for housing semiconductor element and its mounting structure

Publications (2)

Publication Number Publication Date
JP2002057248A true JP2002057248A (en) 2002-02-22
JP3677468B2 JP3677468B2 (en) 2005-08-03

Family

ID=26358749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001249503A Expired - Fee Related JP3677468B2 (en) 1995-02-09 2001-08-20 Package and its mounting structure

Country Status (1)

Country Link
JP (1) JP3677468B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107596A (en) * 1982-12-13 1984-06-21 株式会社日立製作所 Ceramic multilayer wiring circuit board
JPH02105430A (en) * 1988-10-13 1990-04-18 Nec Corp Semiconductor device
JPH06184278A (en) * 1992-12-18 1994-07-05 Sumitomo Bakelite Co Ltd Electrically conductive resin paste for semiconductor
JPH06191887A (en) * 1992-10-29 1994-07-12 Nec Kansai Ltd Glass-ceramic composite and flat package-type piezoelectric parts using the composite
JPH06260566A (en) * 1993-03-04 1994-09-16 Sony Corp Land grid array package, its manufacture and semiconductor package
JPH06322350A (en) * 1993-03-17 1994-11-22 Fujitsu Ltd Conductive adhesive, its production and method for bonding semiconductor chip
JPH0722538A (en) * 1993-07-06 1995-01-24 Citizen Watch Co Ltd Structure of ball grid array type semiconductor package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59107596A (en) * 1982-12-13 1984-06-21 株式会社日立製作所 Ceramic multilayer wiring circuit board
JPH02105430A (en) * 1988-10-13 1990-04-18 Nec Corp Semiconductor device
JPH06191887A (en) * 1992-10-29 1994-07-12 Nec Kansai Ltd Glass-ceramic composite and flat package-type piezoelectric parts using the composite
JPH06184278A (en) * 1992-12-18 1994-07-05 Sumitomo Bakelite Co Ltd Electrically conductive resin paste for semiconductor
JPH06260566A (en) * 1993-03-04 1994-09-16 Sony Corp Land grid array package, its manufacture and semiconductor package
JPH06322350A (en) * 1993-03-17 1994-11-22 Fujitsu Ltd Conductive adhesive, its production and method for bonding semiconductor chip
JPH0722538A (en) * 1993-07-06 1995-01-24 Citizen Watch Co Ltd Structure of ball grid array type semiconductor package

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