JPH0722538A - Structure of ball grid array type semiconductor package - Google Patents
Structure of ball grid array type semiconductor packageInfo
- Publication number
- JPH0722538A JPH0722538A JP5191666A JP19166693A JPH0722538A JP H0722538 A JPH0722538 A JP H0722538A JP 5191666 A JP5191666 A JP 5191666A JP 19166693 A JP19166693 A JP 19166693A JP H0722538 A JPH0722538 A JP H0722538A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- grid array
- type semiconductor
- ball grid
- solder bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のパッケージ
に関するもので、更に詳しくはワイヤーボンディング実
装したボールグリッドアレイ型半導体パッケージの構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly to a structure of a wire grid mounted ball grid array type semiconductor package.
【０００２】[0002]
【従来の技術】近年、集積回路の発展はめざましく、生
産量の増加、価格の低下により使用される分野は、非常
に高い信頼度が要求される宇宙通信、超大型コンピュー
タはもとより、家庭電化製品に至るまで拡がっている。2. Description of the Related Art In recent years, the development of integrated circuits has been remarkable, and the fields used due to the increase in production volume and the decrease in price are used in space communications, ultra-large computers, home appliances, etc., which require extremely high reliability. It has spread to.
【０００３】そこで、従来より集積回路を収容するパッ
ケージが備えるべき基本的条件として、内部素子をいろ
いろな外部条件から保護できること、内部で発生する熱
を効率よく発散させること、取扱が容易であること及び
パッケージそのものが安価であること、などである。Therefore, as a basic condition that a package accommodating an integrated circuit should have conventionally, it is possible to protect internal elements from various external conditions, efficiently dissipate heat generated inside, and easy to handle. And that the package itself is inexpensive.
【０００４】これらの条件を満足するように製造された
パッケージとして、従来からリード線を外部に引き出す
ものとして、いくつかのタイプがあるが、トランジスタ
・タイプ・パッケージはリード線の数が３〜１２本の回
路に限られ、リード線の配列が円形なのでプリント板の
配線の効率が悪い。また、フラット・タイプ・パッケー
ジはリード線の数は最高１４本で装置は小型化できる
が、熱放散が悪く、取扱いに少々難点がある。更に、イ
ンライン・タイプ・パッケージはリード線は１４本程度
であり、リードの強さもあるので自動挿入も可能である
が、前記他のパッケージより高価であった。There are several types of packages manufactured so as to satisfy these conditions, in which lead wires are externally drawn out. However, the transistor type package has 3 to 12 lead wires. Only the circuit of the book, the arrangement of the lead wire is circular, the wiring efficiency of the printed board is poor. In addition, the flat type package has a maximum of 14 lead wires and can be downsized, but the heat dissipation is poor and the handling is a little difficult. Further, since the in-line type package has about 14 lead wires and has a strong lead, it can be automatically inserted, but it is more expensive than the other packages.
【０００５】従って、リード線を外部に引き出す上記タ
イプのパッケージでは、パッケージの実装面積を大きく
しない限り、リード線の数を多くするのに限度があっ
た。そこで、端子数を増加させて、しかも小型に実装す
るパッケージとして、一般に、パット・アレイ・キャリ
ア（ＰＡＣ）または、ボール・グリッド・アレイ（ＢＧ
Ａ）と称する半導体パッケージが開発された。Therefore, in the package of the above-mentioned type in which the lead wire is drawn to the outside, there is a limit to increase the number of lead wires unless the mounting area of the package is increased. Therefore, as a package for increasing the number of terminals and mounting in a small size, generally, a pad array carrier (PAC) or a ball grid array (BG) is used.
A semiconductor package called A) has been developed.
【０００６】先ず、上記ボール・グリッド・アレイ（Ｂ
ＧＡ）の半導体パッケージとして、米国特許第５，１５
３，３８５号に、ワイヤーボンディング実装し、トラン
スファーモールドされた半導体パッケージに関する技術
が開示されている。First, the ball grid array (B
GA) semiconductor package as US Pat.
No. 3,385 discloses a technique related to a semiconductor package which is wire-bonded and transfer-molded.
【０００７】そこで、図３を用いて、上記米国特許第
５，１５３，３８５号に記載されているトランスファー
モールド半導体パッケージについてその概要を説明す
る。図３において、図３（ａ）は、半田バンプ形成前の
状態を示すボールグリッドアレイ型半導体パッケージの
断面図で、ガラスエポキシ樹脂等から作られたプリント
樹脂基板３０にはスルーホール３１が形成され、該スル
ーホール３１を含み、プリント樹脂基板３０の全表面に
金属メッキ層を施し、更に前記プリント樹脂基板３０の
上下面に感光性樹脂被膜を施し、パターン導体回路３２
やダイパターン３３を形成する。また更に、所定の部分
にソルダーレジスト処理を行い、レジスト膜３４を形成
することにより、前記プリント樹脂基板３０の下面側
に、マトリックス状に多数の同一形状の半田付け可能な
表面であるレジスト膜開口部、所謂パターンランド３５
を形成する。次に前記ダイパターン３３にＩＣチップ３
６を搭載して前記パターン導体回路３２とボンディング
ワイヤー３７で接続した後、該ＩＣチップ３６を熱硬化
性の封止樹脂３８でトランスファーモールドにより樹脂
封止することにより、前記ＩＣチップ３６の遮光と保護
を行う。更に前記プリント樹脂基板３０の上面側及び下
面側に形成されているパターン導体回路３２はスルーホ
ール３１を介して導通されている。Therefore, an outline of the transfer mold semiconductor package described in the above-mentioned US Pat. No. 5,153,385 will be described with reference to FIG. In FIG. 3, FIG. 3A is a sectional view of the ball grid array type semiconductor package showing a state before formation of solder bumps. Through holes 31 are formed in a printed resin board 30 made of glass epoxy resin or the like. A metal plating layer is applied to the entire surface of the printed resin board 30 including the through holes 31, and a photosensitive resin film is applied to the upper and lower surfaces of the printed resin board 30 to form a patterned conductor circuit 32.
And the die pattern 33 are formed. Furthermore, a solder resist process is performed on a predetermined portion to form a resist film 34, so that a plurality of resist film openings, which are solderable surfaces of the same shape in a matrix, are formed on the lower surface side of the printed resin substrate 30. Part, so-called pattern land 35
To form. Next, the IC chip 3 is formed on the die pattern 33.
6 is mounted and connected to the patterned conductor circuit 32 by the bonding wire 37, and then the IC chip 36 is resin-sealed with a thermosetting sealing resin 38 by transfer molding, so that the IC chip 36 is shielded from light. Protect. Further, the pattern conductor circuits 32 formed on the upper surface side and the lower surface side of the printed resin board 30 are electrically connected through the through holes 31.
【０００８】また、図３（ｂ）は、半田バンプ形成後の
状態を示すボールグリッドアレイ型半導体パッケージの
断面図、図３（ｃ）は完成したボールグリッドアレイ型
半導体パッケージの変形状態を示す断面図である。前記
プリント樹脂基板３０の下面側には、複数の半田付け可
能なパターンランド３５にそれぞれ同形の半田ボールを
供給し、加熱炉中で加熱することにより、マザーボード
４１との接続用の半田バンプ３９を形成することができ
る。以上によりボールグリッドアレイ型半導体パッケー
ジ４０が完成される。Further, FIG. 3B is a sectional view of the ball grid array type semiconductor package showing a state after the solder bumps are formed, and FIG. 3C is a sectional view showing a deformed state of the completed ball grid array type semiconductor package. It is a figure. On the lower surface side of the printed resin board 30, solder balls 39 of the same shape are respectively supplied to a plurality of solderable pattern lands 35 and heated in a heating furnace to form solder bumps 39 for connection with the mother board 41. Can be formed. As described above, the ball grid array type semiconductor package 40 is completed.
【０００９】[0009]
【発明が解決しようとする課題】しかしながら、前述し
たボールグリッドアレイ型半導体パッケージには、次の
ような問題点がある。即ち、前記ボールグリッドアレイ
型半導体パッケージを構成するプリント樹脂基板に使用
されるガラスエポキシ樹脂とトランスファーモールドに
使用される熱硬化性樹脂とで、それぞれの樹脂の線膨張
係数は、ガラスエポキシ樹脂は１４×１０-6１／°Ｃ、
熱硬化性樹脂は１６×１０-6１／°Ｃと異なり、従っ
て、両者の収縮率が異なる。前記した如くガラスエポキ
シ樹脂と熱硬化性樹脂とでは、収縮率は熱硬化性樹脂の
方が大きいので、トランスファーモールド後は図３
（ｃ）に示すようにボールグリッドアレイ型半導体パッ
ケージは椀状に湾曲し、プリント樹脂基板の下面側に形
成した複数の半田バンプの先端は、外周部に向かって漸
次浮き量が大きくなり、マザーボードとの接触が阻害さ
れてマザーボードとの導通不良を生ずる致命的な問題が
あった。However, the above-mentioned ball grid array type semiconductor package has the following problems. That is, the linear expansion coefficient of each of the glass epoxy resin used for the printed resin substrate and the thermosetting resin used for the transfer molding constituting the ball grid array type semiconductor package is 14 for the glass epoxy resin. × 10 -6 1 / ° C,
The thermosetting resin is different from 16 × 10 -6 1 / ° C, and therefore the shrinkage rate of both is different. As described above, the shrinkage rate of the glass epoxy resin and the thermosetting resin is larger than that of the thermosetting resin.
As shown in (c), the ball grid array type semiconductor package is curved in a bowl shape, and the tips of the plurality of solder bumps formed on the lower surface side of the printed resin board gradually increase in the amount of floating toward the outer peripheral portion. There is a fatal problem that the contact with the motherboard is obstructed and the conduction failure with the motherboard occurs.
【００１０】本発明は上記従来の課題に鑑みなされたも
のであり、その目的は、マザーボードとの導通性のよい
ボールグリッドアレイ型半導体パッケージを安価に提供
するものである。The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a ball grid array type semiconductor package having good electrical conductivity with a mother board at low cost.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、本発明におけるボールグリッドアレイ型半導体パッ
ケージの構造は、下面側にマザーボード接続用の複数の
半田バンプを有するプリント樹脂基板の上面側にＩＣチ
ップをワイヤーボンディング実装し、該ＩＣチップをト
ランスファーモールドにより樹脂封止するボールグリッ
ドアレイ型半導体パッケージの構造において、前記複数
の半田バンプの高さを、プリント樹脂基板の中央部から
外周部に向かって漸次変化させることを特徴とするもの
である。In order to achieve the above object, the structure of the ball grid array type semiconductor package according to the present invention comprises a printed resin board having a plurality of solder bumps for connecting a mother board on the lower surface side. In a structure of a ball grid array type semiconductor package in which an IC chip is mounted by wire bonding and the IC chip is resin-sealed by transfer molding, the heights of the plurality of solder bumps are directed from the central portion of the printed resin board toward the outer peripheral portion. It is characterized in that it is gradually changed.
【００１２】前記プリント樹脂基板の下面側に形成する
複数の半田バンプそれぞれの半田ボール供給量は同一
で、半田付け可能な表面のレジスト膜開口径を、プリン
ト樹脂基板の中央部から外周部に向かって漸次変化させ
ることを特徴とするものである。The supply amount of solder balls for each of the plurality of solder bumps formed on the lower surface side of the printed resin board is the same, and the resist film opening diameter on the solderable surface is directed from the central portion to the outer peripheral portion of the printed resin board. It is characterized in that it is gradually changed.
【００１３】前記レジスト膜開口径を、プリント樹脂基
板の中央部から外周部に向かって漸次小さくなる如く形
成することを特徴とするものである。It is characterized in that the resist film opening diameter is formed so as to become gradually smaller from the central portion of the printed resin substrate toward the outer peripheral portion.
【００１４】前記複数のレジスト膜開口径は同一で、複
数の半田バンプを形成する半田ボール供給量を、プリン
ト樹脂基板の中央部から外周部に向かって漸次変化させ
ることを特徴とするものである。The plurality of resist film openings have the same diameter, and the supply amount of solder balls for forming a plurality of solder bumps is gradually changed from the central portion of the printed resin substrate toward the outer peripheral portion. .
【００１５】前記複数の半田バンプを形成する半田ボー
ル供給量を、プリント樹脂基板の中央部から外周部に向
かって漸次多くすることを特徴とするものである。It is characterized in that the supply amount of the solder balls for forming the plurality of solder bumps is gradually increased from the central portion of the printed resin substrate toward the outer peripheral portion.
【００１６】[0016]
【作用】従って、本発明により得られるボールグリッド
アレイ型半導体パッケージの構造において、前述したよ
うに、プリント樹脂基板に使用されるガラスエポキシ樹
脂とトランスファーモールドに使用される熱硬化性樹脂
とで、前記ガラスエポキシ樹脂と熱硬化性樹脂とでは、
収縮率は熱硬化性樹脂の方が大きいので、ボールグリッ
ドアレイ型半導体パッケージは椀状に湾曲し、プリント
樹脂基板の下面側に形成した複数の半田バンプの先端
は、外周部に向かって漸次浮き量が大きくなる。従っ
て、前記浮き量に対応して、半田ボールの量を同一にし
て、レジスト膜開口径を中央部から外周部に向かって漸
次小さくする如く形成するか、または前記レジスト膜開
口径を同一にして、半田ボールの供給量を中央部から外
周部に向かって漸次多くすることにより、結果としてマ
トリックス状に形成された複数の半田バンプの先端の高
さが均一に揃うので、半導体パッケージが湾曲していて
も、半田バンプはプリント樹脂基板の中央部から外周部
に至りマザーボードと均等に接触することが可能にな
り、マザーボードと導通性のよいボールグリッドアレイ
型半導体パッケージが得られる。Therefore, in the structure of the ball grid array type semiconductor package obtained by the present invention, as described above, the glass epoxy resin used for the printed resin substrate and the thermosetting resin used for the transfer mold are With glass epoxy resin and thermosetting resin,
Since the thermosetting resin has a higher shrinkage rate, the ball grid array type semiconductor package is curved like a bowl, and the tips of the solder bumps formed on the lower surface of the printed resin board gradually float toward the outer peripheral portion. The amount increases. Therefore, in accordance with the floating amount, the solder ball amount is made the same, and the resist film opening diameter is gradually reduced from the central portion to the outer peripheral portion, or the resist film opening diameter is made the same. By gradually increasing the supply amount of the solder balls from the central part toward the outer peripheral part, as a result, the heights of the tips of the plurality of solder bumps formed in a matrix are uniformly aligned, and the semiconductor package is curved. However, the solder bumps can be evenly contacted with the motherboard from the central portion of the printed resin substrate to the outer peripheral portion, and a ball grid array type semiconductor package having good conductivity with the motherboard can be obtained.
【００１７】[0017]
【実施例】以下図面に基づいて好適な実施例を説明す
る。図１は本発明の一実施例で、図１（ａ）はボールグ
リッドアレイ型半導体パッケージの下面側の平面図、図
１（ｂ）はその断面図である。図１（ａ）及び図１
（ｂ）において、従来技術と同一部材は同一符号で示し
説明は省略する。プリント樹脂基板３０の下面側に、マ
トリックス状に多数の半田付け可能な表面であるレジス
ト膜３４の開口部、所謂パターンランド１０を形成す
る。前記パターンランド１０のレジスト膜開口径ｄ１，
ｄ２、ｄ３は、前記半導体パッケージの湾曲に相応し
て、プリント樹脂基板３０の中央部から外周部に向かっ
て漸次小さくなる如く、即ちｄ１＞ｄ２＞ｄ３のように
形成することにより、図１（ｂ）に示すように、供給す
る半田ボールは同一でも、半田バンプ１１の高さｈ１，
ｈ２，ｈ３はプリント樹脂基板３０の中央部から外周部
に向かって漸次細く高くなり、即ちｈ１＜ｈ２＜ｈ３の
ように形成される。従って、半導体パッケージが椀状に
湾曲していても、マトリックス状に形成された複数の半
田バンプ１１の先端が均一に揃い、マザーボード４１と
均等に接触することができる。従って、従来の製造設備
を変えることなく、導通不良が皆無になり、製造コスト
の低減と導通性の向上を図ることが可能となる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment will be described below with reference to the drawings. 1 is an embodiment of the present invention, FIG. 1 (a) is a plan view of the lower surface side of a ball grid array type semiconductor package, and FIG. 1 (b) is a sectional view thereof. 1 (a) and 1
In (b), the same members as those in the conventional technique are designated by the same reference numerals and the description thereof will be omitted. On the lower surface side of the printed resin board 30, a large number of openings of the resist film 34, so-called pattern lands 10, which are solderable surfaces, are formed in a matrix. The resist film opening diameter d1 of the pattern land 10
According to the curve of the semiconductor package, d2 and d3 are gradually reduced from the central portion of the printed resin substrate 30 toward the outer peripheral portion, that is, d1>d2> d3. As shown in b), even if the supplied solder balls are the same, the height h1,
h2 and h3 are gradually increased from the central portion of the printed resin substrate 30 toward the outer peripheral portion thereof, that is, formed as h1 <h2 <h3. Therefore, even if the semiconductor package is curved like a bowl, the tips of the plurality of solder bumps 11 formed in a matrix can be uniformly aligned and can evenly contact the motherboard 41. Therefore, without changing the conventional manufacturing equipment, there is no conduction failure, and it is possible to reduce the manufacturing cost and improve the conductivity.
【００１８】次に、図２は本発明の他の実施例で、図２
（ａ）はボールグリッドアレイ型半導体パッケージの下
面側の平面図、図２（ｂ）はその断面図である。図２
（ａ）及び図２（ｂ）において、従来技術と同一部材は
同一符号で示し説明は省略する。プリント樹脂基板３０
の下面側に、マトリックス状に多数の半田付け可能な表
面であるレジスト膜３４の開口部、所謂パターンランド
１２は従来技術と同様に全て同一形状に形成する。前記
パターンランド１２に供給する複数の半田ボール供給量
を、前記半導体パッケージの湾曲に相応して、プリント
樹脂基板の中央部から外周部に向かって漸次多くするこ
とにより、形成される半田バンプ１３の高さｈ１，ｈ
２，ｈ３はプリント樹脂基板３０の中央部から外周部に
向かって漸次高くなり、即ちｈ１＜ｈ２＜ｈ３のように
形成される。従って、前記実施例と同様に、半導体パッ
ケージが椀状に湾曲していても、マトリックス状に形成
された複数の半田バンプ１３の先端が均一に揃い、マザ
ーボード４１と均等に接触することができる。Next, FIG. 2 shows another embodiment of the present invention.
2A is a plan view of the lower surface side of the ball grid array type semiconductor package, and FIG. 2B is a sectional view thereof. Figure 2
In (a) and FIG. 2 (b), the same members as those of the conventional technique are designated by the same reference numerals and the description thereof will be omitted. Printed resin board 30
On the lower surface side, the openings of the resist film 34, so-called pattern lands 12, which are many solderable surfaces in a matrix, are all formed in the same shape as in the prior art. The supply amount of the plurality of solder balls supplied to the pattern land 12 is gradually increased from the central portion of the printed resin substrate toward the outer peripheral portion in accordance with the curvature of the semiconductor package, so that the solder bumps 13 are formed. Height h1, h
2 and h3 gradually increase from the central portion of the printed resin substrate 30 toward the outer peripheral portion, that is, h1 <h2 <h3. Therefore, similarly to the above-described embodiment, even if the semiconductor package is curved like a bowl, the tips of the plurality of solder bumps 13 formed in a matrix can be uniformly aligned and can evenly contact the mother board 41.
【００１９】上述の如く、本実施例の特徴とするところ
は、ボールグリッドアレイ型半導体パッケージの構造
は、前述したように、プリント樹脂基板とトランスファ
ーモールドで樹脂封止する封止樹脂の収縮率の相違に起
因する半導体パッケージの椀状の湾曲に相応して、プリ
ント樹脂基板の下面側に形成する複数の半田バンプの高
さを中央部から外周部に向かって漸次高くすることによ
って、前記半田バンプの先端の高さを均一に揃えるもの
である。具体的には、供給する半田ボールの量は同一
で、レジスト膜開口径を中央部から外周部に向かって漸
次小さく形成する、即ち半田バンプは、中央部から外周
部に向かって漸次細く高くなるように形成するか、また
はレジスト膜開口径は同一形状で、供給する半田ボール
量を中央部から外周部に向かって漸次多くする、即ち半
田バンプは、中央部から外周部に向かって漸次高くなる
ように形成する。以上により、半導体パッケージが椀状
に湾曲していても、マトリックス状に形成された複数の
半田バンプの先端が均一に揃い、マザーボードと均等に
接触することが可能である。As described above, the feature of this embodiment is that the structure of the ball grid array type semiconductor package is, as described above, the shrinkage ratio of the sealing resin which is resin-sealed with the printed resin substrate and the transfer mold. Corresponding to the bowl-shaped curvature of the semiconductor package due to the difference, the height of the plurality of solder bumps formed on the lower surface side of the printed resin board is gradually increased from the central portion toward the outer peripheral portion, whereby the solder bumps are formed. The heights of the tips of the are even. Specifically, the amount of solder balls to be supplied is the same, and the resist film opening diameter is formed to be gradually smaller from the central portion to the outer peripheral portion, that is, the solder bump is gradually thinner and higher from the central portion to the outer peripheral portion. Or the resist film opening diameter is the same, and the amount of supplied solder balls is gradually increased from the central portion to the outer peripheral portion, that is, the solder bump is gradually increased from the central portion to the outer peripheral portion. To form. As described above, even if the semiconductor package is curved like a bowl, the tips of the plurality of solder bumps formed in a matrix can be uniformly aligned and can be evenly contacted with the motherboard.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
一般にプリント樹脂基板とトランスファーモールドで樹
脂封止する封止樹脂に収縮率の異なる樹脂を使用するこ
とにより生ずる半導体パッケージの椀状の変形を回避す
ることは困難であるが、半導体パッケージの椀状の変形
に相応して、プリント樹脂基板の下面側に形成する複数
の半田バンプの高さを変化させることにより、半田バン
プの先端を均一に揃えることが容易であり、余分な製造
工数をかけることなく、導通不良が低減し、マザーボー
ドとの導通性が向上し、品質の良い、安価なボールグリ
ッドアレイ型半導体パッケージを提供することができ
る。As described above, according to the present invention,
Generally, it is difficult to avoid bowl-shaped deformation of a semiconductor package caused by using resins having different shrinkage rates as a sealing resin that is resin-molded with a print resin substrate and transfer mold. By changing the height of multiple solder bumps formed on the lower surface side of the printed resin board according to the deformation, it is easy to make the tips of the solder bumps even, and without extra manufacturing man-hours. In addition, it is possible to provide a good-quality and inexpensive ball grid array type semiconductor package in which conduction defects are reduced and conductivity with a mother board is improved.
【図１】本発明の一実施例に係わるボールグリッドアレ
イ型半導体パッケージの構造を示し、図１（ａ）は下面
側の平面図、図１（ｂ）は断面図。1A and 1B show a structure of a ball grid array type semiconductor package according to an embodiment of the present invention, FIG. 1A is a plan view of a lower surface side, and FIG. 1B is a sectional view.
【図２】本発明の他の実施例に係わるボールグリッドア
レイ型半導体パッケージの構造を示し、図２（ａ）は下
面側の平面図、図２（ｂ）は断面図。2 shows a structure of a ball grid array type semiconductor package according to another embodiment of the present invention, FIG. 2 (a) is a plan view of the lower surface side, and FIG. 2 (b) is a sectional view.
【図３】従来のボールグリッドアレイ型半導体パッケー
ジの構造を示す断面図。FIG. 3 is a sectional view showing a structure of a conventional ball grid array type semiconductor package.
１０ パターンランド １１ 半田バンプ １２ パターンランド １３ 半田バンプ ３０ プリント樹脂基板 ３２ パターン導体回路 ３４ レジスト膜 ３８ 封止樹脂 ４１ マザーボード ｄ１ レジスト膜開口径 ｄ２ レジスト膜開口径 ｄ３ レジスト膜開口径 ｈ１ 半田バンプ高さ ｈ２ 半田バンプ高さ ｈ３ 半田バンプ高さ 10 pattern land 11 solder bump 12 pattern land 13 solder bump 30 printed resin substrate 32 pattern conductor circuit 34 resist film 38 sealing resin 41 motherboard d1 resist film opening diameter d2 resist film opening diameter d3 resist film opening diameter h1 solder bump height h2 Solder bump height h3 Solder bump height
Claims (5)
田バンプを有するプリント樹脂基板の上面側にＩＣチッ
プをワイヤーボンディング実装し、該ＩＣチップをトラ
ンスファーモールドにより樹脂封止するボールグリッド
アレイ型半導体パッケージの構造において、前記複数の
半田バンプの高さを、プリント樹脂基板の中央部から外
周部に向かって漸次変化させることを特徴とするボール
グリッドアレイ型半導体パッケージの構造。1. A ball grid array type semiconductor package in which an IC chip is wire-bonded on the upper surface side of a printed resin board having a plurality of solder bumps for connecting a mother board on the lower surface side and the IC chip is resin-sealed by transfer molding. 2. The structure of the ball grid array type semiconductor package according to the above structure, wherein the heights of the plurality of solder bumps are gradually changed from the central portion of the printed resin board toward the outer peripheral portion.
る複数の半田バンプそれぞれの半田ボール供給量は同一
で、半田付け可能な表面のレジスト膜開口径を、プリン
ト樹脂基板の中央部から外周部に向かって漸次変化させ
ることを特徴とする請求項１記載のボールグリッドアレ
イ型半導体パッケージの構造。2. The solder ball supply amount of each of the plurality of solder bumps formed on the lower surface side of the printed resin board is the same, and the resist film opening diameter of the solderable surface is from the central portion to the outer peripheral portion of the printed resin board. 2. The structure of the ball grid array type semiconductor package according to claim 1, wherein the structure is gradually changed toward.
基板の中央部から外周部に向かって漸次小さくする如く
形成することを特徴とする請求項２記載のボールグリッ
ドアレイ型半導体パッケージの構造。3. The structure of the ball grid array type semiconductor package according to claim 2, wherein the resist film opening diameter is formed so as to gradually decrease from the central portion of the printed resin substrate toward the outer peripheral portion.
複数の半田バンプを形成する半田ボール供給量を、プリ
ント樹脂基板の中央部から外周部に向かって漸次変化さ
せることを特徴とする請求項１記載のボールグリッドア
レイ型半導体パッケージの構造。4. The opening diameters of the plurality of resist films are the same,
2. The structure of the ball grid array type semiconductor package according to claim 1, wherein the supply amount of solder balls forming a plurality of solder bumps is gradually changed from the central portion of the printed resin substrate toward the outer peripheral portion.
ール供給量を、プリント樹脂基板の中央部から外周部に
向かって漸次多くすることを特徴とする請求項４記載の
ボールグリッドアレイ型半導体パッケージの構造。5. The ball grid array type semiconductor package according to claim 4, wherein the supply amount of the solder balls for forming the plurality of solder bumps is gradually increased from the central portion of the printed resin board toward the outer peripheral portion. Structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19166693A JP3291368B2 (en) | 1993-07-06 | 1993-07-06 | Structure of ball grid array type semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19166693A JP3291368B2 (en) | 1993-07-06 | 1993-07-06 | Structure of ball grid array type semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0722538A true JPH0722538A (en) | 1995-01-24 |
| JP3291368B2 JP3291368B2 (en) | 2002-06-10 |
Family
ID=16278442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19166693A Expired - Lifetime JP3291368B2 (en) | 1993-07-06 | 1993-07-06 | Structure of ball grid array type semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3291368B2 (en) |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477011A (en) * | 1988-04-18 | 1989-03-23 | Minolta Camera Kk | Automatic focusing interchangeable lens camera |
| JPH07193162A (en) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | Ball-grid array semiconductor device and mounting substrate thereof |
| JPH08162560A (en) * | 1994-12-01 | 1996-06-21 | Matsushita Electric Ind Co Ltd | Electronic part |
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
| JPH098081A (en) * | 1995-06-20 | 1997-01-10 | Fujitsu General Ltd | Mounting structure of bga package |
| JPH0927568A (en) * | 1995-07-05 | 1997-01-28 | Anam Ind Co Inc | Method of flattening solder ball of ball grid array semiconductor package using solder ball as input-output terminal and its substrate structure |
| EP0729182A3 (en) * | 1995-02-23 | 1997-02-19 | Matsushita Electric Ind Co Ltd | Chip carrier and method of manufacturing and mounting the same |
| WO1997016849A1 (en) * | 1995-11-02 | 1997-05-09 | Minnesota Mining And Manufacturing Company | Ball grid array integrated circuit socket |
| JPH09129287A (en) * | 1995-10-31 | 1997-05-16 | Aisin Seiki Co Ltd | Circuit board device |
| JPH09283562A (en) * | 1996-04-18 | 1997-10-31 | Nec Corp | Integrated circuit device and method of connecting it to substrate |
| EP0814511A3 (en) * | 1996-06-19 | 1998-11-18 | International Business Machines Corporation | Plastic ball grid array module |
| JPH11150207A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Microelectronics Corp | Semiconductor device and manufacture thereof |
| JPH11163216A (en) * | 1997-11-28 | 1999-06-18 | Nec Corp | Semiconductor device and manufacture thereof |
| JP2002057248A (en) * | 1995-02-09 | 2002-02-22 | Kyocera Corp | Package and mounting structure thereof |
| JP2002100704A (en) * | 1995-02-09 | 2002-04-05 | Kyocera Corp | Package and mounting structure thereof |
| US6400019B1 (en) | 1999-11-25 | 2002-06-04 | Hitachi, Ltd. | Semiconductor device with wiring substrate |
| JP2002164473A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Semiconductor device and method for manufacturing the same |
| US6916683B2 (en) * | 2000-05-11 | 2005-07-12 | Micron Technology, Inc. | Methods of fabricating a molded ball grid array |
| JP2006190902A (en) * | 2005-01-07 | 2006-07-20 | Denso Corp | Method of packaging semiconductor electronic component, and wiring board of semiconductor electronic component |
| JP2007081150A (en) * | 2005-09-14 | 2007-03-29 | Rohm Co Ltd | Semiconductor device and substrate |
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
| US7667325B2 (en) * | 2006-05-10 | 2010-02-23 | Samsung Electronics Co., Ltd. | Circuit board including solder ball land having hole and semiconductor package having the circuit board |
| US8604614B2 (en) | 2010-03-26 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor packages having warpage compensation |
| JP2014220305A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer substrate and electronic device using the same, method of manufacturing electronic device |
| EP2733741A3 (en) * | 2012-10-25 | 2017-12-27 | NXP USA, Inc. | A packaged integrated circuit having large solder pads and method for forming |
| JP2021022718A (en) * | 2019-07-30 | 2021-02-18 | 力成科技股▲分▼有限公司 | Package structure and manufacturing method thereof |
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1993
- 1993-07-06 JP JP19166693A patent/JP3291368B2/en not_active Expired - Lifetime
Cited By (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477011A (en) * | 1988-04-18 | 1989-03-23 | Minolta Camera Kk | Automatic focusing interchangeable lens camera |
| JPH07193162A (en) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | Ball-grid array semiconductor device and mounting substrate thereof |
| JPH08162560A (en) * | 1994-12-01 | 1996-06-21 | Matsushita Electric Ind Co Ltd | Electronic part |
| JP2002100704A (en) * | 1995-02-09 | 2002-04-05 | Kyocera Corp | Package and mounting structure thereof |
| JP2002057248A (en) * | 1995-02-09 | 2002-02-22 | Kyocera Corp | Package and mounting structure thereof |
| US6229209B1 (en) | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
| EP0729182A3 (en) * | 1995-02-23 | 1997-02-19 | Matsushita Electric Ind Co Ltd | Chip carrier and method of manufacturing and mounting the same |
| US6372547B2 (en) | 1995-02-23 | 2002-04-16 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board |
| US6365499B1 (en) * | 1995-02-23 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | Chip carrier and method of manufacturing and mounting the same |
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
| JPH098081A (en) * | 1995-06-20 | 1997-01-10 | Fujitsu General Ltd | Mounting structure of bga package |
| JPH0927568A (en) * | 1995-07-05 | 1997-01-28 | Anam Ind Co Inc | Method of flattening solder ball of ball grid array semiconductor package using solder ball as input-output terminal and its substrate structure |
| JPH09129287A (en) * | 1995-10-31 | 1997-05-16 | Aisin Seiki Co Ltd | Circuit board device |
| WO1997016849A1 (en) * | 1995-11-02 | 1997-05-09 | Minnesota Mining And Manufacturing Company | Ball grid array integrated circuit socket |
| DE19706983B4 (en) * | 1996-02-23 | 2009-06-18 | Denso Corporation, Kariya | Surface mounting unit and transducer assemblies using the surface mounting unit |
| JPH09283562A (en) * | 1996-04-18 | 1997-10-31 | Nec Corp | Integrated circuit device and method of connecting it to substrate |
| KR100294602B1 (en) * | 1996-06-19 | 2001-09-17 | 포만 제프리 엘 | Electronic ball grid array module with solder pads of different sizes |
| EP0814511A3 (en) * | 1996-06-19 | 1998-11-18 | International Business Machines Corporation | Plastic ball grid array module |
| JPH11150207A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Microelectronics Corp | Semiconductor device and manufacture thereof |
| JPH11163216A (en) * | 1997-11-28 | 1999-06-18 | Nec Corp | Semiconductor device and manufacture thereof |
| US6400019B1 (en) | 1999-11-25 | 2002-06-04 | Hitachi, Ltd. | Semiconductor device with wiring substrate |
| US6916683B2 (en) * | 2000-05-11 | 2005-07-12 | Micron Technology, Inc. | Methods of fabricating a molded ball grid array |
| JP2002164473A (en) * | 2000-11-29 | 2002-06-07 | Sharp Corp | Semiconductor device and method for manufacturing the same |
| JP2006190902A (en) * | 2005-01-07 | 2006-07-20 | Denso Corp | Method of packaging semiconductor electronic component, and wiring board of semiconductor electronic component |
| JP2007081150A (en) * | 2005-09-14 | 2007-03-29 | Rohm Co Ltd | Semiconductor device and substrate |
| US7667325B2 (en) * | 2006-05-10 | 2010-02-23 | Samsung Electronics Co., Ltd. | Circuit board including solder ball land having hole and semiconductor package having the circuit board |
| US7952199B2 (en) | 2006-05-10 | 2011-05-31 | Samsung Electronics Co., Ltd. | Circuit board including solder ball land having hole and semiconductor package having the circuit board |
| US8604614B2 (en) | 2010-03-26 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor packages having warpage compensation |
| US9048168B2 (en) | 2010-03-26 | 2015-06-02 | Samsung Electronics Co., Ltd. | Semiconductor packages having warpage compensation |
| EP2733741A3 (en) * | 2012-10-25 | 2017-12-27 | NXP USA, Inc. | A packaged integrated circuit having large solder pads and method for forming |
| JP2014220305A (en) * | 2013-05-06 | 2014-11-20 | 株式会社デンソー | Multilayer substrate and electronic device using the same, method of manufacturing electronic device |
| JP2021022718A (en) * | 2019-07-30 | 2021-02-18 | 力成科技股▲分▼有限公司 | Package structure and manufacturing method thereof |
| WO2022249526A1 (en) * | 2021-05-25 | 2022-12-01 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor package and electronic device |
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