JPH11150207A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which is able to keep the height of solder balls constant and can avoid reduction of manufacturing reliability in post steps, even when a warpage of a substrate having the solder balls formed thereon occurs in the form of a recessed or projected shape. SOLUTION: A package includes a substrate 2, a semiconductor chip mounted one end of the substrate 2, a plurality of solder balls 2 formed on the other side of the substrate, wiring means for electrically connecting the semiconductor chip and solder balls, and a sealing resin part 1 for sealing the semiconductor chip. In this case, in order to avoid the effects by warpages in the substrate 2, the solder balls 3 are set to have different heights, so that the balls 3 are able to have an identical top level, even in the case of the warpage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a BGA (Ball Grid).
Array) Package, especially TA as substrate
The present invention relates to a package having a BGA structure using a B tape substrate.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. In a conventional package having a BGA structure, a TAB tape is generally used as the substrate 22 on which the semiconductor chip 25 is mounted. The substrate supporting the wiring between the bonding portion (usually a copper foil) 24 disposed around the semiconductor chip and the via hole 27 connected to each ball arranged in an array on the lower surface of the substrate is an interlayer. Although a multi-layer TAB tape having a degree of freedom in wiring and a high mechanical strength is used depending on the wiring, a three-layer TAB tape is usually used.

A conventional BGA using a three-layer TAB tape
As shown in FIG. 7, the package is wired using a TAB tape substrate 22 having via holes 27 of the same diameter. First, the substrate 2 on which the bonding portion 24 is formed
After mounting the IC chip 25 on the substrate 2 and bonding the copper foil wiring 24 and the IC chip 25 with the wires 26, resin sealing is performed with the mold resin 21. Then, the via hole 27
The solder ball 23 is mounted on the bottom of the.

[0004] Even when a substrate without warpage is used,
As shown in FIG. 8, in the BGA package after resin sealing and mounting of the solder balls 23, the height of the solder balls is not constant, as indicated by A ″ in the figure. Usually, a variation of less than 0.1 mm occurs. Note that this variation is due to EIJA's FBGA (Fine Ball Grid Array).
).

However, due to differences in the coefficient of thermal expansion between the tape, the semiconductor chip, and the sealing resin, as shown in FIG. In some cases, the concave or convex shape may be warped. Due to the occurrence of the warpage B ′ ″, the height of the substrate is usually about 20 to 30 μm,
It moves up and down by about 0 μm (A ″ ′ in the figure). When the package is warped as described above, the height of the solder balls 23 provided on the substrate 22 varies.
Therefore, regarding the height of the solder ball 23, the FBGA
In some cases, it may be out of the standard, and this may cause board mounting failures in the subsequent steps, which has been a problem in terms of manufacturing yield and product reliability.

[0006]

A conventional multi-layer TAB tape, in particular, a three-layer TAB tape, is resin-sealed, and is used in a BGA package in which solder balls are mounted.
It is difficult to make the amount of solder of each solder ball constant, and as a result, the height of the solder ball typically varies by about 0.1 mm. Further, in the conventional package, the warp more than the variation in the height of the solder ball may occur in the concave or convex shape on the substrate of the TAB tape. For this reason, there were problems in accuracy and reliability in the subsequent steps. In addition, the variation in the height of the solder ball 23 causes a defective mounting on a substrate, and has a problem in terms of yield and product reliability.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to minimize variations in the height of solder balls due to warpage even when warpage of the package is unavoidable due to design. An object of the present invention is to provide a semiconductor device capable of improving yield and improving product reliability.

[0008]

According to the present invention, there is provided a semiconductor device comprising: a substrate; a semiconductor chip mounted on one side of the substrate; a plurality of solder balls formed on the other side; In a semiconductor device having a wiring means for electrically connecting a solder ball and a sealing resin portion for sealing the semiconductor chip, the top of the solder ball has a constant height by eliminating the influence of warpage generated on the substrate. A semiconductor device characterized in that a difference is provided in the height of the solder ball so as to have the following.

Further, each of the solder balls has a constant amount of solder, and the height of the solder balls is made different by changing the area of the solder ball bonding portion of the substrate. The semiconductor device is characterized in that the solder ball bonding portion is formed by a via hole formed in the substrate, and the height of the solder ball from the substrate to the lower portion of the solder ball increases outward. A semiconductor device characterized in that the substrate is made of a multilayer TAB tape; and the semiconductor device constitutes a BGA type package. It is a semiconductor device.

The method of manufacturing a semiconductor device according to the present invention further comprises a step of forming a substrate having a predetermined electric wiring pattern, and a step of forming a plurality of via holes having different diameters in the electric wiring pattern portion of the substrate. A step of bonding a semiconductor chip to one side of the substrate, a step of electrically connecting an electric wiring pattern of the substrate and the semiconductor chip, a step of resin-sealing the semiconductor chip, and a step of forming the via hole on the other side of the substrate. And a step of fusing a solder ball to a portion.

[0011] Further, the manufacturing method is characterized in that the via hole is formed so that the via diameter becomes smaller as going outward, and the height from the other surface of the substrate to the lower portion of the solder ball is reduced. The manufacturing method is characterized in that the substrate is formed so as to become larger toward the outer peripheral portion of the substrate.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the following embodiments with reference to the drawings, but the present invention is not limited to the embodiments described here. The following embodiments can be variously changed.

FIG. 1 schematically shows an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a cross-sectional view showing the features of the embodiment of the present invention, and has basically the same internal structure as that of FIG. 7, except for the area of the solder ball bonding portion formed on the substrate. The difference is that the diameter of the via hole in which the solder ball is installed is different.

One embodiment of the semiconductor device according to the present invention is as follows.
As shown in FIG. 1, a BGA package in which a semiconductor chip (not shown) is mounted is sealed with a molding resin 1, and a multi-layered, in particular, three-layered TAB tape substrate 2 is used. Via holes 4 are formed in the substrate to electrically connect the upper and lower portions of the substrate, and solder balls are formed in the lower via hole openings.

In such a structure, if it is unavoidable that the substrate warps upward in the peripheral portion of the package due to design, the warpage is corrected by providing a difference in the height of the solder ball formed below. It is.
That is, the height of the solder ball is made different so that the height of the top of the solder ball is constant so that the solder ball can uniformly contact the surface of the printed board on which the semiconductor device is mounted.

For this reason, the diameters φ1, φ2, φ3 of the via holes 4 are defined as φ1>φ2> φ3.
A via hole is formed so as to gradually decrease toward the outside. The height of the solder ball naturally depends on the amount of solder, but when the amount of solder is constant, it depends on the area of the bottom of the via hole 4 where the solder ball is formed.
As the area of the bottom is larger, the amount of solder for filling the via hole 4 increases, and the amount of solder forming the solder ball decreases accordingly, so that the height of the solder ball decreases. Further, even when there is no via hole, if the bonding area of the solder ball bonding portion formed on the lower surface of the substrate increases, the solder spreads laterally, so that the height of the solder ball decreases accordingly. Therefore,
The area of the bonding portion, that is, the diameter of the via hole 4 is defined as φ1> φ
When gradually decreasing toward the outside such that 2> φ3, the height of the solder ball formed there increases as the position approaches the outside.

Before the package is warped,
By designing the via hole so that its diameter becomes gradually smaller as it goes to φ1>φ2> φ3, the solder ball 3 ′ ″ installed at the outermost φ3 diameter and the inner φ1 diameter are set. A step A occurs between the height of the solder ball and the height of the solder ball 3 ′.

Next, the state after the package is warped is shown in FIG.
Shown in Although the warp B occurs in the package, since the height of the solder balls is previously changed so as to cancel the warp, each solder ball 3 comes into contact with the substrate 2. Naturally, the step A 'between the solder balls 3 is eliminated.

Next, various conditions for carrying out the present invention will be described. FIG. 3 shows a method of obtaining the height of the solder ball from the relationship between the diameter of the via hole and the volume of the solder ball according to the present invention.

As shown in FIG. 3, VA is the volume of the via hole column, VB is the volume of the solder ball portion obtained by subtracting the volume of the via hole column from the volume of the pure solder ball, and H is the height of the ball portion (after reflow). , R is the radius of the ball portion (after reflow), h is the length obtained by subtracting the radius of the ball portion from the height of the ball portion, DV is the via hole diameter, and t is the depth of the via hole column. The respective relationships are shown below.

[0021]

(Equation 1)

Assuming that VS is the volume of a pure solder ball, VS is given by the equation (1). Here, VA is the volume of the via-hole column, and is expressed by equation (2). VB is the volume of the solder ball portion obtained by subtracting the volume of the via hole column from the volume of the pure solder ball, and is expressed by the following equation (3).

As described above, DV, which is the via diameter (Via diameter), is obtained from equations (1), (2), and (3), and DV is expressed by equation (4). Then, the radius R of the solder ball portion is obtained from Expression (4), and becomes the expression shown in Expression (5).

Based on the above formula, when the diameter of the solder ball before fusion was 0.5 mm, the relationship between the radius R of the solder ball after fusion at the bottom of the via hole and the via diameter DV was determined. Then, with the height H of the solder ball portion as the horizontal axis, the via diameter D
FIG. 4 shows the calculation results when V is taken on the vertical axis.

As shown in FIG. 4, the height of the solder ball decreases as the via diameter DV increases. The height H of the solder ball and the via diameter DV are represented by a constant function, and the height of the solder ball can be controlled by the size of the via diameter.

Next, an example of an actual BGA package will be described. In FIG. 5, 3 is located around the BGA package.
A part of a plan view in which 16 vertical and 16 horizontal solder balls are arranged on a package in a row arrangement is shown. D represents the center of the package, and E represents the outermost periphery of the solder ball.

The diameter of one solder ball in FIG. 5 is assumed to be Ф1, and the distance between the centers of one solder ball and an adjacent solder ball is assumed to be C. At this time, as shown in FIG. 5, where one wire passes between the solder balls, the installation width of one wire is 0.1 mm, and C is 0.1 mm.
When the width is 8 mm, 0.7 mm excluding the wiring width of 0.1 mm
The diameter of the solder ball must be less than 1 mm. In addition, two wires are placed between the solder balls.
Where there is a main line, the installation width of one wire is 0.1
mm, and when C is 0.8 mm, the installation width of the wiring is 0.1 mm.
Solder ball diameter less than 0.6mm excluding 2mmФ1
Must be created. Therefore, such BGA
On the board, the solder amount of the ball, the via diameter, and the
The depth of the via is determined, and the via diameter is changed according to the expected warpage. When the substrate warps upward, the via diameter at the center is set to, for example, a maximum of 0.6 mm, and the via diameter becomes smaller according to the degree of the warping toward the outside.

Next, in the BGA package shown in FIG. 6, balls are arranged in a lattice pattern on the entire surface. FIG. 6 shows a part of a plan view in which 16 vertical and 16 horizontal solder balls are arranged on a package. As in FIG. 5, D represents the center of the package, and E represents the outermost periphery of the solder ball.

As shown in FIG. 6, where two wires pass between the solder balls, the width of one wire is set to 0.1 mm, and when C is 0.8 mm,
The solder ball diameter Ф1 must be created at less than 0.6 mm except for the wiring installation width of 0.2 mm. Also, where three wires pass between solder balls, the installation width of one wire is 0.1 mm, and when C is 0.8 mm, the installation width of the wire is 0.3 mm. The diameter of the solder ball Ф1 must be created with less than 0.5 mm excluding. Therefore, in such a substrate, the solder amount of the ball, the via diameter, and the via depth are determined so that the solder ball diameter Ф1 is within 0.5 mm at the maximum, and the via diameter is changed according to the expected warpage. .

According to the present invention, the height of the solder ball can be controlled in consideration of the above conditions, and the height of the solder ball can be controlled by controlling the via diameter even when the package is warped. The problem can be solved by changing step by step. As described above, it is possible to improve the yield and reliability of products.

[0031]

According to the present invention, the height of the solder ball in the package of the semiconductor device can be arbitrarily controlled, and even when the package is warped, the height of the solder ball is controlled by controlling the via diameter. The problem can be solved by changing step by step. As a result, it is possible to improve the yield and reliability of products.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a perspective view showing a solder ball in the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a relationship between a height of a solder ball and a via diameter according to the embodiment of the present invention.

FIG. 5 is a plan view showing a peripheral three-row arrangement structure of a BGA package of the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a plan view showing the entire lattice arrangement structure of the BGA package of the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a sectional view showing an example of a conventional BGA package.

FIG. 8 is a sectional view showing a conventional BGA package.

FIG. 9 is a sectional view showing a conventional BGA package.

[Description of Signs] 1, 21: Mold resin 2, 22: 3-layer TAB tape substrate 3, 3 ', 3 ", 3"', 23: Solder ball 4, 27: Via hole 24: Copper foil 25: Chip 26: Wires A, A ', A ", A'" ... Difference in height between the highest solder ball and the lowest solder ball B, B ', B ", B '''… Curved portion C… Distance between pin centers D… Package center E… Outermost circumference of package pin Ф1, Ф2… Pin diameter φ1… Diameter of via hole (small) φ2… Diameter of via hole (middle) φ3: diameter of via hole (large) VS: volume of pure solder ball VA: volume of via hole column VB: volume of solder ball portion obtained by subtracting volume of connection portion of via hole column from pure solder ball volume H: ball portion Height (after reflow) R: radius of ball (reflow) ) H ... length DV ... the depth of the via diameter t ... via hole pillar which is obtained by subtracting the radius of the ball portion from the height of the ball portion

Claims (9)

[Claims] 1. A substrate, a semiconductor chip mounted on one side of the substrate, a plurality of solder balls formed on the other side, and wiring means for electrically connecting the semiconductor chip and the solder balls; In a semiconductor device having a sealing resin portion for sealing the semiconductor chip, the height of the solder ball is adjusted so that the influence of the warpage generated on the substrate is eliminated and the top of the solder ball has a constant height. A semiconductor device comprising: 2. The method according to claim 1, wherein each of the solder balls has a constant amount of solder, and the height of the solder balls is made different by changing the area of the solder ball bonding portion of the substrate. 3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein said solder ball bonding portion is formed by a via hole formed in said substrate. 4. The semiconductor device according to claim 1, wherein the height of the solder ball from the substrate to the lower portion of the solder ball increases toward the outside. 5. The semiconductor device according to claim 1, wherein said substrate is made of a multilayer TAB tape. 6. The semiconductor device according to claim 1, wherein said semiconductor device forms a BGA type package.
The semiconductor device according to claim 1. 7. A step of forming a substrate having a predetermined electric wiring pattern, a step of forming a plurality of via holes having different diameters in the electric wiring pattern portion of the substrate, and forming a semiconductor chip on one side of the substrate. Coupling, electrically connecting a semiconductor chip with an electric wiring pattern of the substrate, resin sealing the semiconductor chip, and fusing a solder ball to the via hole on the other side of the substrate. A method for manufacturing a semiconductor device, comprising: 8. The method of manufacturing a semiconductor device according to claim 7, wherein the via hole is formed so that the via diameter becomes smaller as going outward. 9. The semiconductor device according to claim 7, wherein a height from the other surface of the substrate to a lower portion of the solder ball is increased toward an outer peripheral portion of the substrate. Item 9. The method for manufacturing a semiconductor device according to Item 8.