JP2002217240A - Flip chip mounting structure and wiring method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible the mounting and wiring of a narrow-pitch multi-pin flip chip using a multilayered substrate and having a zigzag pad arrangement. SOLUTION: The heights of connecting members between inner and outer pads of the narrow-pitch multi-pin flip chip having the zigzag pad arrangement and inner and outer pads of a sub-substrate are changed from each other. The mounting and wiring of the flip chip and the connection of a fine-pitch semiconductor chip are made possible by connecting the inner and outer pads of the flip chip to the pads of different layers of the sub-substrate, and making the wiring from each layer of the sub-substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

2. Description of the Related Art Conventionally, in a mounting structure in which a flip chip of a semiconductor device is mounted on a substrate, a structure of lands (pads) on the substrate and bumps of the flip chip, and a method of arranging these are designed to achieve high density. We are implementing it.

FIG. 9 shows a flip chip mounting method and a flip chip mounting structure described in Japanese Patent Application Laid-Open No. 11-251363, in which the structures of lands and bumps are devised. In the mounting structure described in the publication, the wiring board 23
In order to mount the semiconductor chip 22 face down, the bumps 26 made of a material softer than the lands 27 on the wiring board 23 are formed on the pads 25 on the lower surface of the semiconductor chip 22.
And the lands 27 are embedded in the bumps 26 so that the bumps 26 and the lands 27 are electrically connected. The semiconductor chip can be mounted at a fine pitch equivalent to the flip chip bump pitch.

As a method of high-density mounting by arranging lands (pads) and bumps, pads and lands arranged in a staggered lattice (staggered) form a narrow pitch, multi-pin flip chip mounted on a substrate. What is possible is being done.

[0004]

The above-described conventional land (pad) and bump mounting structure and the like for mounting and connecting and wiring a semiconductor chip on a substrate at a fine pitch equivalent to the pitch of flip chip bumps. There is a limit to high-density mounting and wiring by narrow pitch and multi-pin mounting only with the contrivance. Also, in connection of a narrow pitch, multi-pin flip chip with a staggered pad arrangement to a substrate, wiring from a substrate pad poses a problem in mounting a narrow pitch, multi-pin. This is because the wiring from the substrate pad inside the flip chip is difficult to wire outward on the surface layer due to the narrow pitch.

As described above, in the conventional flip chip mounting structure and wiring method, wiring may not be possible depending on the width of wiring, the width of space, the number of inner pads, and the like, which hinders high-density mounting. Met.

As a wiring method using a multilayer substrate, for example, a mounting structure of a ball grid array package type semiconductor component disclosed in Japanese Patent Application Laid-Open No. H10-256712 is known. In addition to providing surface pads on the multilayer printed wiring board, a circular via hole is provided for the lower layer wiring, and a pad from the lower layer wiring is formed on the surface by using a via hole pad having a concave vertical cross section, and cream is applied to all the pads. After solder is printed, a ball grid array package type semiconductor component having solder bumps of the same height formed thereon is mounted, and the solder bumps of the component and the cream solder are integrated and connected in a furnace. In such a mounting structure, the shape, structure, and forming method of the concave pad formed from the lower layer are difficult to manufacture. Are those with difficulty Te fit, further there are constraints on the diameter of the concave pad for generation of voids as described in the publication, devised concave pad is a problem in terms of such essential.

(Object) It is an object of the present invention to provide a flip-chip mounting structure and a wiring method capable of mounting and wiring a narrow pitch, multi-pin flip chip.

Another object of the present invention is to provide a flip-chip mounting structure and a wiring method which enable mounting and wiring of narrow-pitch, multi-pin flip chips with a staggered pad arrangement using a multilayer substrate.

[0009]

SUMMARY OF THE INVENTION A flip chip mounting structure and wiring method according to the present invention are directed to a method for mounting a flip chip of a narrow pitch, multi-pin semiconductor device with a staggered pad arrangement on a flip chip mounting sub-substrate (hereinafter, sub-substrate). In flip-chip mounting in which leads are not used on the back surface, a structure is used in which the height of a connecting material between pads inside and outside the flip chip and pads inside and outside the sub-substrate is changed. By connecting to the pads of different layers of the sub-substrate and performing wiring from each layer, mounting and wiring of a narrow pitch, multi-pin flip chip in a staggered pad arrangement and connection of a fine pitch semiconductor chip are enabled.

The flip-chip mounting structure of the present invention is a flip-chip mounting structure for mounting and wiring a flip chip (for example, FIG. 2B) face down on a multilayer wiring board (for example, FIG. 2A). A pad (for example, 8 in FIG. 2) provided on the surface of the uppermost layer (for example, 13 in FIG. 2) of the multilayer wiring board and on the surface of a lower layer (for example, 14 in FIG. 2) exposed by an opening in the upper layer; The flip chip and the multilayer wiring board are formed by bumps (for example, 9 in FIG. 2) made of an electrical connection material having a height corresponding to a position and a distance of the flip chip facing the pad of the multilayer wiring board. Are mounted and connected face down. The pads of the multilayer wiring board and the bumps of the flip chip are arranged in a staggered manner (for example, 7 and 8 in FIG. 1) on the periphery of the flip chip so as to face each other.
The pad inside the multilayer wiring board is provided on a lower layer surface.

The upper opening for exposing the lower surface of the multilayer wiring board is a single opening (for example, 3 in FIG. 2) including a plurality of inner pads arranged in a staggered manner. It is characterized by.

Further, the connection between the layers of the wiring connected to the pads is made through through holes (for example, 12 in FIG. 2).

The flip-chip wiring method of the present invention is a flip-chip wiring method for mounting and wiring a flip chip on a multilayer wiring board face-down, wherein the flip chip is exposed on the uppermost surface of the multilayer wiring board and through an opening in the upper layer. Pads are provided on the surface of the lower layer, and bumps made of an electrical connection material having a height corresponding to a position and a distance facing the pads of the multilayer wiring board are provided on a flip chip mounted on the multilayer wiring board. The flip chip is mounted and connected to the multilayer wiring board face down.

The pads of the multilayer wiring board and the bumps of the flip chip are arranged in a zigzag pattern facing each other around the periphery of the flip chip, and the pad inside the multilayer wiring board is provided on the lower layer surface. It is characterized by. The connection between the layers of the wiring connected to the pad is made through a through hole.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Description of Configuration) Next, an embodiment of a flip chip mounting structure and a wiring method according to the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a flip-chip mounting structure according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA 'of the flip-chip mounting structure shown in FIG. is there.

In this embodiment, the semiconductor device comprises a substrate a and a flip chip b of a semiconductor device mounted on the substrate a. The substrate a is, as shown in FIG. 2 has a multilayer structure composed of a substrate inner layer 14 formed on the substrate 2 and a substrate surface layer 13 having an opening for forming the cavity 3 above the substrate inner layer 14.

And, in the substrate inner layer 14 of the substrate a,
Having wiring on the upper surface of the inner layer and wiring from the wiring to the sub-substrate side that penetrates through the inner layer of the substrate 14 through the through hole
The substrate surface layer 13 has a wiring on the upper surface of the outer layer and a wiring from the wiring to the sub-substrate side through the substrate surface layer 13 and the substrate inner layer 14 through the through hole 12. Also,
The outer substrate pad 7 on the wiring is provided on the substrate surface layer 13.
However, an inner substrate pad 8 is formed on the wiring at a location opened by the cavity 3 in the substrate inner layer 14.

On the other hand, the flip chip b has outer chip pads 5 and inner chip pads 6 formed at positions corresponding to the outer board pads 7 and the inner board pads 8 of the board a, respectively. It is a semiconductor chip 1 on which connecting members 9 having different thicknesses are formed.
That is, the connecting material 9 of the pad corresponding to the outer substrate pad 7 is selected to have a small thickness, and the connecting material 9 of the pad corresponding to the inner substrate pad 8 is selected to have a large thickness.

In this embodiment, the flip chip b of the semiconductor device is mounted face down on the substrate a, and the chip pads 5 and 6 formed on the flip chip b and the substrate on the sub-substrate 2 are mounted. Flip chip mounting is performed by electrically connecting the substrate pads 7 and 8 formed on each layer with the connecting material 9. Also, the upper surface of the substrate a and the flip chip b
Is sealed with a resin 4 to protect the flip chip b and its connection.

In this embodiment, as described above, the connection between the flip chip b and the substrate a is made by the outer chip pad 5 being the outer substrate pad 7 and the inner chip pad 6 being the inner substrate pad 8 formed in the cavity 3. Are connected by connecting members 9. Here, the substrate a can be constituted by a multilayer substrate using a resin substrate or the like having a cavity structure for flip-chip mounting, and the sub-substrate 2 can also be a multilayer substrate.

Further, a thermosetting metal material, a solder material, or the like can be used for the connecting material 9. The thickness (height) of the connecting material between the outer pads and the connecting material between the inner pads is possible. Is changed to electrically connect the flip chip b and the sub-board 2. The method of wiring from the substrate pads 7 and 8 to the sub-substrate 2 side is as follows.
From the inner substrate pad 8 to the substrate inner layer 14.
Wiring. This enables connection between the layers via the through holes 12. (Other Embodiment 1) In the above embodiment, as can be seen from FIGS. 1 and 2, the wiring on the upper surface of the substrate inner layer 14 and the wiring to the sub-substrate 2 via the through hole are provided outside the flip chip. However, the interlayer wiring of the multi-layer substrate through the through hole according to the present invention can be performed from both the outside and the inside of the flip chip.

FIG. 3 is a plan view showing another embodiment of the present invention in which a through hole is formed below the flip chip and wiring is provided on the sub-substrate side. FIG.
FIG. 3 is a cross-sectional view showing a BB ′ plane of FIG.

Referring to FIG. 3 and FIG. 4, wirings from the inner substrate pad 8 to the inner layer 14 of the substrate are used in combination with the wiring 11 and the wiring 15 below the flip chip b. Furthermore, mounting of a multi-pin flip chip and wiring from pads are possible, and high-density mounting is possible. (Other Embodiment 2) FIG. 5 is a plan view showing another embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along the line CC 'of FIG.

Referring to FIGS. 5 and 6, in this embodiment, the openings provided in the outer layer 19 of the substrate are individually provided in a size corresponding to the connecting members 18 of the respective inner chip pads 16 of the flip chip. It has a structure provided as a single groove-shaped opening having a width corresponding to the connection material 18 of the plurality of inner chip pads 16.

The multilayer substrate of the present embodiment has an outer substrate layer 19 also below the flip chip, and furthermore, a method of embedding the inner layer 20 of the substrate in such a manner that the connecting material 18 of the chip pad 16 of the flip chip is embedded in the outer layer 19 of the substrate. Since it is fixed and electrically connected to the pad 7, the strength of the connection is increased,
It becomes easy to manufacture a sub-substrate composed of the substrate inner layer 20 and the substrate outer layer 19.

(Embodiment 3) In the above embodiments, an example was described in which the multilayer substrate was a two-layer substrate.
The present invention can be applied to a multilayer substrate having at least two wiring layers, and in this case, a higher-density mounting can be achieved.

FIG. 7 is a plan view showing such another embodiment, and FIG. 8 is a sectional view taken along the line DD 'of FIG.
The multilayer substrate side is configured in a three-layer structure, the flip-chip chip pads are configured in three rows, the first row is used for the uppermost layer wiring pads, the second row is used for the second layer wiring pads, and The wiring in the column has a configuration connected to the pads of the wiring in the lowermost layer. In the present embodiment, the wiring of the third layer is wired from the lower part of the flip chip toward the sub-substrate via a through hole.

In this embodiment, it goes without saying that the arrangement of through holes and the forms of openings for the uppermost layer and the intermediate layer shown in the second and third embodiments can be applied.

Further, in the above embodiments, the use of a ceramic substrate as the material of the substrate results in excellent heat dissipation, and the use of a flexible substrate makes it possible to cope with various mounting forms.

[0031]

According to the flip-chip mounting structure and the wiring method of the present invention, an opening is provided in an upper layer at a position corresponding to a pad in a lower layer of a multilayer substrate, and a bump using a connecting material having a different height is formed on the flip chip. By forming and connecting by face-down, it is possible to easily realize the connection between the inner chip pad of the flip chip and the pad on the upper surface of the lower substrate of the multilayer substrate. Connection with the wiring outside the chip becomes possible, and mounting and wiring of a narrow pitch, multi-pin flip chip with a staggered pad arrangement, which could not be performed conventionally, can be performed, so that high density mounting is possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a flip chip mounting structure and a wiring method according to the present invention.

FIG. 2 is a cross-sectional view of the flip-chip mounting structure shown in FIG.
It is sectional drawing of A 'side.

FIG. 3 is a diagram showing another embodiment of a flip chip mounting structure and a wiring method according to the present invention.

FIG. 4 is a cross-sectional view of the flip-chip mounting structure shown in FIG.
It is sectional drawing of B 'side.

FIG. 5 is a view showing still another embodiment of a flip chip mounting structure and a wiring method according to the present invention.

FIG. 6 is a cross-sectional view of the flip-chip mounting structure shown in FIG.
It is sectional drawing of C 'plane.

FIG. 7 is a diagram showing still another embodiment of a flip chip mounting structure and a wiring method according to the present invention.

FIG. 8 is a cross-sectional view of the flip-chip mounting structure shown in FIG.
It is sectional drawing of the D 'plane.

FIG. 9 is a diagram showing a conventional flip chip mounting structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Sub-substrate 3 Cavity 4, 24 Resin 5 Outer chip pad 6, 16 Inner chip pad 7 Outer board pad 8, 17 Inner board pad 9, 18 Connecting material 10, 11 Wiring 12 Through hole 13, 19 Substrate surface layer 14 , 20 substrate inner layer 22 semiconductor chip 23 wiring substrate 25 pad 27 land

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 21/92 602Q 23/12 N

Claims (7)

[Claims] 1. A flip chip mounting structure for mounting and wiring a flip chip face down on a multilayer wiring board, wherein the flip chip is provided on a surface of an uppermost layer of the multilayer wiring board and on a surface of a lower layer exposed through an opening in the upper layer. The flip chip and the multilayer wiring board are mounted face-down by a pad which is formed and a bump made of an electrical connection material having a height corresponding to a position and a distance of the flip chip facing the pad of the multilayer wiring board. And a flip-chip mounting structure. 2. The method according to claim 1, wherein the pads of the multilayer wiring board and the bumps of the flip chip are arranged in a staggered manner on the periphery of the flip chip so as to face each other, and the pad inside the multilayer wiring board is provided on a lower layer surface. The flip-chip mounting structure according to claim 1, wherein: 3. The multi-layer wiring board according to claim 2, wherein the upper layer opening for exposing a lower layer surface is a single opening including a plurality of inner pads arranged in a staggered manner. Flip chip mounting structure. 4. The method according to claim 1, wherein the connection between the layers of the wiring connected to the pad is made through a through hole.
Or the flip-chip mounting structure according to 3. 5. A flip-chip wiring method for mounting and wiring a flip chip face-down on a multilayer wiring board, wherein the flip-chip wiring method comprises: A pad is provided, and a flip chip mounted on the multilayer wiring board is provided with a bump made of an electrical connection material having a height corresponding to a position and a distance of the multilayer wiring board facing the pad, and the flip chip is mounted on the multilayer chip. A flip-chip wiring method, which is mounted and connected to a wiring board by face-down. 6. A pad of the multilayer wiring board and bumps of the flip chip are arranged in a zigzag pattern on the periphery of the flip chip so as to face each other, and a pad inside the multilayer wiring board is provided on a lower layer surface. 6. The method according to claim 5, wherein
The described flip-chip wiring method. 7. The flip-chip wiring method according to claim 6, wherein the connection between the layers of the wiring connected to the pad is made through a through hole.