JPH0897322A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0897322A JPH0897322A JP6227711A JP22771194A JPH0897322A JP H0897322 A JPH0897322 A JP H0897322A JP 6227711 A JP6227711 A JP 6227711A JP 22771194 A JP22771194 A JP 22771194A JP H0897322 A JPH0897322 A JP H0897322A
- Authority
- JP
- Japan
- Prior art keywords
- protruding
- circuit board
- electrode
- electrodes
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、種々の半導体パッケー
ジ形態の中でも、特にプリント基板の一方の面にＩＣチ
ップを搭載し、他方の面に突起電極を形成した、いわゆ
るＢＧＡ（ボール・グリッド・アレイ）パッケージに関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called BGA (ball grid, ball grid, etc.) in which, among various types of semiconductor packages, an IC chip is mounted on one surface of a printed circuit board and protruding electrodes are formed on the other surface. Array) package.
【０００２】[0002]
【従来の技術】この種の半導体パッケージとしては、セ
ラミック基板をベースにしたＣ（セラミック）−ＢＧＡ
パッケージや、プリント基板をベースにしたＰ（プラス
チック）−ＢＧＡパッケージが広く知られているが、最
近ではパッケージの低価格化のニーズに対応するためＰ
−ＢＧＡパッケージを採用する動きが高まっている。Ｐ
−ＢＧＡパッケージでは、図４に示すように、プリント
基板１の一方の面にＩＣチップ２が搭載され、他方の面
に複数の突起電極３が形成されている。またＩＣチップ
２は、ボンディングワイヤ４によって基板上のボンディ
ングパターン（不図示）に接続され、さらにモールド樹
脂５によってボンディングワイヤ４と一体に封止されて
いる。2. Description of the Related Art As a semiconductor package of this type, a C (ceramic) -BGA based on a ceramic substrate is used.
Although packages and P (plastic) -BGA packages based on printed circuit boards are widely known, recently, P (Plastic) -BGA packages have been developed to meet the needs for package price reduction.
-There is a growing trend to adopt BGA packages. P
In the BGA package, as shown in FIG. 4, the IC chip 2 is mounted on one surface of the printed board 1 and the plurality of protruding electrodes 3 are formed on the other surface. Further, the IC chip 2 is connected to a bonding pattern (not shown) on the substrate by a bonding wire 4, and is further sealed integrally with the bonding wire 4 by a molding resin 5.
【０００３】[0003]
【発明が解決しようとする課題】ところで、この種の半
導体パッケージにおいては、プリント基板１上に搭載し
たＩＣチップ２をボンディングワイヤ４とともにモール
ド樹脂５にて封止した際、モールド樹脂５の収縮によっ
てパッケージに反りが発生する。ところが従来の半導体
パッケージでは、複数の突起電極３がいずれも同じ大き
さで格子状に配列されていたため、パッケージの反りに
よってプリント基板１の外側と内側とで突起電極３の高
さにばらつきが生じる。このため、パッケージをマザー
基板に実装しようとした場合、プリント基板１の外側領
域では突起電極３とマザー基板との間に隙間が生じてし
まい、両者の間に安定した接合状態が得られなくなると
いう問題があった。By the way, in this type of semiconductor package, when the IC chip 2 mounted on the printed board 1 is sealed together with the bonding wires 4 by the molding resin 5, the molding resin 5 shrinks. The package warps. However, in the conventional semiconductor package, since the plurality of protruding electrodes 3 are all arranged in the same size in a grid pattern, the height of the protruding electrodes 3 on the outer side and the inner side of the printed circuit board 1 varies due to the warpage of the package. . Therefore, when the package is mounted on the mother board, a gap is generated between the protruding electrode 3 and the mother board in the outer region of the printed board 1, and a stable joint state cannot be obtained between the two. There was a problem.
【０００４】本発明は、上記問題を解決するためになさ
れたもので、その目的は、パッケージの反りに伴う突起
電極の高さのばらつきを解消することができる半導体パ
ッケージを提供することにある。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor package which can eliminate the variation in height of the protruding electrodes due to the warp of the package.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、プリント基板の一方の面
にＩＣチップが搭載され、他方の面に所定の配列で複数
の突起電極が形成された半導体パッケージにおいて、複
数の突起電極のうち、プリント基板の外側に配置された
突起電極がそれよりも内側に配置された突起電極よりも
大きく形成された構成となっている。The present invention has been made in order to achieve the above-mentioned object, and an IC chip is mounted on one surface of a printed board, and a plurality of protruding electrodes are arranged on the other surface in a predetermined arrangement. In the semiconductor package in which is formed, among the plurality of protruding electrodes, the protruding electrodes arranged outside the printed board are formed larger than the protruding electrodes arranged inside thereof.
【０００６】[0006]
【作用】本発明の半導体パッケージにおいては、プリン
ト基板の外側に配置された突起電極をそれよりも内側に
配置された突起電極よりも大きく形成することで、プリ
ント基板上のＩＣチップをモールド樹脂にて封止した際
のパッケージの反りによって突起電極の高さのばらつき
が矯正されるようになる。In the semiconductor package of the present invention, the IC chip on the printed circuit board is molded with the molding resin by forming the protruding electrode arranged outside the printed circuit board larger than the protruding electrode arranged inside thereof. Due to the warp of the package when the package is sealed, the height variation of the protruding electrode is corrected.
【０００７】[0007]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明に係わる半導体パ
ッケージの第１実施例を説明する図であり、これはＩＣ
チップを搭載する前の状態を示している。図１に示すよ
うに本実施例の半導体パッケージにおいては、プリント
基板１の底面に複数の突起電極３ａ，３ｂ，３ｃが形成
されており、これらの突起電極３ａ，３ｂ，３ｃは例え
ば図示のごとく３列で環状に配置されている。本実施例
では、複数の突起電極３ａ，３ｂ，３ｃのうち、プリン
ト基板１の外側に配置された突起電極、例えば最外郭に
配置された突起電極３ａがそれよりも内側に配置された
突起電極３ｂよりも大きく形成され、さらにその突起電
極３ｂがそれよりも内側、つまり図例では最内に配置さ
れた突起電極３ｃよりも大きく形成されている。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram for explaining a first embodiment of a semiconductor package according to the present invention, which is an IC
The state before mounting a chip is shown. As shown in FIG. 1, in the semiconductor package of this embodiment, a plurality of protruding electrodes 3a, 3b, 3c are formed on the bottom surface of the printed circuit board 1, and these protruding electrodes 3a, 3b, 3c are, for example, as shown in the figure. They are annularly arranged in three rows. In the present embodiment, among the plurality of protruding electrodes 3a, 3b, 3c, the protruding electrode arranged outside the printed circuit board 1, for example, the protruding electrode 3a arranged at the outermost portion is arranged inside the protruding electrode 3a. The protrusion electrode 3b is formed to be larger than the protrusion electrode 3b, and the protrusion electrode 3b is formed to be larger than the protrusion electrode 3c arranged inside thereof, that is, the innermost protrusion electrode 3c in the illustrated example.
【０００８】ここで、上述のごとくプリント基板１に大
きさの異なる突起電極３ａ，３ｂ，３ｃを形成する具体
的な手段としては、例えば以下に述べる（１）〜（３）
のような方法が考えられる。 （１）プリント基板１の電極パターンに応じて形成され
たランドにはんだペーストを供給し、これをリフローに
より加熱溶融して突起電極３ａ，３ｂ，３ｃを形成する
際に、各ランドに対するはんだペーストの供給量を変え
る。 （２）スタッドバンプと呼ばれるボールボンド方式にて
突起電極３ａ，３ｂ，３ｃを形成する際に、ワイヤ先端
に形成するボール径を変える。 （３）プリント基板１のランド上にフラックス等を介し
て粒状のはんだボールや銅ボールを供給して突起電極３
ａ，３ｂ，３ｃを形成する際に、各ランドに対して供給
するボール径を変える。Here, as a specific means for forming the protruding electrodes 3a, 3b, 3c of different sizes on the printed board 1 as described above, for example, the following (1) to (3) will be described.
The following method is possible. (1) When the solder paste is supplied to the land formed according to the electrode pattern of the printed board 1 and heated and melted by reflow to form the protruding electrodes 3a, 3b, 3c, the solder paste for each land is Change the supply. (2) When forming the protruding electrodes 3a, 3b, 3c by a ball bonding method called stud bump, the diameter of the ball formed at the tip of the wire is changed. (3) The bump electrodes 3 are provided by supplying granular solder balls or copper balls onto the lands of the printed circuit board 1 through flux or the like.
When forming a, 3b, and 3c, the diameter of the ball supplied to each land is changed.
【０００９】また、各々の突起電極３ａ，３ｂ，３ｃの
大きさを設定するにあたっては、プリント基板１上に搭
載したＩＣチップ（不図示）を樹脂封止する際のパッケ
ージの反り量を見込んで適宜設定することが肝要であ
る。ちなみに本実施例においては、最外郭に配置された
突起電極３ａがφ０．４ｍｍ、その内側に配置された突
起電極３ｂがφ０．３ｍｍ、そして最も内側に配置され
た突起電極３ｃがφ０．２ｍｍの大きさをもって形成さ
れている。When setting the size of each of the protruding electrodes 3a, 3b, 3c, the amount of warpage of the package when the IC chip (not shown) mounted on the printed circuit board 1 is resin-sealed is taken into consideration. It is important to set it appropriately. Incidentally, in this embodiment, the outermost protruding electrode 3a has a diameter of 0.4 mm, the inner protruding electrode 3b has a diameter of 0.3 mm, and the innermost protruding electrode 3c has a diameter of 0.2 mm. It is formed with a size.
【００１０】上記構成からなる本実施例の半導体パッケ
ージにおいては、プリント基板１の底面に形成された複
数の突起電極３ａ，３ｂ，３ｃの大きさが異なるため、
樹脂封止前の状態では図２（ａ）に示すように、各々の
突起電極３ａ，３ｂ，３ｃの高さにばらつきが生じるこ
とになる。しかしながら、図２（ｂ）に示すように、プ
リント基板１上にＩＣチップ２を搭載し、これをボンデ
ィングワイヤ４にてボンディングパターン（不図示）に
接続したのち、ＩＣチップ２とボンディングワイヤ４と
をモールド樹脂５にて封止した際には、モールド樹脂５
の収縮によってパッケージに反りが生じ、これによって
樹脂封止前の突起電極３ａ，３ｂ，３ｃの高さのばらつ
きが矯正される。したがって、樹脂封止の際のパッケー
ジの反り量を見込んで予め各突起電極３ａ，３ｂ，３ｃ
の大きさを適宜設定することにより、基準平面Ｆに対し
て各々の突起電極３ａ，３ｂ，３ｃの高さを均一にする
ことができる。In the semiconductor package of this embodiment having the above structure, the plurality of protruding electrodes 3a, 3b, 3c formed on the bottom surface of the printed circuit board 1 have different sizes.
In the state before resin sealing, as shown in FIG. 2A, the heights of the respective protruding electrodes 3a, 3b, 3c vary. However, as shown in FIG. 2B, after mounting the IC chip 2 on the printed board 1 and connecting it to a bonding pattern (not shown) with the bonding wire 4, the IC chip 2 and the bonding wire 4 are connected. When the resin is sealed with the mold resin 5, the mold resin 5
Warpage occurs in the package due to the contraction of, and thereby the variation in height of the protruding electrodes 3a, 3b, 3c before resin sealing is corrected. Therefore, in consideration of the warp amount of the package at the time of resin sealing, the protruding electrodes 3a, 3b, 3c are preliminarily prepared.
The height of each of the protruding electrodes 3a, 3b, 3c with respect to the reference plane F can be made uniform by appropriately setting the size of.
【００１１】ところで、プリント基板１の外側、例えば
最外郭に配置された突起電極３ａはそれよりも内側に配
置された突起電極３ｂよりも大きくなり、さらにその突
起電極３ｂはそれよりも内側に配置された突起電極３ｃ
よりも大きくなる（３ａ＞３ｂ＞３ｃ）。したがって、
プリント基板１上に異なる大きさの突起電極３ａ，３
ｂ，３ｃを形成した場合は、その外径が大きくなるほど
突起電極３ａ，３ｂ，３ｃ間の隙間が小さくなる。By the way, the protruding electrode 3a arranged on the outer side of the printed circuit board 1, for example, the outermost portion is larger than the protruding electrode 3b arranged inside thereof, and the protruding electrode 3b is arranged inside thereof. Protruding electrode 3c
(3a>3b> 3c). Therefore,
The protruding electrodes 3a, 3 of different sizes are formed on the printed circuit board 1.
When b and 3c are formed, the gap between the protruding electrodes 3a, 3b and 3c becomes smaller as the outer diameter increases.
【００１２】このため、特に、突起電極３ａ，３ｂ，３
ｃ間の隙間Ｇａ，Ｇｂ，Ｇｃが最も小さいプリント基板
１の外側領域では、突起電極３ａ，３ｂ，３ｃを介して
パッケージをマザー基板に接合する際の突起電極のコラ
プス（つぶれ）によって突起電極同士の接触が起こる。
その結果、電気的ショートが起こり、接合不良となる虞
れがある。その対策としては、最外郭に配置された突起
電極３ａに合わせて突起電極３ａ，３ｂ，３ｃ間の配列
ピッチを十分に広く確保することも考えられるが、そう
した場合はプリント基板１の内側領域での突起電極３
ｂ，３ｃの配置状態が疎らになり、同じ電極数を得るに
もパッケージ全体が大型化してしまう。そこで、パッケ
ージ実装時の電気的ショートを回避しつつ、高密度な電
極形成を可能にすることを目的として、以下に本発明の
第２実施例を説明する。Therefore, in particular, the protruding electrodes 3a, 3b, 3
In the outer region of the printed circuit board 1 where the gaps Ga, Gb, Gc between c are the smallest, the protrusion electrodes are collided with each other by the collapse of the protrusion electrodes when the package is bonded to the mother substrate via the protrusion electrodes 3a, 3b, 3c. Contact occurs.
As a result, an electrical short circuit may occur, resulting in a defective joint. As a countermeasure against this, it is conceivable to secure a sufficiently wide array pitch between the protruding electrodes 3a, 3b, 3c in accordance with the protruding electrode 3a arranged at the outermost portion, but in such a case, in the inner region of the printed board 1, Protruding electrode 3
The arrangement state of b and 3c becomes sparse, and the entire package becomes large even if the same number of electrodes is obtained. Therefore, a second embodiment of the present invention will be described below for the purpose of enabling high-density electrode formation while avoiding an electrical short circuit during package mounting.
【００１３】図３は本発明に係わる半導体パッケージの
第２実施例を説明する図である。本第２実施例において
は、その特徴部分の一つとして、プリント基板１上に形
成された複数の突起電極３ａ，３ｂ，３ｃのうち、プリ
ント基板１の外側、例えば最外郭に配置された突起電極
３ａ間の配列ピッチＰａがそれよりも内側に配置された
突起電極３ｂ間の配列ピッチＰｂよりも広く形成され、
さらにその突起電極３ｂ間の配列ピッチＰｂがそれより
も内側、つまり最内に配置された突起電極３ｃ間の配列
ピッチＰｃよりも広く形成されている（Ｐａ＞Ｐｂ＞Ｐ
ｃ）。FIG. 3 is a diagram for explaining a second embodiment of the semiconductor package according to the present invention. In the second embodiment, as one of the characteristic portions, among the plurality of protrusion electrodes 3a, 3b, 3c formed on the printed board 1, the protrusions arranged on the outer side of the printed board 1, for example, the outermost portion. The arrangement pitch Pa between the electrodes 3a is formed wider than the arrangement pitch Pb between the protruding electrodes 3b arranged inside thereof.
Further, the arrangement pitch Pb between the protruding electrodes 3b is formed to be wider than that, that is, wider than the arrangement pitch Pc between the protruding electrodes 3c arranged in the innermost portion (Pa>Pb> P).
c).
【００１４】これにより、上記第１実施例のごとくプリ
ント基板１上に大きさの異なる突起電極３ａ，３ｂ，３
ｃを形成する場合であっても、プリント基板１の外側、
例えば最外郭に配置された突起電極３ａ間の隙間Ｇａと
それよりも内側に配置された突起電極３ｂ間の隙間Ｇ
ｂ、さらには最内に配置された突起電極３ｃ間の隙間Ｇ
ｃを異なる寸法、つまり外郭にいくほど広く設定するこ
とができるため（Ｇａ＞Ｇｂ＞Ｇｃ）、パッケージ実装
時の電気的ショートを回避しつつ、プリント基板１に対
して高密度に突起電極３ａ，３ｂ，３ｃを形成すること
が可能となる。As a result, the protruding electrodes 3a, 3b, 3 having different sizes are formed on the printed board 1 as in the first embodiment.
Even when forming c, the outside of the printed circuit board 1,
For example, a gap Ga between the protruding electrodes 3a arranged at the outermost portion and a gap G between the protruding electrodes 3b arranged inside the gap Ga.
b, and the gap G between the protruding electrodes 3c arranged in the innermost part
Since c can be set to different dimensions, that is, the wider it is to the outer edge (Ga>Gb> Gc), the protruding electrodes 3a can be densely formed on the printed circuit board 1 while avoiding an electrical short circuit during package mounting. It is possible to form 3b and 3c.
【００１５】また、上記以外の特徴部分として、プリン
ト基板１に環状に配列された第１の突起電極列、例えば
最外郭に配列された突起電極３ａ列とそれよりも内側に
配列された第２の突起電極３ｂ列との列間隔Ｐｄが、そ
の第２の突起電極３ｂ列とそれよりも内側、つまり最内
に配列された第３の突起電極３ｃ列との列間隔Ｐｅより
も広く形成されている（Ｐｄ＞Ｐｅ）。Further, as a characteristic portion other than the above, a first protruding electrode row arranged in a ring on the printed board 1, for example, an outermost protruding electrode row 3a and a second row arranged inside thereof. Of the second protruding electrode 3b is formed to be wider than the column interval Pe between the second protruding electrode 3b and the third protruding electrode 3c arranged inside, that is, the innermost third protruding electrode 3c. (Pd> Pe).
【００１６】これにより、上記第１実施例のごとくプリ
ント基板１上に大きさの異なる突起電極３ａ，３ｂ，３
ｃを形成する場合であっても、プリント基板１に環状に
配列された第１の突起電極３ａ列とそれよりも内側に配
列された第２の突起電極３ｂ列との隙間Ｇｄと、その第
２の突起電極３ｂ列とそれよりも内側に配列された第３
の突起電極３ｃ列との隙間Ｇｅとを異なる寸法に設定す
ることができるため（Ｇｄ＞Ｇｅ）、パッケージ実装時
の電気的ショートを回避しつつ、より一層高密度に突起
電極３ａ，３ｂ，３ｃを形成することが可能となる。As a result, the protruding electrodes 3a, 3b, 3 having different sizes are formed on the printed circuit board 1 as in the first embodiment.
Even in the case of forming c, the gap Gd between the first protruding electrode 3a array arranged in an annular shape on the printed circuit board 1 and the second protruding electrode 3b array arranged inside thereof is 2 row of protruding electrodes 3b and the third arrayed inside
Since the gap Ge with the row of the protruding electrodes 3c can be set to different dimensions (Gd> Ge), the protruding electrodes 3a, 3b, 3c can be denser while avoiding an electrical short circuit during package mounting. Can be formed.
【００１７】なお、上記第１及び第２実施例において
は、プリント基板１上にいずれも３列で突起電極３ａ，
３ｂ，３ｃが形成された場合を挙げて説明したが、本発
明はこれに限定されることなく、例えばプリント基板１
上にフルマトリクス形態で複数の突起電極が形成された
半導体パッケージなどに対しても適用できることは言う
までもない。In the first and second embodiments, the projection electrodes 3a, 3a are arranged in three rows on the printed circuit board 1.
Although the case where 3b and 3c are formed has been described as an example, the present invention is not limited to this.
It goes without saying that the present invention can also be applied to a semiconductor package or the like on which a plurality of protruding electrodes are formed in a full matrix form.
【００１８】[0018]
【発明の効果】以上、説明したように本発明によれば、
プリント基板の外側に配置された突起電極をそれよりも
内側に配置された突起電極よりも大きく形成すること
で、プリント基板上のＩＣチップをモールド樹脂にて封
止する際のパッケージの反りにより電極高さのばらつき
が矯正されるようになる。このため、モールド樹脂の収
縮に伴うパッケージの反り量を見込んで、各突起電極の
大きさを適宜設定することにより、パッケージ実装時に
は各々の突起電極の高さを均一にすることが可能とな
る。その結果、パッケージをマザー基板等に実装する際
には、マザー基板に対して全ての突起電極を均一に密着
させることができるため、パッケージとマザー基板との
間に安定した接合状態を得ることが可能となる。As described above, according to the present invention,
By forming the protruding electrodes arranged on the outer side of the printed circuit board larger than the protruding electrodes arranged on the inner side thereof, the electrodes are caused by the warp of the package when the IC chip on the printed circuit board is sealed with the mold resin. Height variations will be corrected. Therefore, the height of each protruding electrode can be made uniform at the time of mounting the package by appropriately setting the size of each protruding electrode in consideration of the amount of warpage of the package due to the shrinkage of the mold resin. As a result, when mounting the package on the mother board or the like, all the protruding electrodes can be evenly adhered to the mother board, so that a stable bonding state can be obtained between the package and the mother board. It will be possible.
【図１】本発明に係わる半導体パッケージの第１実施例
を説明する図である。FIG. 1 is a diagram illustrating a first embodiment of a semiconductor package according to the present invention.
【図２】パッケージの反りによる電極高さの変化を示す
図である。FIG. 2 is a diagram showing changes in electrode height due to warpage of a package.
【図３】本発明に係わる半導体パッケージの第２実施例
を説明する図である。FIG. 3 is a diagram illustrating a second embodiment of a semiconductor package according to the present invention.
【図４】従来の半導体パッケージを説明する図である。FIG. 4 is a diagram illustrating a conventional semiconductor package.
１ プリント基板 ２ ＩＣチップ ３ａ，３ｂ，３ｃ 突起電極 1 Printed Circuit Board 2 IC Chips 3a, 3b, 3c Projection Electrodes
Claims (3)
搭載され、他方の面に所定の配列で複数の突起電極が形
成された半導体パッケージにおいて、 前記複数の突起電極のうち、前記プリント基板の外側に
配置された突起電極がそれよりも内側に配置された突起
電極よりも大きく形成されていることを特徴とする半導
体パッケージ。1. A semiconductor package in which an IC chip is mounted on one surface of a printed circuit board and a plurality of protruding electrodes are formed on the other surface in a predetermined arrangement, wherein among the plurality of protruding electrodes, a printed circuit board of the printed circuit board is provided. A semiconductor package, wherein the protruding electrode arranged on the outside is formed larger than the protruding electrode arranged on the inside.
起電極間の配列ピッチがそれよりも内側に配置された突
起電極間の配列ピッチよりも広く形成されていることを
特徴とする請求項１記載の半導体パッケージ。2. The arrangement pitch between the protruding electrodes arranged outside the printed circuit board is wider than the arrangement pitch between the protruding electrodes arranged inside thereof. The semiconductor package described.
１の突起電極列とそれよりも内側に配列された第２の突
起電極列との列間隔が、前記第２の電極突起列とそれよ
りも内側に配列された第３の突起電極列との列間隔より
も広く形成されていることを特徴とする請求項１又は２
記載の半導体パッケージ。3. A row interval between a first protruding electrode row arranged in a ring on the printed circuit board and a second protruding electrode row arranged inside thereof is the second electrode protruding row and the second electrode protruding row. 3. It is formed to be wider than the row interval with the third protruding electrode row arranged on the inside.
The semiconductor package described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6227711A JPH0897322A (en) | 1994-09-22 | 1994-09-22 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6227711A JPH0897322A (en) | 1994-09-22 | 1994-09-22 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0897322A true JPH0897322A (en) | 1996-04-12 |
Family
ID=16865158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6227711A Pending JPH0897322A (en) | 1994-09-22 | 1994-09-22 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0897322A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
| JPH098081A (en) * | 1995-06-20 | 1997-01-10 | Fujitsu General Ltd | Mounting structure of bga package |
| EP0814511A3 (en) * | 1996-06-19 | 1998-11-18 | International Business Machines Corporation | Plastic ball grid array module |
| JPH1174312A (en) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device and method for forming solder bump |
| JPH11150207A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Microelectronics Corp | Semiconductor device and manufacture thereof |
| US6674163B1 (en) | 1998-08-18 | 2004-01-06 | Oki Electric Industry Co., Ltd. | Package structure for a semiconductor device |
| US7123480B1 (en) | 1998-08-18 | 2006-10-17 | Oki Electric Industry Co., Ltd. | Package structure for a semiconductor device |
| JP2009099830A (en) * | 2007-10-18 | 2009-05-07 | Sony Chemical & Information Device Corp | Wiring board, and method of mounting ic chip |
-
1994
- 1994-09-22 JP JP6227711A patent/JPH0897322A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
| JPH098081A (en) * | 1995-06-20 | 1997-01-10 | Fujitsu General Ltd | Mounting structure of bga package |
| EP0814511A3 (en) * | 1996-06-19 | 1998-11-18 | International Business Machines Corporation | Plastic ball grid array module |
| JPH1174312A (en) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | Semiconductor device and method for forming solder bump |
| JPH11150207A (en) * | 1997-11-17 | 1999-06-02 | Toshiba Microelectronics Corp | Semiconductor device and manufacture thereof |
| US6674163B1 (en) | 1998-08-18 | 2004-01-06 | Oki Electric Industry Co., Ltd. | Package structure for a semiconductor device |
| US7123480B1 (en) | 1998-08-18 | 2006-10-17 | Oki Electric Industry Co., Ltd. | Package structure for a semiconductor device |
| US7514768B2 (en) | 1998-08-18 | 2009-04-07 | Oki Electric Industry Co., Ltd. | Package structure for a semiconductor device incorporating enhanced solder bump structure |
| JP2009099830A (en) * | 2007-10-18 | 2009-05-07 | Sony Chemical & Information Device Corp | Wiring board, and method of mounting ic chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6649448B2 (en) | Method of manufacturing a semiconductor device having flexible wiring substrate | |
| US6521997B1 (en) | Chip carrier for accommodating passive component | |
| US6736306B2 (en) | Semiconductor chip package comprising enhanced pads | |
| JP3291368B2 (en) | Structure of ball grid array type semiconductor package | |
| US20080096314A1 (en) | Ball grid array package and method thereof | |
| JPH0897322A (en) | Semiconductor package | |
| JP3171297B2 (en) | Package mounting method | |
| JP2007266564A (en) | Flip chip bonded package | |
| JP2000124259A (en) | Ic chip, semiconductor device, and manufacture of the semiconductor device | |
| JPH08125062A (en) | Semiconductor device and its manufacture | |
| US7691745B1 (en) | Land patterns for a semiconductor stacking structure and method therefor | |
| JP2768315B2 (en) | Semiconductor device | |
| JPH1074887A (en) | Electronic part and its manufacture | |
| JPH1022341A (en) | Mounting method for bga package and mounted structure | |
| JP2907195B2 (en) | Method for manufacturing semiconductor device | |
| JP4677152B2 (en) | Semiconductor device | |
| JPH08162560A (en) | Electronic part | |
| JP2002026239A (en) | Semiconductor device and its manufacturing method | |
| JPH09298217A (en) | Semiconductor device, its manufacture and electronic device | |
| JP2001094244A (en) | Mounting method for package | |
| JP2642074B2 (en) | Ball grid array type semiconductor device and method of manufacturing the same | |
| JPH1092965A (en) | Surface mount semiconductor package | |
| JPH11186454A (en) | Bga type integrated circuit parts, manufacture of the parts and method for mounting the parts | |
| JP2003218290A (en) | Resin-sealing semiconductor device | |
| JP2001176911A (en) | Manufacturing method of semiconductor device |