JP2003218290A - Resin-sealing semiconductor device - Google Patents

Resin-sealing semiconductor device

Info

Publication number
JP2003218290A
JP2003218290A JP2003037906A JP2003037906A JP2003218290A JP 2003218290 A JP2003218290 A JP 2003218290A JP 2003037906 A JP2003037906 A JP 2003037906A JP 2003037906 A JP2003037906 A JP 2003037906A JP 2003218290 A JP2003218290 A JP 2003218290A
Authority
JP
Japan
Prior art keywords
resin
substrate
semiconductor device
semiconductor element
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003037906A
Other languages
Japanese (ja)
Inventor
Hitoshi Ito
仁 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2003037906A priority Critical patent/JP2003218290A/en
Publication of JP2003218290A publication Critical patent/JP2003218290A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resin-sealing semiconductor device capable of reducing warping. <P>SOLUTION: This resin-sealing semiconductor device 1 is provided with a semiconductor element 10 mounted on one face side of a substrate 2, a metallic thin wire 11 connecting the semiconductor element 10 to a wiring pattern provided at one face side of the substrate 2, a resin sealing part 3 for sealing the semiconductor element 10 and the metallic thin wire 11 at one face side of the substrate 2, and an electrode 4 formed at the other face side of the substrate 2 so as to be conducted to the wiring pattern. As for the thickness of the resin sealing part 3 from one face side of the substrate 2, the part where the semiconductor element 10 is sealed is made thinner than the part where the metallic thin wire 11 is sealed, and the part where the metallic thin wire is sealed is divided by the parts to which the metallic thin wire is not connected. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【０００１】 【発明の属する技術分野】本発明は、基板の一方面側に
実装した半導体素子を樹脂にて封止して成る樹脂封止型
半導体装置に関する。 【０００２】 【従来の技術】近年、半導体素子の高集積化にともな
い、半導体素子と外部回路との電気的な接続を行うリー
ド等の電極部の高密度化が進んでいる。ＰＧＡ（ピング
リッドアレイ）やＢＧＡ（ボールグリッドアレイ）等か
ら成る半導体装置は、電極部の高密度化を図るため基板
の片面側においてエリア状に多数の電極部を配列したも
のである。 【０００３】図３は従来のＢＧＡから成る樹脂封止型半
導体装置１を説明する図であり、（ａ）は斜視図、
（ｂ）は部分拡大断面図、（ｃ）は反り状態を示してい
る。図３（ａ）に示すように、樹脂封止型半導体装置１
は例えばＢＴ樹脂やポリイミド系から成る基板２と、基
板２の一方面側に実装される半導体素子１０と、半導体
素子１０を封止するための樹脂封止部３と、基板２の他
方面側に配列されるはんだバンプ等から成る電極部４と
から構成されている。 【０００４】図３（ｂ）に示すように、基板２上に実装
された半導体素子１０は、ボンディングワイヤー等の金
属細線１１によって基板２上に設けられた配線パターン
（図示せず）と接続されており、この金属細線１１とと
もにエポキシ系等から成る樹脂封止部３にて封止されて
いる。この金属細線１１は基板２上の配線パターン（図
示せず）を介して図３（ａ）に示す電極部４と導通して
おり、この電極部４を外部回路（図示せず）へ接続する
ことによって半導体素子１０と外部回路（図示せず）と
の信号入出力が行われることになる。 【０００５】 【発明が解決しようとする課題】しかしながらこのよう
な樹脂封止型半導体装置には次のような問題がある。す
なわち、樹脂封止型半導体装置における樹脂封止部を形
成する場合、基板の一方面側に実装された半導体素子を
金型のキャビティ内に配置しておき、軟化した樹脂をこ
のキャビティ内に充填することによって半導体素子を樹
脂にて覆うようにする。その後、この樹脂を硬化させる
ことによって基板の一方面側に樹脂封止部を形成する。
ところが、この硬化の際における樹脂の収縮により完成
後の樹脂封止型半導体装置に反りが生じてしまう。 【０００６】つまり、図３（ｃ）に示すように、樹脂封
止部３は基板２の片面側のみに設けられており、硬化の
際における樹脂と基板２との収縮量の違いから硬化後の
樹脂封止型半導体装置１には凹状の反りが生じることに
なる。このような反りが生じると、樹脂封止型半導体装
置１と他の基板との実装不良すなわち電極部４と他の基
板上の電極パターンとの接触不良を起こすことになる。
また、反りによって樹脂封止部３内の半導体素子に応力
が加わり、特性不良を発生させる原因となる。 【０００７】 【課題を解決するための手段】本発明は、このような課
題を解決するために成された樹脂封止型半導体装置であ
る。すなわち、本発明の樹脂封止型半導体装置は、基板
の一方面側に実装された半導体素子と、半導体素子と基
板の一方面側に設けられた配線パターンとを接続する金
属細線と、基板の一方面側において半導体素子および金
属細線を封止する樹脂封止部と、基板の他方面側に設け
られ配線パターンと導通する電極部とを備えたものであ
り、樹脂封止部の基板の一方面からの厚さとして、金属
細線を封止する部分に比べて半導体素子を封止する部分
の方を薄くするとともに、金属細線を封止する部分を金
属細線の接続されていない部分で分割して設けるように
している。 【０００８】本発明では、基板の一方面側に実装された
半導体素子を金属細線にて配線し、これらを樹脂封止部
にて封止して成る樹脂封止型半導体装置において、半導
体素子を封止する樹脂封止部の基板の一方面からの厚さ
が金属細線を封止する樹脂封止部の基板の一方面からの
厚さよりも薄くなっている。このため、金属細線を封止
する厚さと同じ厚さで半導体素子を封止する場合と比べ
て樹脂封止部を構成する樹脂量を少なくすることがで
き、樹脂硬化の際の収縮量を少なくすることができるよ
うになる。また、金属細線を封止する部分が金属細線の
接続されていない部分で分割されていることで、樹脂封
止部を構成する樹脂の量を少なくできるとともに、樹脂
硬化時における収縮量を少なくできるようになる。 【０００９】 【発明の実施の形態】以下に、本発明の樹脂封止型半導
体装置の実施例を図に基づいて説明する。図１は本発明
の樹脂封止型半導体装置を説明する図で、（ａ）は斜視
図、（ｂ）は部分拡大断面図である。図１（ａ）に示す
ように、本実施例における樹脂封止型半導体装置１は、
ＢＴ樹脂やポリイミド系のプリント配線板等から成る基
板２と、この基板２の一方面側に実装される半導体素子
１０と、半導体素子１０と基板２の一方面側に形成され
た配線パターン（図示せず）とを接続する金属細線１１
（図１（ｂ）参照）と、基板２の一方面側において半導
体素子１０および金属細線１１を封止する樹脂封止部３
と、基板２の他方面側に設けられ配線パターン（図示せ
ず）と導通する電極部４とから構成されている。 【００１０】電極部４がはんだバンプから成り基板２の
他方面側にエリア状に複数個配列されている場合には、
本実施例における樹脂封止型半導体装置１はＢＧＡ（ボ
ールグリッドアレイ）と呼ばれる。また、図示しないが
電極部３が金属ピンから成り基板２の他方面側にエリア
状複数本配列されている場合にはＰＧＡ（ピングリッド
アレイ）と呼ばれる。 【００１１】以下においては、ＢＧＡから成る樹脂封止
型半導体装置１を例として説明を行う。本実施例におけ
る樹脂封止型半導体装置１においては、基板２の一方面
側に設けられた樹脂封止部３の基板２の一方面からの厚
さが、半導体素子１０を封止する部分と金属細線１１を
封止する部分とで異なっている。 【００１２】すなわち、図１（ｂ）に示すように、基板
２の一方面側に実装された半導体素子１０は、同じく基
板２の一方面側に形成されている配線パターン（図示せ
ず）と金属細線１１によって接続されている。金属細線
１１は例えば金線を用いたボンディングワイヤーから成
るものであり、半導体素子１０の上面から上方にループ
を描いて接続されている。本実施例における樹脂封止型
半導体装置１においては、このような半導体素子１０お
よび金属細線１１を封止する樹脂封止部３の厚さを、金
属細線１１を封止する部分３ｂに比べ半導体素子１０を
封止する部分３ａの方を薄くしている。 【００１３】つまり、基板２の一方面からの最上部の高
さが金属細線１１と半導体素子１０とで異なるような場
合において、樹脂封止部３の基板２の一方面からの厚さ
を金属細線１１の高さに合わせて一律にするのではな
く、金属細線１１および半導体素子１０のそれぞれの最
上部の高さに応じた必要量（封止効果を損なわない程度
の量）の厚さに設定している。これによって、従来の樹
脂封止型半導体装置（図３参照）と比べて樹脂封止部３
を構成する樹脂の量を減らすことができるようになる。
すなわち、樹脂の量を減らすことができるということ
は、樹脂封止部３を形成する場合において、材料となる
樹脂の硬化の際の収縮量を少なくできることになる。 【００１４】本実施例における樹脂封止型半導体装置１
を製造する場合には、先ず、基板２の一方面側にチップ
状の半導体素子１０を実装し、半導体素子１０と基板２
の配線パターン（図示せず）とを金属細線１１にて接続
する。その後、半導体素子１０の実装および金属細線１
１による配線が終了した基板２を金型にセットし、半導
体素子１０および金属細線１１を封止するための樹脂を
金型のキャビティ内に充填する。 【００１５】この際、樹脂を所定の温度に加熱して溶融
させた状態でキャビティ内に流し込む。金型のキャビテ
ィ形状としては、半導体素子１０を封止する部分３ａよ
りも金属細線３ｂを封止する部分３ｂの方を高く設けて
おき、図１（ａ）に示すような厚さの異なる樹脂封止部
３の形状となるように設定しておく。このような金型の
キャビティ内に溶融した樹脂を充填した後に、樹脂を硬
化させることによって基板２の一方面側に樹脂封止部３
を形成する。 【００１６】先に説明したように、本実施例における樹
脂封止型半導体装置１においては、樹脂封止部３を構成
する樹脂の量を従来の樹脂封止型半導体装置（図３参
照）と比べて少なくすることができるため、溶融した樹
脂を硬化させる際の収縮量を少なくすることができ、完
成後の樹脂封止型半導体装置１の反り発生を抑制するこ
とができるようになる。しかも、完成後の樹脂封止型半
導体装置１に対して熱を加えてはんだ付け等を行い実装
用基板（図示せず）上に接続する場合において、その熱
による反りの発生をも抑制できるようになる。 【００１７】次に、本発明の樹脂封止型半導体装置１に
おける他の例を説明する。図２は本発明における樹脂封
止型半導体装置１の他の例を説明する斜視図で、（ａ）
はその１、（ｂ）はその２である。すなわち、図２
（ａ）に示す例では、樹脂封止部３における金属細線１
１（図１（ｂ）参照）を封止する部分３ｂが連続して設
けられている樹脂封止型半導体装置１を示している。こ
れは、金属細線１１（図１（ｂ）参照）が例えば半導体
素子１０（図１（ｂ）参照）の隅部にも接続されている
場合や、隅部近くまで接続されている場合に適応される
ものであり、特に樹脂封止部３を形成するための金型の
キャビティ形状を簡素化できるというメリットがある。 【００１８】また、図２（ｂ）に示す例では、樹脂封止
部３における金属細線１１（図１（ｂ）参照）を封止す
る部分３ｂが図１に示す場合と比べてさらに細かく分割
されている樹脂封止型半導体装置１を示している。これ
は、半導体素子１０の各辺（４辺）に対して金属細線１
１（図１（ｂ）参照）の接続されていない部分が多数あ
り、そこに樹脂封止部３を設ける必要がない場合に適応
されるものである。これによって、図１に示す樹脂封止
型半導体装置１と比べてさらに樹脂封止部３を構成する
樹脂の量を少なくできる。つまり、図２（ｂ）における
樹脂封止型半導体装置１では、図１に示す樹脂封止型半
導体装置１の場合と比べてさらに樹脂硬化時における収
縮量を少なくできるというメリットがある。 【００１９】なお、本実施例においては、いずれもＢＧ
Ａ型から成る樹脂封止型半導体装置１を例として説明し
たが、本発明はこれに限定されずＰＧＡ型から成る場合
であっても同様である。また、樹脂封止部３の形状につ
いてもこれらの実施例に限定されず、半導体素子１０や
金属細線１１（図１（ｂ）参照）の高さおよび配置位置
に合わせて設定するようにすればどのような形状であっ
ても同様である。 【００２０】 【発明の効果】以上説明したように、本発明の樹脂封止
型半導体装置によれば次のような効果がある。すなわ
ち、基板の一方面側に樹脂封止部が設けられている場合
において、この樹脂封止部を構成する樹脂の硬化時にお
ける収縮量を少なくできるため、完成後の樹脂封止型半
導体装置における反り発生を抑制できることになる。こ
れによって、樹脂封止型半導体装置とこれを実装する他
の基板との接続を確実に行うことができるようになると
ともに、電極部と他の基板上の電極パターンとの良好な
接触を得ることが可能となる。また、反りによって加わ
る半導体素子への応力を緩和できるため、電気的特性の
良好な樹脂封止型半導体装置を提供できるようになる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device in which a semiconductor element mounted on one side of a substrate is sealed with a resin. 2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, the density of electrodes such as leads for electrically connecting the semiconductor devices to external circuits has been increasing. 2. Description of the Related Art A semiconductor device including a PGA (pin grid array), a BGA (ball grid array), or the like has a large number of electrode portions arranged in an area on one side of a substrate in order to increase the density of the electrode portions. FIG. 3 is a view for explaining a conventional resin-encapsulated semiconductor device 1 made of a BGA.
(B) is a partially enlarged sectional view, and (c) shows a warped state. As shown in FIG. 3A, the resin-encapsulated semiconductor device 1
Is a substrate 2 made of, for example, BT resin or polyimide, a semiconductor element 10 mounted on one side of the substrate 2, a resin sealing portion 3 for sealing the semiconductor element 10, and a second side of the substrate 2 And an electrode portion 4 formed of a solder bump or the like arranged in a matrix. As shown in FIG. 3B, a semiconductor element 10 mounted on a substrate 2 is connected to a wiring pattern (not shown) provided on the substrate 2 by a thin metal wire 11 such as a bonding wire. The thin metal wire 11 is sealed together with the resin sealing portion 3 made of epoxy or the like. The thin metal wire 11 is electrically connected to the electrode portion 4 shown in FIG. 3A via a wiring pattern (not shown) on the substrate 2 and connects the electrode portion 4 to an external circuit (not shown). As a result, signal input / output between the semiconductor element 10 and an external circuit (not shown) is performed. [0005] However, such a resin-sealed semiconductor device has the following problems. That is, when forming a resin-sealed portion in a resin-sealed type semiconductor device, a semiconductor element mounted on one surface side of a substrate is placed in a cavity of a mold, and the softened resin is filled in the cavity. By doing so, the semiconductor element is covered with the resin. Thereafter, a resin sealing portion is formed on one surface side of the substrate by curing the resin.
However, due to the shrinkage of the resin during this curing, the completed resin-encapsulated semiconductor device is warped. That is, as shown in FIG. 3C, the resin sealing portion 3 is provided only on one side of the substrate 2, and the resin sealing portion 3 is hardened after curing due to a difference in shrinkage between the resin and the substrate 2 during curing. In the resin-sealed semiconductor device 1 described above, a concave warp is generated. When such a warp occurs, a mounting failure between the resin-encapsulated semiconductor device 1 and another substrate, that is, a contact failure between the electrode portion 4 and an electrode pattern on another substrate occurs.
In addition, the warp applies a stress to the semiconductor element in the resin sealing portion 3 and causes a characteristic failure. [0007] The present invention is a resin-sealed semiconductor device made to solve such a problem. That is, the resin-encapsulated semiconductor device of the present invention includes a semiconductor element mounted on one side of the substrate, a thin metal wire connecting the semiconductor element and a wiring pattern provided on one side of the substrate, A resin sealing portion for sealing the semiconductor element and the fine metal wire on one surface side; and an electrode portion provided on the other surface side of the substrate and electrically connected to the wiring pattern. In terms of thickness from the side, the portion that seals the semiconductor element is thinner than the portion that seals the fine metal wire, and the portion that seals the fine metal wire is divided by the portion where the thin metal wire is not connected. To be provided. According to the present invention, in a resin-sealed semiconductor device in which semiconductor elements mounted on one side of a substrate are wired with thin metal wires and sealed with a resin sealing portion, The thickness of the resin sealing portion to be sealed from one surface of the substrate is smaller than the thickness of the resin sealing portion to seal the fine metal wires from one surface of the substrate. For this reason, compared with the case where the semiconductor element is sealed with the same thickness as that for sealing the thin metal wire, the amount of resin constituting the resin sealing portion can be reduced, and the amount of shrinkage during resin curing is reduced. Will be able to In addition, since the portion for sealing the thin metal wire is divided at a portion where the thin metal wire is not connected, the amount of resin constituting the resin sealing portion can be reduced, and the amount of shrinkage during resin curing can be reduced. Become like An embodiment of a resin-sealed semiconductor device according to the present invention will be described below with reference to the drawings. 1A and 1B are diagrams illustrating a resin-sealed semiconductor device according to the present invention. FIG. 1A is a perspective view, and FIG. 1B is a partially enlarged cross-sectional view. As shown in FIG. 1A, the resin-encapsulated semiconductor device 1 in this embodiment is
A substrate 2 made of a BT resin or a polyimide-based printed wiring board, a semiconductor element 10 mounted on one side of the substrate 2, and a wiring pattern formed on one side of the semiconductor element 10 and the substrate 2 (FIG. (Not shown))
(See FIG. 1B) and a resin sealing portion 3 for sealing the semiconductor element 10 and the fine metal wire 11 on one surface side of the substrate 2.
And an electrode portion 4 provided on the other surface side of the substrate 2 and electrically connected to a wiring pattern (not shown). When a plurality of electrode portions 4 are formed of solder bumps and arranged in an area on the other surface side of the substrate 2,
The resin-encapsulated semiconductor device 1 in this embodiment is called a BGA (ball grid array). Although not shown, when the electrode section 3 is formed of metal pins and a plurality of areas are arranged on the other surface side of the substrate 2, it is called a PGA (pin grid array). In the following, the resin-sealed semiconductor device 1 made of BGA will be described as an example. In the resin-sealed semiconductor device 1 according to the present embodiment, the thickness of the resin sealing portion 3 provided on one surface side of the substrate 2 from one surface of the substrate 2 is the same as that of the portion for sealing the semiconductor element 10. It differs from the portion that seals the thin metal wire 11. That is, as shown in FIG. 1B, the semiconductor element 10 mounted on one side of the substrate 2 is connected to a wiring pattern (not shown) also formed on one side of the substrate 2. They are connected by thin metal wires 11. The thin metal wire 11 is made of, for example, a bonding wire using a gold wire, and is connected in a loop upward from the upper surface of the semiconductor element 10. In the resin-sealed semiconductor device 1 according to the present embodiment, the thickness of the resin sealing portion 3 for sealing the semiconductor element 10 and the thin metal wire 11 is smaller than that of the portion 3b for sealing the thin metal wire 11. The portion 3a for sealing the element 10 is thinner. That is, when the height of the uppermost portion from one surface of the substrate 2 is different between the thin metal wire 11 and the semiconductor element 10, the thickness of the resin sealing portion 3 from one surface of the substrate 2 Instead of making the thickness uniform according to the height of the fine wire 11, the thickness of the metal wire 11 and the semiconductor element 10 is set to a required amount (an amount that does not impair the sealing effect) according to the height of the uppermost portion of each. You have set. As a result, compared with the conventional resin-sealed semiconductor device (see FIG. 3), the resin-sealed portion 3
Can be reduced.
That is, the fact that the amount of the resin can be reduced means that, when the resin sealing portion 3 is formed, the amount of shrinkage when the resin as the material is cured can be reduced. Resin-sealed semiconductor device 1 in this embodiment
When manufacturing a semiconductor device, first, a chip-shaped semiconductor element 10 is mounted on one surface side of the substrate 2, and the semiconductor element 10 and the substrate 2 are mounted.
(Not shown) with thin metal wires 11. Thereafter, mounting of the semiconductor element 10 and the thin metal wire 1 are performed.
The substrate 2 on which the wiring by 1 is completed is set in a mold, and a resin for sealing the semiconductor element 10 and the fine metal wires 11 is filled in the cavity of the mold. At this time, the resin is poured into the cavity while being heated and melted to a predetermined temperature. As the cavity shape of the mold, a portion 3b for sealing the fine metal wire 3b is provided higher than a portion 3a for sealing the semiconductor element 10, and a resin having a different thickness as shown in FIG. It is set so as to have the shape of the sealing portion 3. After filling the molten resin in the cavity of such a mold, the resin is cured to form a resin sealing portion 3 on one surface side of the substrate 2.
To form As described above, in the resin-encapsulated semiconductor device 1 according to the present embodiment, the amount of resin constituting the resin-encapsulated portion 3 is different from that of the conventional resin-encapsulated semiconductor device (see FIG. 3). Since the amount of shrinkage can be reduced, the amount of shrinkage when the molten resin is cured can be reduced, and the occurrence of warpage of the resin-encapsulated semiconductor device 1 after completion can be suppressed. In addition, when the completed resin-encapsulated semiconductor device 1 is connected to a mounting substrate (not shown) by applying heat and performing soldering or the like, occurrence of warpage due to the heat can be suppressed. become. Next, another example of the resin-sealed semiconductor device 1 of the present invention will be described. FIG. 2 is a perspective view illustrating another example of the resin-encapsulated semiconductor device 1 according to the present invention.
Is 1 and (b) is 2. That is, FIG.
In the example shown in (a), the thin metal wire 1 in the resin sealing portion 3 is used.
1 shows a resin-sealed semiconductor device 1 in which a portion 3b for sealing 1 (see FIG. 1B) is continuously provided. This is applicable when the thin metal wire 11 (see FIG. 1B) is also connected to, for example, a corner of the semiconductor element 10 (see FIG. 1B), or when it is connected to near the corner. In particular, there is an advantage that the shape of the cavity of the mold for forming the resin sealing portion 3 can be simplified. In the example shown in FIG. 2B, the portion 3b for sealing the fine metal wire 11 (see FIG. 1B) in the resin sealing portion 3 is further finely divided as compared with the case shown in FIG. 1 shows a resin-encapsulated semiconductor device 1 that has been used. This means that each side (four sides) of the semiconductor element 10
1 (see FIG. 1 (b)) is applied when there are many unconnected portions and it is not necessary to provide the resin sealing portion 3 there. This makes it possible to further reduce the amount of resin forming the resin sealing portion 3 as compared with the resin-sealed semiconductor device 1 shown in FIG. That is, the resin-encapsulated semiconductor device 1 in FIG. 2B has an advantage that the amount of shrinkage during resin curing can be further reduced as compared with the case of the resin-encapsulated semiconductor device 1 shown in FIG. In this embodiment, all of the BG
Although the A-type resin-sealed semiconductor device 1 has been described as an example, the present invention is not limited to this, and the same applies to the case of a PGA type. Also, the shape of the resin sealing portion 3 is not limited to these embodiments, but may be set in accordance with the height and arrangement position of the semiconductor element 10 and the thin metal wires 11 (see FIG. 1B). The same applies to any shape. As described above, the resin-encapsulated semiconductor device of the present invention has the following effects. That is, when the resin sealing portion is provided on one surface side of the substrate, the amount of shrinkage of the resin constituting the resin sealing portion during curing can be reduced. Warpage can be suppressed. This makes it possible to reliably connect the resin-encapsulated semiconductor device to another substrate on which it is mounted, and to obtain good contact between the electrode portion and the electrode pattern on another substrate. Becomes possible. Further, since the stress applied to the semiconductor element due to the warpage can be reduced, a resin-sealed semiconductor device having good electric characteristics can be provided.

【図面の簡単な説明】 【図１】本発明の樹脂封止型半導体装置を説明する図
で、（ａ）は斜視図、（ｂ）は部分拡大断面図である。 【図２】他の例を説明する斜視図で、（ａ）はその１、
（ｂ）はその２である。 【図３】従来例を説明する図で、（ａ）は斜視図、
（ｂ）は部分拡大断面図、（ｃ）は反り状態を示してい
る。 【符号の説明】 １…樹脂封止型半導体装置、２…基板、３…樹脂封止
部、４…電極部、１０…半導体素子、１１…金属細線BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining a resin-sealed semiconductor device of the present invention, in which (a) is a perspective view and (b) is a partially enlarged cross-sectional view. FIGS. 2A and 2B are perspective views illustrating another example, in which FIG.
(B) is the second. 3A and 3B are diagrams illustrating a conventional example, in which FIG.
(B) is a partially enlarged sectional view, and (c) shows a warped state. [Description of Signs] 1 ... resin-sealed semiconductor device, 2 ... substrate, 3 ... resin-sealed portion, 4 ... electrode portion, 10 ... semiconductor element, 11 ... fine metal wire

Claims (1)

【特許請求の範囲】 【請求項１】 基板の一方面側に実装される半導体素子
と、該半導体素子と該基板の一方面側に形成された配線
パターンとを接続する金属細線と、該基板の一方面側に
おいて該半導体素子および該金属細線を封止する樹脂封
止部と、該基板の他方面側に設けられ該配線パターンと
導通する電極部とを備えた樹脂封止型半導体装置であっ
て、 前記樹脂封止部における前記基板の一方面からの厚さ
は、前記金属細線を封止する部分に比べて前記半導体素
子を封止する部分の方が薄くなっているとともに前記金
属細線を封止する部分が前記金属細線の接続されていな
い部分で分割されていることを特徴とする樹脂封止型半
導体装置。Claims: 1. A semiconductor element mounted on one side of a substrate, a thin metal wire connecting the semiconductor element to a wiring pattern formed on one side of the substrate, and the substrate A resin-sealed portion for sealing the semiconductor element and the fine metal wire on one side of the substrate, and an electrode portion provided on the other side of the substrate and electrically connected to the wiring pattern. The thickness of the resin sealing portion from one surface of the substrate is smaller in a portion for sealing the semiconductor element than in a portion for sealing the thin metal wire, and the thickness of the thin metal wire is reduced. A resin-sealed semiconductor device, wherein a portion for sealing is divided at a portion where the thin metal wire is not connected.
JP2003037906A 2003-02-17 2003-02-17 Resin-sealing semiconductor device Withdrawn JP2003218290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003037906A JP2003218290A (en) 2003-02-17 2003-02-17 Resin-sealing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003037906A JP2003218290A (en) 2003-02-17 2003-02-17 Resin-sealing semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP6197377A Division JPH0846072A (en) 1994-07-29 1994-07-29 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JP2003218290A true JP2003218290A (en) 2003-07-31

Family

ID=27656239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003037906A Withdrawn JP2003218290A (en) 2003-02-17 2003-02-17 Resin-sealing semiconductor device

Country Status (1)

Country Link
JP (1) JP2003218290A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103098202A (en) * 2010-09-14 2013-05-08 高通股份有限公司 Electronic packaging with a variable thickness mold cap
US9478523B2 (en) 2014-11-14 2016-10-25 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103098202A (en) * 2010-09-14 2013-05-08 高通股份有限公司 Electronic packaging with a variable thickness mold cap
JP2013537372A (en) * 2010-09-14 2013-09-30 クアルコム，インコーポレイテッド Electronic packaging with mold caps of variable thickness
US8753926B2 (en) 2010-09-14 2014-06-17 Qualcomm Incorporated Electronic packaging with a variable thickness mold cap
JP2015144314A (en) * 2010-09-14 2015-08-06 クアルコム，インコーポレイテッド Electronic packaging with variable thickness mold cap
US9478523B2 (en) 2014-11-14 2016-10-25 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same

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