JP3171297B2 - Package mounting method - Google Patents

Package mounting method

Info

Publication number
JP3171297B2
JP3171297B2 JP17840494A JP17840494A JP3171297B2 JP 3171297 B2 JP3171297 B2 JP 3171297B2 JP 17840494 A JP17840494 A JP 17840494A JP 17840494 A JP17840494 A JP 17840494A JP 3171297 B2 JP3171297 B2 JP 3171297B2
Authority
JP
Japan
Prior art keywords
package
solder bumps
solder
bump
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP17840494A
Other languages
Japanese (ja)
Other versions
JPH0846313A (en
Inventor
直樹 山崎
憲治 池滝
徹 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17840494A priority Critical patent/JP3171297B2/en
Publication of JPH0846313A publication Critical patent/JPH0846313A/en
Application granted granted Critical
Publication of JP3171297B2 publication Critical patent/JP3171297B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16058—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8193—Reshaping
    • H01L2224/81935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明はＩＣパッケージ等のパッ
ケージの実装方法に関し、更に詳しくは、下面に複数の
半田バンプを有するＢＧＡパッケージ（ボールグリッド
アレイパッケージ）の実装方法に関する。The present invention relates to a method of mounting a package such as an IC package, and more particularly, to a method of mounting a BGA package (ball grid array package) having a plurality of solder bumps on a lower surface.

【０００２】近年、ＩＣパッケージの高密度化に伴い、
リードを有するパッケージとしては、リードピッチが
０．３mm乃至０．４mmのものが実用に供されている。特
に、最近においては、更なる高密度化のためにリードを
有していないＢＧＡパッケージが注目されており、その
実装技術の最適化が模索されている。[0002] In recent years, with the increasing density of IC packages,
As a package having leads, a package having a lead pitch of 0.3 mm to 0.4 mm has been put to practical use. In particular, recently, a BGA package having no lead has been attracting attention for further densification, and optimization of the mounting technology has been sought.

【０００３】[0003]

【従来の技術】従来、図５の（Ａ）に示されるように、
パッケージ２の下面に設けられた複数の半田バンプ４を
プリント配線板６上で溶融させることで、パッケージ２
をプリント配線板６上の導体パターン８に半田付け接続
するようにしたパッケージの実装構造が公知である。2. Description of the Related Art Conventionally, as shown in FIG.
By melting a plurality of solder bumps 4 provided on the lower surface of the package 2 on the printed wiring board 6, the package 2
There is known a package mounting structure in which is connected to a conductor pattern 8 on a printed wiring board 6 by soldering.

【０００４】半田バンプの溶融は、例えばプリント配線
板６上にパッケージ２を載置して、これをリフロー炉内
で加熱することにより行われる。[0004] The melting of the solder bumps is performed, for example, by placing the package 2 on a printed wiring board 6 and heating it in a reflow furnace.

【０００５】[0005]

【発明が解決しようとする課題】従来のパッケージの実
装方法においては、半田バンプの溶融に際してパッケー
ジがその自重により沈み込んでしまい、図５の（Ａ）に
示されるようにバンプ接合部が樽形になり、接合部にク
ラックが発生し易くなる。In the conventional package mounting method, when the solder bump is melted, the package sinks due to its own weight, and as shown in FIG. And cracks are likely to occur at the joints.

【０００６】これに対処するために、半田バンプを溶融
させる際に適当な治具を用いてパッケージを引っ張り上
げる作業を行い、図５の（Ｂ）に示されるように接合部
の形状を鼓形にしている。In order to cope with this, when melting the solder bumps, an operation of pulling up the package by using an appropriate jig is performed, and the shape of the joint is changed to a drum shape as shown in FIG. I have to.

【０００７】しかし、この場合、パッケージを引っ張り
上げる作業が煩雑であり、量産には不向きである。However, in this case, the operation of pulling up the package is complicated and is not suitable for mass production.

【０００８】よって、本発明の目的は、接合部にクラッ
クが発生しにくく且つ製造作業性に優れたパッケージの
実装方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of mounting a package in which cracks are less likely to occur in a joint portion and which is excellent in manufacturing workability.

【０００９】[0009]

【課題を解決するための手段】本発明によると、プリン
ト配線板にパッケージを半田バンプにて実装するパッケ
ージの実装方法において、前記パッケージにおける該半
田バンプが形成された下面で且つ直線上にない少なくと
も３箇所に、該半田バンプの直径と略同じ高さを有し、
該半田バンプよりも高融点の半田からなるダミーバンプ
を、前記半田バンプとともに形成し、該パッケージの該
半田バンプと前記プリント配線板に形成された導体パタ
ーンとが対向するように位置決めして載置し、半田バン
プを加熱溶融させることで当該半田バンプを鼓形状にす
ることを特徴とするパッケージの実装方法、が提供され
る。According to the SUMMARY for the present invention, in the mounting method of a package mounting the package on a printed wiring board by solder bumps, and at the lower surface of said half <br/> field bump in the package is formed At least three locations that are not on a straight line have a height substantially equal to the diameter of the solder bump,
A dummy bump made of solder having a higher melting point than the solder bump is formed together with the solder bump , and the solder bump of the package is positioned and placed so as to face a conductor pattern formed on the printed wiring board. In addition, there is provided a package mounting method characterized in that a solder bump is formed into a drum shape by heating and melting the solder bump.

【００１０】[0010]

【作用】本発明によると、パッケージの下面に多数の半
田バンプが形成されるとともに、そのパッケージの下面
の特定箇所に、その半田バンプとは別に、半田バンプの
直径と略同じ高さを有し、尚且つ半田バンプよりも高融
点の半田からなるダミーバンプを設けたことにより、半
田バンプを溶融させるに際してパッケージが沈み込むこ
とが無くなり、半田バンプを鼓形状にすることができ
る。According to the present invention , a number of semi-conductors are provided on the lower surface of the package.
A bump is formed, and the lower surface of the package is formed.
In a specific place, separate from the solder bump,
Has almost the same height as the diameter, and has a higher melting point than solder bumps
By providing the dummy bumps made of point solder , the package does not sink when the solder bumps are melted, and the solder bumps can be shaped like a drum.

【００１１】本発明によると、半田バンプを溶融させる
に際してパッケージを引っ張り上げる作業が不要になる
ので、製造作業性が向上する。According to the present invention, it is not necessary to pull up the package when melting the solder bumps, so that the operability in manufacturing is improved.

【００１２】このように、本発明によると、接合部にク
ラックが発生しにくく且つ製造作業性に優れたパッケー
ジの実装方法の提供が可能になる。As described above, according to the present invention, it is possible to provide a package mounting method in which cracks are less likely to occur in a joint portion and excellent in workability.

【００１３】[0013]

【実施例】以下、本発明の実施例を説明する。Embodiments of the present invention will be described below.

【００１４】図１は本発明の第１実施例を示すパッケー
ジの側面図（Ａ）及び底面図（Ｂ）である。この実施例
は本発明の第１の構成の具体例に相当している。FIG. 1 is a side view (A) and a bottom view (B) of a package showing a first embodiment of the present invention. This embodiment corresponds to a specific example of the first configuration of the present invention.

【００１５】この実施例では、パッケージ２の底面の四
隅にそれぞれダミーバンプ１０が設けられている。ダミ
ーバンプ１０は、高融点半田、レジスト、樹脂或いはメ
ッキ等により形成することができる。In this embodiment, dummy bumps 10 are provided at the four corners of the bottom surface of the package 2 respectively. The dummy bump 10 can be formed by high melting point solder, resist, resin, plating, or the like.

【００１６】図２は本発明の第１実施例における原理の
説明図である。半田バンプ４を溶融させる前には、半田
バンプ４は図１の（Ａ）に示されるようにほぼ球形の形
状をしており、ダミーバンプ１０の高さは半田バンプ４
の直径にほぼ等しく設定されている。FIG. 2 is an explanatory diagram of the principle in the first embodiment of the present invention. Before the solder bumps 4 are melted, the solder bumps 4 have a substantially spherical shape as shown in FIG. 1A, and the height of the dummy bumps 10 is
Is set to be approximately equal to the diameter.

【００１７】パッケージ２をプリント配線板６に実装す
るに際しては、半田バンプ４が対応する導体パターン８
に対向するようにパッケージ２の位置決めを行った後、
パッケージ２をプリント配線板６上に載置する。When the package 2 is mounted on the printed wiring board 6, the solder bumps 4 correspond to the corresponding conductor patterns 8
After positioning the package 2 so as to face the
The package 2 is placed on the printed wiring board 6.

【００１８】そして、この状態でプリント配線板６を予
め定められた温度に加熱されているリフロー炉内に導入
する。こうして半田バンプ４が溶融すると、この実施例
では、図２に示されるようにダミーバンプ１０の存在に
よってパッケージ２が沈み込むことがないので、溶融し
た半田バンプ４はプリント配線板６上の導体パターン８
とパッケージ２の下面に設けられた図示しない電極との
間の表面張力によって鼓形になり、この状態でプリント
配線板６をリフロー炉から取り出すと、半田バンプ４が
鼓形状を保ったまま凝固するのである。Then, in this state, the printed wiring board 6 is introduced into a reflow furnace heated to a predetermined temperature. When the solder bumps 4 are melted in this manner, in this embodiment, the package 2 does not sink due to the presence of the dummy bumps 10 as shown in FIG.
When the printed wiring board 6 is taken out of the reflow furnace in this state, the solder bumps 4 solidify while maintaining the drum shape due to the surface tension between the electrode and an electrode (not shown) provided on the lower surface of the package 2. It is.

【００１９】凝固した半田バンプ４は、前述したよう
に、樽形であるよりも鼓形である方が信頼性が高い。従
って、この実施例によると、信頼性の高いパッケージの
実装が可能になる。As described above, the solidified solder bumps 4 are more reliable if they are drum-shaped than barrel-shaped. Therefore, according to this embodiment, a highly reliable package can be mounted.

【００２０】また、この実施例では、半田バンプを溶融
させる際に従来のような特殊な治具が不要であるので、
製造作業性が向上する。Further, in this embodiment, a special jig as in the prior art is unnecessary when melting the solder bumps.
Manufacturing workability is improved.

【００２１】図３は本発明の第２実施例を示す図であ
り、この実施例は本発明の第２の構成の具体例に相当し
ている。FIG. 3 is a view showing a second embodiment of the present invention. This embodiment corresponds to a specific example of the second configuration of the present invention.

【００２２】この実施例では、パッケージ２の下面にダ
ミーバンプを設けることに代えて、プリント配線板６上
にダミーバンプ１０’を設けている。ダミーバンプ１
０’はプリント配線板６上のパッケージ２に対向する部
分の直線上にない少なくとも３箇所に設ければよいので
あるが、この実施例では、パッケージ２をプリント配線
板６上に載置するに際しての位置決めを容易にするため
に、ダミーバンプ１０’をプリント配線板６上のパッケ
ージ２の四隅に対向する位置にそれぞれ設けている。In this embodiment, a dummy bump 10 ′ is provided on the printed wiring board 6 instead of providing the dummy bump on the lower surface of the package 2. Dummy bump 1
0 'may be provided in at least three places on the printed wiring board 6 which are not on a straight line in a portion facing the package 2, but in this embodiment, when the package 2 is mounted on the printed wiring board 6, In order to facilitate positioning, dummy bumps 10 ′ are provided at positions facing the four corners of the package 2 on the printed wiring board 6.

【００２３】本実施例によると、パッケージ２をプリン
ト配線板６上に載置して半田バンプ４を溶融させるに際
して、前実施例におけるのと同じように半田バンプ４を
鼓形にすることができ、パッケージの信頼性が高い実装
が可能になる。また、この実施例でも、特殊な治具が不
要であるので、製造作業性が良好である。更に、この実
施例では、ダミーバンプ１０’をプリント配線板６上の
パッケージ２の四隅に対応する位置に設けているので、
パッケージ２をプリント配線板６上に載置するに際して
の位置決めが極めて容易である。According to the present embodiment, when the package 2 is placed on the printed wiring board 6 and the solder bumps 4 are melted, the solder bumps 4 can be shaped like a drum in the previous embodiment. Therefore, the package can be mounted with high reliability. Also in this embodiment, since a special jig is not required, the manufacturing workability is good. Further, in this embodiment, since the dummy bumps 10 'are provided at positions corresponding to the four corners of the package 2 on the printed wiring board 6,
Positioning when mounting the package 2 on the printed wiring board 6 is extremely easy.

【００２４】図４は本発明の第３実施例を示すパッケー
ジの部分側面図であり、この実施例は本発明の第３の構
成に対応している。FIG. 4 is a partial side view of a package showing a third embodiment of the present invention. This embodiment corresponds to the third configuration of the present invention.

【００２５】この実施例では、半田バンプ４に、パッケ
ージ２の下面から突出するピン１２を埋設している。ピ
ン１２の材質としては、金属等の半田バンプ４の溶融温
度で変形しないものが選択される。また、ピン１２は複
数ある半田バンプのうちの直線上にない少なくとも３つ
の半田バンプについて設けられている。例えば、複数の
半田バンプ４が格子状に形成されている場合には、その
四隅の半田バンプについてピン１２が設けられる。In this embodiment, pins 12 projecting from the lower surface of the package 2 are embedded in the solder bumps 4. As the material of the pin 12, a material such as a metal that does not deform at the melting temperature of the solder bump 4 is selected. The pins 12 are provided for at least three solder bumps that are not on a straight line among the plurality of solder bumps. For example, when a plurality of solder bumps 4 are formed in a grid, pins 12 are provided for the solder bumps at the four corners.

【００２６】図４において符号１４は各半田バンプ４に
対応してパッケージ２の下面に設けられた電極を表して
おり、ピン１２は例えば電極１４と一体に形成される。
図示はしないが、ピン１２は電極１４を貫通してパッケ
ージ２の内部に埋設されていてもよい。In FIG. 4, reference numeral 14 denotes an electrode provided on the lower surface of the package 2 corresponding to each solder bump 4, and the pin 12 is formed integrally with the electrode 14, for example.
Although not shown, the pin 12 may be embedded in the package 2 through the electrode 14.

【００２７】尚、ピン１２の高さは半田バンプ４が溶融
する前の球形であるときのほぼ直径に等しく設定され
る。この実施例によっても、これまでの実施例と同様
に、半田バンプ４を溶融させるに際して鼓形にすること
ができるので、接合部にクラックが発生しにくく、信頼
性の高いパッケージの実装が可能になる。尚、図３の第
２実施例において、ダミーバンプ１０’は例えば基板６
上で接着剤を固化させることにより形成することができ
る。The height of the pin 12 is set to be substantially equal to the diameter of the solder bump 4 when the solder bump 4 has a spherical shape before melting. According to this embodiment, similarly to the previous embodiments, since the solder bump 4 can be formed into a drum shape when it is melted, cracks are less likely to occur at the joints, and a highly reliable package can be mounted. Become. In the second embodiment shown in FIG. 3, the dummy bump 10 '
It can be formed by solidifying the adhesive above.

【００２８】[0028]

【発明の効果】以上説明したように、本発明によると、
接合部にクラックが発生しにくく且つ製造作業性に優れ
たパッケージの実装方法の提供が可能になるという効果
が生じる。As described above, according to the present invention,
There is an effect that it is possible to provide a package mounting method in which cracks are less likely to occur in the joint portion and excellent in workability.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施例を示すパッケージの側面図
（Ａ）及び底面図（Ｂ）である。FIG. 1 is a side view (A) and a bottom view (B) of a package showing a first embodiment of the present invention.

【図２】本発明の第１実施例における原理の説明図であ
る。FIG. 2 is an explanatory diagram of a principle in the first embodiment of the present invention.

【図３】本発明の第２実施例の説明図である。FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

【図４】本発明の第３実施例を示すパッケージの部分側
面図である。FIG. 4 is a partial side view of a package showing a third embodiment of the present invention.

【図５】従来技術の説明図である。FIG. 5 is an explanatory diagram of a conventional technique.

【符号の説明】[Explanation of symbols]

２ パッケージ ４ 半田バンプ ６ プリント配線板 ８ 導体パターン １０，１０’ ダミーバンプ １２ ピン 2 Package 4 Solder bump 6 Printed wiring board 8 Conductor pattern 10, 10 'Dummy bump 12 pin

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−177205（ＪＰ，Ａ) 特開 昭49−92548（ＪＰ，Ａ) 特開 平１−185952（ＪＰ，Ａ) 特公 昭53−36312（ＪＰ，Ｂ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H05K 1/14 H01L 21/60 311 H05K 3/36 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-177205 (JP, A) JP-A-49-92548 (JP, A) JP-A-1-185952 (JP, A) 36312 (JP, B1) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 1/14 H01L 21/60 311 H05K 3/36

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 プリント配線板にパッケージを半田バン
プにて実装するパッケージの実装方法において、 前記パッケージにおける該半田バンプが形成された下面
で且つ直線上にない少なくとも３箇所に、該半田バンプ
の直径と略同じ高さを有し、該半田バンプよりも高融点
の半田からなるダミーバンプを、前記半田バンプととも
に形成し、 該パッケージの該半田バンプと前記プリント配線板に形
成された導体パターンとが対向するように位置決めして
載置し、 半田バンプを加熱溶融させることで当該半田バンプを鼓
形状にすることを特徴とするパッケージの実装方法。1. A mounting method of a package for mounting the package on a printed wiring board by solder bumps, at least three not in and straight line at a bottom surface of said solder bumps is formed in the package, solder bumps
Has a height approximately the same as the diameter of the solder bump and a higher melting point than the solder bump.
The dummy bump and, together with the solder bumps made from solder
The solder bumps of the package are positioned and placed so that the solder bumps of the package and the conductor pattern formed on the printed wiring board are opposed to each other, and the solder bumps are heated and melted to form a drum shape. A package mounting method characterized by the above-mentioned.
JP17840494A 1994-07-29 1994-07-29 Package mounting method Expired - Lifetime JP3171297B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17840494A JP3171297B2 (en) 1994-07-29 1994-07-29 Package mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17840494A JP3171297B2 (en) 1994-07-29 1994-07-29 Package mounting method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2000296216A Division JP3430138B2 (en) 2000-09-28 2000-09-28 Package mounting method

Publications (2)

Publication Number Publication Date
JPH0846313A JPH0846313A (en) 1996-02-16
JP3171297B2 true JP3171297B2 (en) 2001-05-28

Family

ID=16047910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17840494A Expired - Lifetime JP3171297B2 (en) 1994-07-29 1994-07-29 Package mounting method

Country Status (1)

Country Link
JP (1) JP3171297B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6316735B1 (en) * 1996-11-08 2001-11-13 Ricoh Company, Ltd. Semiconductor chip mounting board and a semiconductor device using same board
JP3179420B2 (en) 1998-11-10 2001-06-25 日本電気株式会社 Semiconductor device
JP3418134B2 (en) * 1999-02-12 2003-06-16 ローム株式会社 Semiconductor device with chip-on-chip structure
JP3490987B2 (en) 2001-07-19 2004-01-26 沖電気工業株式会社 Semiconductor package and manufacturing method thereof
US6960830B2 (en) 2002-10-31 2005-11-01 Rohm Co., Ltd. Semiconductor integrated circuit device with dummy bumps
JP4650269B2 (en) * 2006-01-05 2011-03-16 日立電線株式会社 Manufacturing method of stacked semiconductor device
JP2008199198A (en) * 2007-02-09 2008-08-28 New Japan Radio Co Ltd Gunn diode oscillator
JP2008227271A (en) 2007-03-14 2008-09-25 Fujitsu Ltd Electronic device and electronic component mounting method
JP5170123B2 (en) * 2010-02-05 2013-03-27 日立電線株式会社 Multilayer semiconductor device and manufacturing method thereof
JP6608640B2 (en) 2015-07-28 2019-11-20 新光電気工業株式会社 Manufacturing method of mounting structure

Also Published As

Publication number Publication date
JPH0846313A (en) 1996-02-16

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