JPH098081A - Mounting structure of bga package - Google Patents
Mounting structure of bga packageInfo
- Publication number
- JPH098081A JPH098081A JP7153595A JP15359595A JPH098081A JP H098081 A JPH098081 A JP H098081A JP 7153595 A JP7153595 A JP 7153595A JP 15359595 A JP15359595 A JP 15359595A JP H098081 A JPH098081 A JP H098081A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- soldering land
- double
- land
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多数個の半田ボールを
有するＢＧＡ型パッケージの実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA type package mounting structure having a large number of solder balls.
【０００２】[0002]
【従来の技術】従来、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａ
ｒｒａｙ）型パッケージ１は、図５及び図６（Ａ）
（Ｂ）に示されているように、両面プリント基板２の表
面には半導体等のチップ部品３が搭載され、同部品３と
基板２はワイヤ４によって接続され、その表面は樹脂５
によってモールドされており、裏面に高融点の半田ペー
ストが選択的に被着された第１の半田付ランド６が形成
され、同第１の半田付ランド６に半田ボール７がリフロ
ーによって接合されている。一方、面実装用回路基板８
には前記半田ボール７に対応して同半田ボール７をリフ
ローによって接合する第２の半田付ランド９が形成され
ている。ところで、前記ＢＧＡ型パッケージ１は、その
構造上特に次のような問題を有している。即ち、前記第
１の半田付ランド６に半田ボール７をリフローする際
に、前記両面プリント基板２の熱膨脹係数が樹脂５の熱
膨脹係数よりもやや小さいため図７に示すように前記両
面プリント基板２の第２の半田付ランド９が中央部に近
づくにしたがって上側に、周縁部に近づくにしたがって
下側に反りを生じ、この反りの量は約０．２ｍｍ程度と
なる。また、前記リフローによって半田ボール７が溶融
すると、リフロー後の半田ボール７ａの高さは０．５ｍ
ｍ程度となるため面実装用回路基板８の表面に対して両
面プリント基板の中央部の半田ボール７の下端が面実装
用回路基板１の表面から離れ半田付ランド８とオープン
になり接合が不完全になるという問題を有するものであ
った。2. Description of the Related Art Conventionally, BGA (Ball Grid A)
rray) type package 1 is shown in FIG. 5 and FIG.
As shown in (B), a chip component 3 such as a semiconductor is mounted on the surface of the double-sided printed circuit board 2, the component 3 and the substrate 2 are connected by a wire 4, and the surface thereof is made of resin 5.
Is formed by molding, and a first soldering land 6 to which a high melting point solder paste is selectively applied is formed on the back surface, and solder balls 7 are joined to the first soldering land 6 by reflow. There is. On the other hand, surface mounting circuit board 8
A second solder land 9 is formed corresponding to the solder ball 7 to join the solder ball 7 by reflow. By the way, the BGA type package 1 has the following problems due to its structure. That is, when the solder balls 7 are reflowed on the first soldering lands 6, the coefficient of thermal expansion of the double-sided printed circuit board 2 is slightly smaller than that of the resin 5, so that the double-sided printed circuit board 2 as shown in FIG. The second soldering land 9 warps upward as it approaches the central portion, and warps downward as it approaches the peripheral portion, and the amount of warping is about 0.2 mm. When the solder balls 7 are melted by the reflow, the height of the solder balls 7a after the reflow is 0.5 m.
Since the distance is about m, the lower end of the solder ball 7 at the center of the double-sided printed circuit board is separated from the surface of the surface-mounting circuit board 1 from the surface of the surface-mounting circuit board 1 and becomes open with the soldering land 8 and thus the bonding is not possible. It had the problem of becoming perfect.
【０００３】[0003]
【発明が解決しようとする課題】本技術は上記問題に鑑
みなされたもので、両面プリント基板の反りにかかわら
ず半田ボールが第２の半田付ランドとオープンにならな
いように、それぞれの半田ボールの下端が面実装用回路
基板の表面に接触するようにし、これによって半田ボー
ルと第２の半田付ランドとの接合を完全なものとし、接
続信頼性の高いＢＧＡ型パッケージの実装構造を提供す
ることを目的とする。The present technology has been made in view of the above problems. To prevent the solder ball from opening with the second solder land regardless of the warp of the double-sided printed circuit board, To provide a mounting structure of a BGA type package having a high connection reliability by allowing the lower end to contact the surface of the surface mounting circuit board, thereby completing the joint between the solder ball and the second solder land. With the goal.
【０００４】[0004]
【課題を解決するための手段】本発明は上述の課題を解
決するため、両面プリント基板の表面に部品を搭載し、
同部品を樹脂モールドし、裏面に多数の第１の半田付ラ
ンドを形成したＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａ
ｙ）型パッケージを、表面に前記半田ボールに対応する
第２の半田付ランドが形成された面実装用回路基板に実
装するものにおいて、前記ＢＧＡ型パッケージの両面プ
リント基板の反りに合わせて前記面実装用回路基板の第
２の半田付ランドの面積を可変するようにしたことを特
徴とする。また、前記第２の半田付ランドの面積を前記
両面プリント基板の反りの量の１／２となる位置に対応
する第２の半田付ランドを基準にして、前記反りが下側
になるに従って漸次広く、上側に反るに従って漸次狭く
するように形成したことを特徴とする。In order to solve the above-mentioned problems, the present invention mounts parts on the surface of a double-sided printed circuit board,
BGA (Ball Grid Arra) in which the same parts are resin-molded and a large number of first soldering lands are formed on the back surface.
y) The type package is mounted on a surface mounting circuit board having second soldering lands corresponding to the solder balls formed on the surface thereof, and the surface is adjusted according to the warp of the double-sided printed circuit board of the BGA type package. The area of the second soldering land of the mounting circuit board is variable. Further, the area of the second solder land is gradually reduced as the warp becomes lower with reference to the second solder land corresponding to the position where the amount of warp of the double-sided printed circuit board is 1/2. It is characterized in that it is formed so as to be wide and gradually narrow as it goes upward.
【０００５】[0005]
【作用】上記のように構成したので、本発明によるＢＧ
Ａ型パッケージの実装構造においては、前記両面プリン
ト基板の反りの量の１／２の位置に対応する第２の半田
付ランドに対して広い面積に形成した第２の半田付ラン
ドの半田ボールは広くリフローされて高さが低くなり、
狭い面積に形成した第２の半田付ランドの半田ボールは
狭くリフローされて高さが高くなり、それぞれの半田ボ
ールを面実装用回路基板の第２の半田付ランドに確実に
接続することができる。With the above construction, the BG according to the present invention
In the mounting structure of the A-type package, the solder balls of the second soldering land formed in a wider area than the second soldering land corresponding to the position of 1/2 of the warp amount of the double-sided printed circuit board are Widely reflowed to lower the height,
The solder balls of the second soldering lands formed in a narrow area are reflowed narrowly to increase the height, and each solder ball can be reliably connected to the second soldering lands of the surface mounting circuit board. .
【０００６】[0006]
【実施例】以下図に基づいて本発明によるＢＧＡ型パッ
ケージの実装構造の一実施例を図面に基づいて詳細に説
明する。尚、図中符号は従来例と同一のものを付す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a BGA type package mounting structure according to the present invention will be described in detail below with reference to the drawings. The reference numerals in the figure are the same as those in the conventional example.
【０００７】図１及び図２（Ａ）（Ｂ）に示すように、
１はＢＧＡ型パッケージで、同ＢＧＡ型パッケージ１の
両面プリント基板２の表面には、例えば、半導体チップ
等の部品３が搭載され、同部品３と基板２とはワイヤ４
によって接続され、その表面は、例えば、シリコンゴム
よりなる樹脂５によってモールドされ、裏面には高融点
半田が選択的に被着された第１の半田付ランド６にリフ
ローによって真球状になった同一直径の半田ボール７が
接続されている。８は面実装用回路基板で、その表面に
は前記半田ボール７に対応して低融点の半田ペーストが
選択的に被着された第２の半田付ランド９が形成されて
いる。As shown in FIGS. 1 and 2A and 2B,
Reference numeral 1 denotes a BGA type package, and a component 3 such as a semiconductor chip is mounted on the surface of a double-sided printed circuit board 2 of the BGA type package 1.
, The front surface of which is molded with a resin 5 made of, for example, silicon rubber, and the rear surface of which is made into a true spherical shape by a reflow process on a first soldering land 6 to which a high melting point solder is selectively applied. Solder balls 7 of diameter are connected. Reference numeral 8 denotes a surface mounting circuit board, on the surface of which second solder lands 9 corresponding to the solder balls 7 and having a low melting point solder paste selectively applied are formed.
【０００８】また、前記両面プリント基板２は、その熱
膨脹係数が樹脂５の熱膨脹係数よりやや小さいため、前
記リフローの際に面実装用回路基板８に対し、周縁部Ｂ
が下側に、中央部Ａが上側に反りが生じ、この反りのた
め周縁部Ｂの第１の半田付ランド６は中央部Ｃの第１の
半田付ランド６よりも面実装用回路基板８に近いように
なっている。一方、前記面実装用回路基板８の第２の半
田付ランド９の面積は前記両面プリント基板２の反りの
量の１／２となる位置の第２の半田付ランド９の面積を
基準とし、この第２の半田付ランド９に対し、他の第２
の半田付ランド９の面積は両面プリント基板２が下側に
反るに従って漸次広く、上側に反るに従って漸次狭くな
るように形成されている。Since the coefficient of thermal expansion of the double-sided printed circuit board 2 is slightly smaller than that of the resin 5, the peripheral portion B of the surface-mounting circuit board 8 during the reflow process.
Is warped on the lower side and the central portion A is warped on the upper side. Due to this warpage, the first soldering land 6 on the peripheral portion B is more surface-mounted than the first soldering land 6 on the central portion C. It is close to. On the other hand, the area of the second soldering land 9 of the surface mounting circuit board 8 is based on the area of the second soldering land 9 at a position which is 1/2 of the amount of warpage of the double-sided printed board 2. For this second soldering land 9, another second
The area of the soldering land 9 is formed such that it gradually widens as the double-sided printed circuit board 2 warps downward, and becomes gradually narrower as the double-sided printed circuit board 2 warps upward.
【０００９】上記構成による面実装用回路基板８の第２
の半田付ランドにＢＧＡ型パッケージ１をリフローによ
って接合すると、図３に示すように基準とした第２の半
田付ランド９に対し、広い面積の第２の半田付ランド９
上でリフローされた半田ボール７ａは裾野が広く、且
つ、中央部が太い太鼓状となって高さが低くなり、狭い
面積の第２の半田付ランド９上でリフロされた第２の半
田ボール７ａはその裾野が狭く、且つ、中央部が細くな
って高さが高くなり、中央部の半田ボール７等が反りに
よって面実装用回路基板８の表面から離れることがな
く、リフローされた半田ボール７ａの全てが半田付ラン
ド９に完全に接合される。The second of the surface mounting circuit board 8 having the above structure
When the BGA type package 1 is joined to the soldering land 9 of FIG. 3 by reflow, the second soldering land 9 having a larger area than the second soldering land 9 used as a reference as shown in FIG.
The reflowed solder ball 7a has a wide skirt and a thick drum shape at the center to have a low height, and is reflowed on the second solder land 9 having a small area. 7a has a narrow skirt, and the central part becomes thin and the height becomes high. The solder balls 7 and the like in the central part do not separate from the surface of the surface mounting circuit board 8 due to warping, and the reflowed solder balls All of 7a are completely bonded to the soldering land 9.
【００１０】図４は本発明によるＢＧＡ型パッケージの
実装構造の他の実施例を示すもので、両面プリント基板
２は、その熱膨脹係数が樹脂５の熱膨脹係数よりやや小
さいため、同図（Ａ）に示すように前記リフローの際に
面実装用回路基板８に対し、平面上の縦方向（Ｘ−Ｘ）
と横方向（Ｙ−Ｙ）のそれぞれは周縁部が下側に、中央
部が上側に反りが生じ、この反りのため周縁部の第１の
半田付ランド６は中央部の第１の半田付ランド６よりも
面実装用回路基板８に近いようになっている。一方、同
図（Ｂ）に示すように面実装用回路基板８の第２の半田
付ランド９は前記両面プリント基板２の反りの量の１／
２となる位置の第２の半田付ランド９の面積を基準と
し、他の第２の半田付ランド９の面積は両面プリント基
板２が下側に反るに従って漸次広く、上側に反るに従っ
て漸次狭くなるように形成されている。FIG. 4 shows another embodiment of the mounting structure of the BGA type package according to the present invention. Since the coefficient of thermal expansion of the double-sided printed board 2 is slightly smaller than that of the resin 5, FIG. In the reflow, as shown in FIG. 7, the vertical direction (XX) on the plane with respect to the circuit board 8 for surface mounting.
And the lateral direction (Y-Y), the peripheral edge portion warps downward and the central portion warps upward. Due to this warpage, the first soldering land 6 on the peripheral edge portion is subjected to the first soldering on the central portion. It is closer to the surface mounting circuit board 8 than the land 6. On the other hand, as shown in FIG. 2B, the second soldering land 9 of the surface mounting circuit board 8 is 1 / th of the warp amount of the double-sided printed board 2.
Based on the area of the second soldering land 9 at the position of 2, the area of the other second soldering land 9 is gradually widened as the double-sided printed circuit board 2 warps downward, and gradually as the double-sided printed board 2 warps upward. It is formed to be narrow.
【００１１】上記構成による面実装用回路基板８の第２
の半田付ランド９にＢＧＡ型パッケージ１をリフローに
よって接合すると、基準とした第２の半田付ランド９に
対し、広い面積の第２の半田付ランド９上でリフローさ
れた半田ボール７は裾野が広く、且つ、中央部が太い太
鼓状となって高さが低くなり、狭い面積の第２の半田付
ランド９上でリフロされた第２の半田ボール７はその裾
野が狭く、且つ、中央部が細くなって高さが高くなり、
中央部の半田ボール７が反りによって面実装用回路基板
８の表面から離れることがなく、全ての半田ボール７が
第２の半田付ランド９に完全に接合される。The second of the surface mounting circuit board 8 having the above structure
When the BGA type package 1 is joined to the soldering land 9 by reflow, the solder ball 7 reflowed on the second soldering land 9 having a large area has a skirt with respect to the reference second soldering land 9. The second solder ball 7 reflowed on the second soldering land 9 having a wide area and a thick center portion having a thick drum shape and a low height has a narrow skirt and a central portion. Becomes thinner and the height becomes higher,
All the solder balls 7 are completely bonded to the second soldering lands 9 without the solder balls 7 in the central portion being separated from the surface of the surface mounting circuit board 8 due to the warp.
【００１２】[0012]
【発明の効果】以上に説明したように、本発明によるＢ
ＧＡ型パッケージの実装構造によれば、ＢＧＡ型パッケ
ージの全ての半田ボールは、面実装用回路基板の第２の
半田付ランドに確実に接合され電気的な接続が行われ、
該半田ボールと第２の半田付ランドとのオープンが発生
することのない、信頼性の高い電気的な接続が容易に達
成される。As described above, B according to the present invention
According to the mounting structure of the GA type package, all the solder balls of the BGA type package are securely joined to the second soldering lands of the surface mounting circuit board to be electrically connected,
It is possible to easily achieve a highly reliable electrical connection without opening the solder ball and the second solder land.
【図１】本発明によるＢＧＡ型パッケージの実装構造の
実装前の断面図である。FIG. 1 is a cross-sectional view of a mounting structure of a BGA type package according to the present invention before mounting.
【図２】本発明によるＢＧＡ型パッケージの実装構造を
示し、（Ａ）は両面プリント基板の一部裏面図で、
（Ｂ）は面実装用回路基板の一部表面図である。FIG. 2 shows a mounting structure of a BGA type package according to the present invention, (A) is a partial rear view of a double-sided printed circuit board,
FIG. 3B is a partial front view of the surface mounting circuit board.
【図３】本発明によるＢＧＡ型パッケージの実装構造の
実装後の断面図である。FIG. 3 is a cross-sectional view of a BGA type package mounting structure according to the present invention after mounting.
【図４】本発明によるＢＧＡ型パッケージの実装構造の
他の実施例を示し、（Ａ）は両面プリント基板の一部裏
面図で、（Ｂ）は面実装用回路基板の一部表面図であ
る。FIG. 4 shows another embodiment of the mounting structure of the BGA type package according to the present invention, (A) is a partial rear view of the double-sided printed circuit board, and (B) is a partial front view of the surface mounting circuit board. is there.
【図５】従来のＢＧＡ型パッケージの実装構造の実装前
の断面図である。FIG. 5 is a sectional view of a conventional BGA type package mounting structure before mounting.
【図６】従来のＢＧＡ型パッケージの実装構造を示し、
（Ａ）は両面プリント基板の一部裏面図で、（Ｂ）は面
実装用回路基板の一部表面である。FIG. 6 shows a mounting structure of a conventional BGA type package,
(A) is a partial rear view of the double-sided printed circuit board, and (B) is a partial front surface of the surface mounting circuit board.
【図７】従来のＢＧＡ型パッケージの実装構造の実装後
の断面図である。FIG. 7 is a cross-sectional view of a conventional BGA type package mounting structure after mounting.
１ ＢＧＡ型パッケージ ２ 両面プリント基板 ３ 部品 ４ ワイヤ ５ 樹脂 ６ 第１の半田付ランド ７ 半田ボール ８ 面実装用回路基板 ９ 第２の半田付ランド 1 BGA type package 2 Double-sided printed circuit board 3 Component 4 Wire 5 Resin 6 First solder land 7 Solder ball 8 Surface mounting circuit board 9 Second solder land
Claims (2)
し、同部品を樹脂モールドし、裏面に多数の第１の半田
付ランドを形成したＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒ
ｒａｙ）型パッケージを、表面に前記半田ボールに対応
する第２の半田付ランドが形成された面実装用回路基板
に実装するものにおいて、前記ＢＧＡ型パッケージの両
面プリント基板の反りに合わせて前記面実装用回路基板
の第２の半田付ランドの面積を可変するようにしたこと
を特徴とするＢＧＡ型パッケージの実装構造。1. A BGA (Ball Grid Ar) in which components are mounted on the front surface of a double-sided printed circuit board, the components are resin-molded, and a large number of first soldering lands are formed on the rear surface.
in a surface mounting circuit board having second soldering lands corresponding to the solder balls formed on the surface thereof, wherein the surface of the BGA type package is matched with the warp of the double-sided printed circuit board. A mounting structure of a BGA type package, wherein an area of a second soldering land of a mounting circuit board is made variable.
面プリント基板の反りの量の１／２となる位置に対応す
る第２の半田付ランドを基準にして、前記反りが下側に
なるに従って漸次広く、上側に反るに従って漸次狭くす
るように形成したことを特徴とする請求項１記載のＢＧ
Ａ型パッケージの実装構造。2. The warp is directed downward with respect to the second solder land corresponding to a position where the area of the second solder land is 1/2 of the warp amount of the double-sided printed circuit board. 2. The BG according to claim 1, wherein the BG is formed so that it gradually widens as it goes, and gradually narrows as it goes upward.
Mounting structure of A type package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153595A JPH098081A (en) | 1995-06-20 | 1995-06-20 | Mounting structure of bga package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7153595A JPH098081A (en) | 1995-06-20 | 1995-06-20 | Mounting structure of bga package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH098081A true JPH098081A (en) | 1997-01-10 |
Family
ID=15565931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7153595A Pending JPH098081A (en) | 1995-06-20 | 1995-06-20 | Mounting structure of bga package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH098081A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100504547B1 (en) * | 2000-12-09 | 2005-08-04 | 주식회사 하이닉스반도체 | structure of stencil for fabricating stack-type package |
| JP2006190902A (en) * | 2005-01-07 | 2006-07-20 | Denso Corp | Method of packaging semiconductor electronic component, and wiring board of semiconductor electronic component |
| US7759799B2 (en) | 2006-01-13 | 2010-07-20 | Nec Electronics Corporation | Substrate and semiconductor device |
| JP2013251303A (en) * | 2012-05-30 | 2013-12-12 | Canon Inc | Semiconductor package and lamination type semiconductor package |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62158865U (en) * | 1986-03-31 | 1987-10-08 | ||
| JPH03190238A (en) * | 1989-12-20 | 1991-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor chip and mounting structure using same chip |
| JPH0722538A (en) * | 1993-07-06 | 1995-01-24 | Citizen Watch Co Ltd | Structure of ball grid array type semiconductor package |
| JPH07193162A (en) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | Ball-grid array semiconductor device and mounting substrate thereof |
| JPH0897322A (en) * | 1994-09-22 | 1996-04-12 | Oki Electric Ind Co Ltd | Semiconductor package |
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
-
1995
- 1995-06-20 JP JP7153595A patent/JPH098081A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62158865U (en) * | 1986-03-31 | 1987-10-08 | ||
| JPH03190238A (en) * | 1989-12-20 | 1991-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor chip and mounting structure using same chip |
| JPH0722538A (en) * | 1993-07-06 | 1995-01-24 | Citizen Watch Co Ltd | Structure of ball grid array type semiconductor package |
| JPH07193162A (en) * | 1993-12-27 | 1995-07-28 | Hitachi Ltd | Ball-grid array semiconductor device and mounting substrate thereof |
| JPH0897322A (en) * | 1994-09-22 | 1996-04-12 | Oki Electric Ind Co Ltd | Semiconductor package |
| JPH08298264A (en) * | 1995-04-27 | 1996-11-12 | Hitachi Ltd | Electronic circuit device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100504547B1 (en) * | 2000-12-09 | 2005-08-04 | 주식회사 하이닉스반도체 | structure of stencil for fabricating stack-type package |
| JP2006190902A (en) * | 2005-01-07 | 2006-07-20 | Denso Corp | Method of packaging semiconductor electronic component, and wiring board of semiconductor electronic component |
| US7759799B2 (en) | 2006-01-13 | 2010-07-20 | Nec Electronics Corporation | Substrate and semiconductor device |
| JP2013251303A (en) * | 2012-05-30 | 2013-12-12 | Canon Inc | Semiconductor package and lamination type semiconductor package |
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